SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
This register is used in LLC topologies to produce the correct Filter Duty output. The Filter output is multiplied by this register to calculate Filter Duty. In the LLC reference firmware (UCD3138LLCEVM-028) it is set to 1/2 of the maximum desired period. In this case, bits 13-0 are used as an unsigned number. To enable this mode, the DPWM must be in Resonant Mode, and the FILTER_DUTY_SEL field in DPWMCTRL2 must be set to a 2.
If FILTER_DUTY_SEL is set to 0 or 1 and the DPWM is in resonant mode, the 16 bit signed contents of the register are added to the Filter Period value, and the result is used for the DPWM Period. This is another option for adjusting the resonant mode timing to match other modes across a mode shift. This mode is not currently used in any topologies.