SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7F030
9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXT_TRIG_MUX_SEL | JTAG_CLK_MUX_SEL | JTAG_DATA_MUX_SEL | SYNC_MUX_SEL | UART_MUX_SEL | PMBUS_MUX_SEL |
R/W-00 | R/W-00 | R/W-00 | R/W-00 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
I/O Pin | 0 | 1 | 2 | 3 |
---|---|---|---|---|
EXT TRIG | EXT TRIG | TCAP | SYNC | PWM-0 |
I/O Pin | 0 | 1 | 2 | 3 |
---|---|---|---|---|
TCK | TCK | TCAP | SYNC | PWM-0 |
I/O Pin | 0 | 1 | 2 | 3 |
---|---|---|---|---|
TDO | TDO | SCI_TX-0 | ALERT | FAULT-0 |
TDI | TDI | SCI_RX-0 | CONTROL | FAULT-1 |
I/O Pin | 0 | 1 | 2 | 3 |
---|---|---|---|---|
SYNC | SYNC | TCAP | EXT TRIG | PWM-0 |
I/O Pin | 0 | 1 |
---|---|---|
SCI_TX-1 | SCI_TX-1 | ALERT |
SCI_RX-1 | SCI_RX-1 | CONTROL |
I/O Pin | 0 | 1 |
---|---|---|
SCL | SCL | SCI_TX-0 |
SDA | SDA | SCI_RX-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
9 | TPWM0_MUX_SEL | R/W | 0 | Pin Mux Select 0 = TMR_PWM_0 via the TMR_PWM_0 (Default) 1 = SYNC via the TMR_PWM_0 |
8 | Reserved | R | 0 | |
7-6 | TCAP1_MUX_SEL | R/W | 0 | Pin Mux Select 0 = MR_CAP_1 function utilized via the TMR_CAP_1 pin (Default) 1 = MR_CAP_1 function utilized via the TDI pin 2 = MR_CAP_1 function utilized via the TDO pin 3 = MR_CAP_1 function utilized via the TMR_CAP_0 pin |
5-4 | TCAP0_MUX_SEL | R/W | 0 | Pin Mux Select 0 = MR_CAP_0 via the TMR_CAP_0 (Default) 1 = MR_CAP_0 via the TDI 2 = TMR_CAP_0 via the TDO 3 = MR_CAP_0 via the TMR_CAP_1 |
3 | Reserved | R | 0 | |
2 | JTAG_MUX_SEL | R/W | 0 | Pin Mux Select 0 = JTAG pins function as JTAG port. TCK/TMS/TDI/TDO 1 = JTAG pins disabled JTAG port functions as SPI port in this mode. TCK -> SPI_CLK TMS -> SPI_CS TDI -> SPI_MISO TDO -> SPI_MOSI (default) Note: This bit is left set at reset if the pflash checksum is valid to disable JTAG for flash code protection. If code protection is desired, and SPI is also desired, it should be left set, and the JTAG pins should be used for SPI. If the pflash checksum is not valid, the bit is cleared to permit JTAG use.] JTAG can also be disabled by the other IOMUX bits which affect the JTAG pins instead. Setting 2 bits which affect the same pin will have unpredictable results. |
1 | RTC_CLK_IN_SEL | R/W | 0 | Pin Mux Select 0 = Input to RTC module clock connected to XTAL_CLK_IN (default) 1 = Input to RTC module clock connected to TCK |
0 | RTC_CLK_OUT_SEL | R/W | 0 | Pin Mux Select 0 = Output of RTC reference clock disabled (default) 1 = Output of RTC reference clock connected to TCK |