SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFD2C
1 | 0 |
TRAIL_OVR | WBUF_ENA |
R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
1 | TRAIL_OVR | R/W | 0 | Write trailing wait state override. 0 = At least one trailing wait state (Default) 1 = TRAIL sets trailing wait states |
0 | WBUF_ENA | R/W | 0 | Write buffer enable. When this bit is 1, the memory controller latches the data and control signals in the first cycle for write operations to the memories and peripherals on the expansion bus and lets the CPU perform other operations. However, the CPU starts a wait state if there is another request before the memory controller finishes. 0 = Write buffer disabled (Disabled) 1 = Write buffer enabled |