SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD44 – 16-bit PWM0 Compare Control Register
Address FFF7FD68 – 16-bit PWM1 Compare Control Register
Address FFF7FD7C – 16-bit PWM2 Compare Control Register
Address FFF7FD90 – 16-bit PWM3 Compare Control Register
Note – Bits indicated with a * are only available for 16 bit timers which have an external pin associated with them. On the UCD3138 and most family members, this is only PWM0 and PWM1. On the UCD3138128 and UCD3138A64 80 pin devices, all 4 timers have an external pin.
12 | 11 | 10 | 9 | 8 |
SHADOW | *PWM_IN | *PWM_OUT | *PWM_OUT_ENA | PWM_OUT_DRV |
R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_OUT_ ACTION1 | PWM_OUT_ ACTION0 | CMP1_ INT_ ENA | CMP1_ INT_ FLAG | CMP0_ INT_ ENA | CMP0_ INT_ FLAG |
R/W-00 | R/W-00 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
12 | SHADOW | R/W | 0 | Controls the update of the 16-bit output compare Registers. 0 = PWM output compare Registers immediately written (Default) 1 = PWM output compare Registers updated through the buffers T16PWMxCMPyDAT after a match occurs in the corresponding Register T16PWMxCMPyDAT. |
11 | *PWM_IN | R | 0 | Input value of PWM pin when configured in PWM mode 0 = Logic level low detected on PWM pin 1 = Logic level high detected on PWM pin |
10 | *PWM_OUT | R/W | 0 | Data to be written into the output latch when PWM_OUT_DRV is high. 0 = Output latch is cleared when PWM_OUT_DRV=1 (Default) 1 = Output latch is set when PWM_OUT_DRV=1 |
9 | *PWM_OUT_ENA | R/W | 0 | FAN-PWM pin configuration 0 = FAN-PWM configured as an input pin (Default) 1 = FAN-PWM configured as an output pin |
8 | *PWM_OUT_DRV | R/W | 0 | Causes the value of the bit PWM_OUT to be written into the output latch. So it is possible to preload the output latch or to use the pin as GPIO. The compare action has priority before the preload function. This bit is always read as ‘0’. 0 = Output latch not affected by the value of PWM_OUT (Default) 1 = Value of OUT written into the output latch |
7-6 | PWM_OUT_ACTION1 | R/W | 00 | These 2 bits select the output action when a compare equal is detected on T16CMP1DAT 00 = No action (Default) 01 = Set pin 10 = Clear pin 11 = Toggle pin |
5-4 | PWM_OUT_ACTION0 | R/W | 00 | Selects the output action when a compare equal is detected on T16CMP0DAT. 00 = No action (Default) 01 = Set pin 10 = Clear pin 11 = Toggle pin |
3 | CMP1_INT_ENA | R/W | 0 | Compare 1 Interrupt Enable 0 = Disables Compare 1 Interrupt (Default) 1 = Enables Compare 1 Interrupt |
2 | CMP1_INT_FLAG | R/W | 0 | Flag which indicates a valid output compare 1 event. This bit is cleared by writing ‘1’ to this bit or by rewriting T16PWMxCMP1DAT. If a clear and a compare event occurs at the same time, the flag will remain high (set has priority versus write clear). 0 = No compare event since last clear 1 = Compare event since last clear |
1 | CMP0_INT_ENA | R/W | 0 | Compare 0 Interrupt Enable 0 = Disables Compare 0 Interrupt (Default) 1 = Enables Compare 0 Interrupt |
0 | CMP0_INT_FLAG | R/W | 0 | Flag which indicates a valid output compare 1 event. This bit is cleared by writing ‘1’ to this bit or by rewriting T16PWMxCMP0DAT. If a clear and a compare event occurs at the same time, the flag will remain high (set has priority versus write clear). 0 = No compare event since last clear 1 = Compare event since last clear |