SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 00050000 – DPWM 3 Control Register 0
Address 00070000 – DPWM 2 Control Register 0
Address 000A0000 – DPWM 1 Control Register 0
Address 000D0000 – DPWM 0 Control Register 0
31 | 28 | 27 | 24 |
PWM_B_INTRA_MUX | PWM_A_INTR4_MUX |
R/W-0000 | R/W-0000 |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CBC_PWM_C _EN | MULTI_MODE _CLA_B_OFF | MULTI_MODE _CLA_A_OFF | CBC_PWM_AB _EN | CBC_ADV _CNT_EN | MIN_DUTY_MODE | MASTER _SYNC_CNTL _SEL |
R/W-000 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-00 | R/W-0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSYNC _SLAVE_EN | D_ENABLE | CBC_SYNC _CUR_LIMIT _EN | RESON_MODE _FIXED _DUTY_EN | PWM_B_FLT _POL | PWM_A_FLT _POL | BLANK_B_EN | BLANK_A_EN |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
7 | 4 | 3 | 2 | 1 | 0 |
PWM_MODE | PWM_B_INV | PWM_A_INV | CLA_EN | PWM_EN |
R/W-0010 | R/W-0 | R/W-0 | R/W-1 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PWM_B_INTRA _MUX | R/W | 0000 | Interchanges DPWM signals post edge generation 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through (DPWM n+1)A 5 = Pass-through (DPWM n+1)B 6 = Pass-through (DPWM n+1)C 7 = Pass-through (DPWM n+2)C 8 = Pass-through (DPWM n+3)C |
27-24 | PWM_A_INTRA _MUX | R/W | 0000 | Combines DPWM signals are prior to HR module 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through (DPWM n+1)A 5 = Pass-through (DPWM n+1)B 6 = Pass-through (DPWM n+1)C 7 = Pass-through (DPWM n+2)C 8 = Pass-through (DPWM n+3)C |
23 | CBC_PWM_C_EN | R/W | 000 | Sets if Fault CBC changes output waveform for PWM-C 0 = PWM-C unaffected by Fault CBC (Default) 1 = PWM-C affected by Fault CBC |
22 | MULTI_MODE _CLA_B_OFF | R/W | 0 | Configures control of PWM B output in Multi-Output Mode when CLA_ENABLE is asserted 0 = PWM B pulse width controlled by Filter Calculation (Default) 1 = PWM B pulse width controlled by Event3 and Event4 registers |
21 | MULTI_MODE _CLA_A_OFF | R/W | 0 | Configures control of PWM A output in Multi-Output Mode when CLA_ENABLE is asserted 0 = PWM A pulse width controlled by Filter Calculation (Default) 1 = PWM A pulse width controlled by Event1 and Event2 registers |
20 | CBC_PWM_AB _EN | R/W | 0 | Sets if Fault CBC changes output waveform for PWM-A and PWM-B 0 = PWM-A and PWM-B unaffected by Fault CBC (Default) 1 = PWM-A and PWM-B affected by Fault CBC |
19 | CBC_ADV_CNT _EN | R/W | 0 | Selects cycle-by-cycle of operation Normal Mode 0 = CBC disabled (Default) 1 = CBC enabled Multi and Resonant Modes 0 = PWM-A and PWM-B operate independently (Default) 1 = PWM-A and PWM-B pulse matching enabled |
18-17 | MIN_DUTY _MODE | R/W | 00 | Minimum Duty Cycle Mode 00 = Suppression of minimum duty cycles is disabled (Default) 01 = CLA value is clamped to zero when below input value is less than MIN_DUTY_LOW 10 = CLA value is clamped to MIN_DUTY_LOW register value when input value is less than MIN_DUTY_LOW |
16 | MASTER_SYNC _CNTL_SEL | R/W | 0 | Configures master sync location 0 = Master Sync controlled by Phase Trigger Register (Default) 1 = Master Sync controlled by CLA value |
15 | MSYNC_SLAVE _EN | R/W | 0 | Multi-Sync Slave Mode Control 0 = PWM not synchronized to another PWM channel (Default) 1 = Enable Multi-Sync Slave Mode, current channel will be slaved from corresponding channel |
14 | D_ENABLE | R/W | 0 | Converts CLA duty value to DPWM as period-CLA duty value 0 = Value used for event calculations if CLA Duty (Default) 1 = Value used for event calculations is period minus CLA duty value |
13 | CBC_SYNC_CUR _LIMIT_EN | R/W | 0 | Sets how current limit affects slave sync 0 = Slave sync is unaffected during current limit (Default) 1 = Slave sync is advanced during current limit. |
12 | RESON_MODE _FIXED_DUTY _EN | R/W | 0 | Configures how duty cycle is controlled in Resonance Mode 0 = Resonant mode duty cycle set by Filter duty (Default) 1 = Resonant mode duty cycle set by Auto Switch High Register |
11 | PWM_B_FLT_POL | R/W | 0 | Sets the fault output polarity during a disable condition (i.e. fault or module disabled) 0 = PWM B fault output polarity is set to low (Default) 1 = PWM B fault output polarity is set to high |
10 | PWM_A_FLT_POL | R/W | 0 | Sets the fault output polarity during a disable condition (i.e. fault or module disabled) 0 = PWM A fault output polarity is set to low (Default) 1 = PWM A fault output polarity is set to high |
9 | BLANK_B_EN | R/W | 0 | Comparator Blanking Window B Enable 0 = Comparator Blanking Window for PWM-B Disabled (Default) 1 = Comparator Blanking Window for PWM-B Enabled |
8 | BLANK_A_EN | R/W | 0 | Comparator Blanking Window A Enable 0 = Comparator Blanking Window for PWM-A Disabled (Default) 1 = Comparator Blanking Window for PWM-B Enabled |
7-4 | PWM_MODE | R/W | 0010 | DPWM Mode 0 = Normal Mode 1 = Resonant Mode 2 = Multi-Output Mode (Default) 3 = Triangular Mode 4 = Leading Mode |
3 | PWM_B_INV | R/W | 0 | PWM B Output Polarity Control 0 = Non-inverted PWM B output (Default) 1 = Inverts PWM B output |
2 | PWM_A_INV | R/W | 0 | PWM A Output Polarity Control 0 = Non-inverted PWM A output (Default) 1 = Inverted PWM A output |
1 | CLA_EN | R/W | 1 | CLA Processing Enable 0 = Generate PWM waveforms from PWM Register values 1 = Enable CLA input (Default) |
0 | PWM_EN | R/W | 0 | PWM Processing Enable 0 = Disable PWM module, outputs zero (Default) 1 = Enable PWM operation |