SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0x0008_0008 – Front End Control 2 Ramp Cycle Register
Address 0x000B_0008 – Front End Control 1 Ramp Cycle Register
Address 0x000E_0008 – Front End Control 0 Ramp Cycle Register
23 | 8 |
DELAY_CYCLES |
R/W-0000 0000 0000 0000 |
7 | 6 | 0 |
Reserved | SWITCH_CYC_PER_STEP |
R-0 | R/W-000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23-8 | DELAY_CYCLES | R/W | 0000 0000 0000 0000 | Configures the number of delay cycles before an initiation of ramp sequence. Each delay cycle consists of n switching cycles, as specified by SWITCH_CYC_PER_STEP (Bits 6-0). Number of delay cycles can vary from 0 to 65535 0 = Ramp starts without delay (Default) 1 = Ramp starts after (1*SWITCH_CYC_PER_STEP) switching cycles 2 = Ramp starts after (2*SWITCH_CYC_PER_STEP) switching cycles ……. 65535 = Ramp starts after (65535*SWITCH_CYC_PER_STEP) switching cycles |
7 | Reserved | R | 0 | |
6-0 | SWITCH_CYC _PER_STEP | R/W | 000 0000 | Selects number of switching cycles per DAC step. Number of subcycles can vary from 1 to 128. 0 = 1 switching cycle per step (Default) 1 = 2 subcycles per cycle 2 = 3 subcycles per cycle ……. 127 = 128 subcycles per cycle |