SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

2.4.3 Probe the XI Clock

Verify the frequency and signal integrity. For link integrity the clock must be 25 MHz ±50 ppm.

If using a crystal as the clock source, probe the CLK_OUT signal. Probing the crystal can change the capacitive loading and therefore change the operational frequency. The default signal on CLK_OUT is a buffered version of the XI reference and will provide a representative measurement.