SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

2.7.1 RGMII Debug

Reference the waveforms in this section verify the expected MAC data and clock signals for RGMII in shift and align modes. To capture data and clock signals, measure close to the receiver end. Note the following requirements for selecting the correct delay mode:

Table 2-7 Selecting the Correct RGMII Delay Mode
If MAC's Configuration is Required PHY Configuration
RGMII Align Mode on TX side RGMII Shift Mode on TX side
RGMII Align Mode on RX side RGMII Shift Mode on RX side
RGMII Shift Mode on TX side RGMII Align Mode on TX side
RGMII Shift Mode on RX side RGMII Align Mode on RX side
Note:

In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086.

RX_D[3:0] Data Aligned with RX_CLK

For the PHY set in RX align mode in 10/100Mbps, probe the clock and data signals on the MAC end and compare to the reference waveforms shown below:

GUID-B2CB1313-1AC3-4FAB-A7FD-EAF4D2D17397-low.png Figure 2-11 10 Mbps Data Aligned with RX_CLK

Verify the frequency of the clock (C2) as 2.5MHz, and the data (C1) being sampled at the rising edge of the clock.

GUID-6DB8B1FC-6095-4AC8-B91E-1FFA2A78F5D6-low.png Figure 2-12 100 Mbps Data Aligned with RX_CLK

Verify the frequency of the clock (C2) as 25MHz, and the data (C1) being sampled at the rising edge of the clock.

GUID-9FAE5EFD-CCD5-4CFF-9489-ED2020F6129B-low.png Figure 2-13 10Mbps Data and Clock Delay in Align Mode

Verify the delay between clock and data is <500ps in align mode.

RX_D[3:0] Data and RX_CLK in Shift Mode

For the PHY set in RX shift mode (0x32) in 10/100Mbps, probe the clock and data signals on the MAC end and compare to the following reference waveforms.

GUID-39DADD63-A604-4E0E-95B6-BB808121821B-low.png Figure 2-14 10 Mbps Data and RX_CLK in Shift Mode (4ns Programmed Delay)

Verify the delay between clock and data is >1ns in shift mode. The programmed delay is relative to the clock's initial position in aligned mode. Measuring the difference in the clock's position before and after setting shift mode yields a value closer to the programmed delay.

TX_D[3:0] and TX_CLK in Shift and Align Mode

For the PHY set in TX shift or align mode, probe the data and clock signals on the PHY end and verify the timing requirements below are met:

For the PHY set in TX shift or align mode, probe the data and clock signals on the PHY end and verify the timing requirements following are met:

PARAMETER MIN NOM MAX UNIT
TskewT Data to Clock output Skew
(at Transmitter)		 –500 0 500 ps
TskewR Data to Clock input Skew
(at Receiver)		 1 1.8 2.6 ns
TsetupT Data to Clock output Setup
(at Transmitter – internal delay)		 1.2 2 ns
TholdT Clock to Data output Hold
(at Transmitter – internal delay)		 1.2 2 ns
TsetupR Data to Clock input Setup
(at Receiver – internal delay)		 1 2 ns
TholdR Clock to Data input Hold
(at Receiver – internal delay)		 1 2 ns
Tcyc Clock Cycle Duration 7.2 8 8.8 ns
Duty_G Duty Cycle for Gigabit 45 50 55%
Duty_T Duty Cycle for 10/100T 40 50 60%
TR Rise Time (20% to 80%) 0.75 ns
TF Fall Time (20% to 80%) 0.75 ns