SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

3.6 Compliance Debug

The following section mainly go over the general guideline on how to debug compliance issue on DP83867PHY.

  • Check the schematic
    • Make sure the Transformer follow data sheet specification in Section 2.3.1.
    • No shorted center taps on transformer
    • Double check on the capacitors on the center taps of transformer
    GUID-621CFEA7-2114-4768-BCE6-5A07A574AA43-low.gif
    • Remove ESD diodes on MDI lines for compliance test
    • Check Rbias value and make sure the value falls in the 1% range
    • Follow the schematic check list recommendation in Section 2.2
  • Check the layout
    • Make sure no clock signal and data signal near the MDI lines
    • Check length matching and impedance matching (100ohms) for MDI lines
    • No vias around the MDI lines
    • Follow the layout checklist in Section 2.2
  • Check the compliance test How to Configure DP8386x for Ethernet Compliance Testing application note. Follow the procedure on the compliance test application note.
  • If all schematic, layout checklist, and compliance test application note do not help, adjusting register 0x00A0, 0x00A1, 0x00A2, 0x00A3 can help with compliance test.
    Note: Default values of 0x00A1 and 0x00A2 registers are trimmed.