If you are encountering an issue with packet loss or CRC errors while using the DP83867, please consider some of these items for debug when using short cables.

Short cables at 1m or less in length for your device can experience signal quality issues. One reason could be that the digital signal processing internally can take too long to converge or can converge to suboptimal filter values at shorter lengths which can result to a bad SNR - Signal to Noise Ratio. This then creates link dropping or potential packet losses which can require you to reset your device before beginning packet transfer again.

We have a register configuration below that can improve the SNR in applications where this marginality is observed. This script allows for a change in the timing bandwidths to make sure the DSP converges correctly:

begin
// Hard Reset
001F 8000
// Threshold for consecutive amount of Idle symbols for Viterbi Idle detector to assert Idle Mode set to 5
0053 2054
// CAGC DC Compensation Disable
00EF 3840
// Master Training Timers - increasing time in different training states
0102 7477
// Master Training Timers - increasing time in different training states
0103 7777
// Master Training Timers - increasing time in different training states
0104 4577
// Timing Loop Bandwidth
010C 7777
// Timing Loop Bandwidth
01C2 7FDE
// Slave Timers - increasing time in different training states
0115 5555
// Slave Timers - increasing time in different training states
0118 0771
// Timing Loop Bandwidth
011D 6DB2
// Timing Loop Bandwidth
011E 3FFB
// Timing Loop Bandwidth
01C3 FFC6
// Timing Loop Bandwidth
01C4 0FC2
// Timing Loop Bandwidth
01C5 0FF0
// FFE Fix
012C 0E81
// Soft Reset
001F 4000
end