SNLA466A August   2024  – October 2024 DP83822I , DP83826E , DP83826I , DP83867E , DP83867IR , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Abbreviation
  5. 2Introduction
  6. 3EMC Emission
    1. 3.1 Radiated Emission
      1. 3.1.1 Test Setup for Radiated Emission Test
      2. 3.1.2 Main Radiated Emission Sources
    2. 3.2 Conducted Emission
      1. 3.2.1 Test Setup for Conducted Emission Test
      2. 3.2.2 Main Conducted Emission Sources
    3. 3.3 Debug Procedure on EMC Emission
      1. 3.3.1 General Debug Procedure
      2. 3.3.2 RE Specific Debug
      3. 3.3.3 CE Specific Debug
  7. 4EMC Immunity Test
    1. 4.1 EMI Passing Criteria
    2. 4.2 Common EMI Knowledge
    3. 4.3 IEC61000 4-2 ESD
      1. 4.3.1 ESD Test Setup
      2. 4.3.2 Possible Root Cause of Failure
      3. 4.3.3 Debug Procedure
        1. 4.3.3.1 Follow the Test Setup
        2. 4.3.3.2 Remove External Factors on Cable or Link Partner
        3. 4.3.3.3 Areas to Explore to Improve ESD Performance
          1. 4.3.3.3.1 Air or Capacitive Coupling Discharge ESD Recommendations
          2. 4.3.3.3.2 Direct Contact Discharge ESD Recommendation
        4. 4.3.3.4 Schematic and Layout Recommendations
    4. 4.4 IEC 61000 4-3 RI
      1. 4.4.1 RI Test Setup
      2. 4.4.2 Possible Root Cause of Failure
      3. 4.4.3 Debug Procedure
        1. 4.4.3.1 Follow RI Test Setup
        2. 4.4.3.2 Remove External Factor on Cable or Link Partner
        3. 4.4.3.3 Found out Main Emission Area
        4. 4.4.3.4 Schematic and Layout Recommendation
    5. 4.5 IEC 61000 4-4 EFT
      1. 4.5.1 EFT Test Setup
      2. 4.5.2 Possible Root Cause of Failure
      3. 4.5.3 Debug Procedure
        1. 4.5.3.1 Follow EFT Test Setup
        2. 4.5.3.2 Remove External Factor on Cable or Link Parnter
        3. 4.5.3.3 Areas to Explore to Improve EFT Performance
        4. 4.5.3.4 Schematic and Layout Recommendation
    6. 4.6 IEC 61000 4-5 Surge
      1. 4.6.1 Surge Test Setup
      2. 4.6.2 Possible Root Cause of Failure
      3. 4.6.3 Debug Procedure
        1. 4.6.3.1 Follow Surge Test Setup
        2. 4.6.3.2 Remove External Factor on Cable or Link Partner
        3. 4.6.3.3 Area to Explore to Improve Surge Performance
        4. 4.6.3.4 Schematic and Layout Recommendation
    7. 4.7 IEC 61000 4-6 CI
      1. 4.7.1 CI Test Setup
      2. 4.7.2 Possible Root Cause of Failure
      3. 4.7.3 Debug Procedure
        1. 4.7.3.1 Follow CI Test Setup
        2. 4.7.3.2 Remove External Factors on Cable or Link Partner
        3. 4.7.3.3 Areas to Explore to Improve CI Performance
        4. 4.7.3.4 Schematic and Layout Recommendation
  8. 5Schematic and Layout Recommendation for All EMC, EMI Tests
    1. 5.1 Schematic Recommendation
    2. 5.2 Layout Recommendation
  9. 6Summary
  10. 7References
  11. 8Revision History

IEC 61000 4-5 Surge

IEC61000-4-5 is also known as the surge immunity test. This mainly tests the immunity of electrical equipment to a unidirectional surge caused by overvoltage from switching or transients. Unlike ESD and EFT tests, Surge test involves an injection of high energy or power pulses into the system. These pulses are in the millisecond range, unlike the nanosecond pulse range for ESD and EFT tests. The surge test is defined by the ability of electrical equipment to withstand high energy pulses without any damage in the device or system application. The system needs to recover automatically without any power cycle or hardware reset after the surge injection. Unlike other EMI tests, where no packet errors or loss is allowed in the system, surge tests mainly look for Class B performance. For this, packet errors or loss is allowed, but the PHY must automatically recover by itself.

Within IEC61000 4-5 Surge test, there are different tests defined for: Open circuit, Short circuit, and Telecom ports. Both Open and Short circuit testing is mainly used for power surge tests. There are Section 5 tests that can improve the power circuitry performance. However, power EMC tests depend on power ICs other than Ethernet. Therefore, we can mainly focus on the signal ports' surge test.

In signal or telecom port surge tests, there are different test setups for Shielded and Unshielded cables. Here are the differences between the two test setups:

Both types of surge test setups noted above simulate real life scenarios. Compared to shielded cable surge tests, unshielded cable surge tests normally give worse performance. This is due to the noise directly injecting into the cable. Again, Surge test is a high power noise injection into the system. Having a potential path for high power noise to inject into the signal lines is not always recommended for the design. In industrial applications, most customers use shielded cables. The following section focus on shielded cables or line to ground surge tests.

Surge Test level:

  • Level 1: ±0.5kV (line to line), ±1kV (line to ground)
  • Level 2: ±1kV (line to line), ±2kV (line to ground)
  • Level 3: ±2kV (line to line), ±4kV (line to ground)
Note: Class A, Class B, and Class C depends on the customer's requirements. Normally, engineers are looking for Class B performance for surge test. The purpose of surge test is to verify the system is able to recover automatically after huge energy is injected into the system.

Normally line to ground surge test have higher passing level than line to line surge test.

Surge waveform:

For Signal and Telecom port surge tests, the pulse width is 1.4ms with 10us Front time. The pulse is a high-power pulse injected into the system:

 Surge Test WaveformFigure 4-8 Surge Test Waveform