SNLU297 May   2021 DS320PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1  DS320PR810 5-Level I/O Control Inputs
    2. 2.2  DS320PR810 Modes of Operation
    3. 2.3  DS320PR810 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR810 Equalization Control
    5. 2.5  DS320PR810 RX Detect State Machine
    6. 2.6  DS320PR810 DC Gain Control
    7. 2.7  DS320PR810 EVM Global Controls
    8. 2.8  DS320PR810EVM Downstream Devices Control
    9. 2.9  DS320PR810EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus Slave Mode)
  4. 3Test Setup and Results
  5. 4Schematics
  6. 5Board Layout
  7. 6Bill of Materials
  8. 7References

2.5 DS320PR810 RX Detect State Machine

Each DS320PR810 deploys an RX Detect state machine that governs the RX detection cycle as defined in the PCI Express specification. At power up or after a manually triggered event, the redriver determines whether or not a valid PCI Express termination is present at the far end of the link. The RX_DET pin of DS320PR810 provides additional flexibility to system designers to appropriately set the device in their desired mode, according to Table 2-5.

Table 2-5 Four-Level Control Pin Settings
PD0 PIN LEVEL PD1 PIN LEVEL RX_DET PIN LEVEL Channels 0-3 RXCommon-mode Impedance Channels 4-7 RXCommon-mode Impedance DESCRIPTION
L L L0 Always 50 Ω Always 50 Ω PCI Express RX detection state machine is disabled. Recommended for non-PCI Express use cases.
L L L1 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Outputs poll until 3 consecutive valid detections.
L L L2 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Outputs poll until 2 consecutive valid detections.
L L L3 N/A N/A Reserved
L L L4(Float) Pre Detect: Hi-Z
Post Detect: 50 Ω		 Pre Detect: Hi-Z
Post Detect: 50 Ω		 TX polls every ~150us until valid termination is detected. Reset by asserting PD0/1 high for 200us then low.
H L X Hi-Z Pre Detect: Hi-Z
Post Detect: 50 Ω		 Reset Channels 0-3 signal path.
L H X Pre Detect: Hi-Z
Post Detect: 50 Ω		 Hi-Z Reset Channels 4-7 signal path.
H H X Hi-Z Hi-Z Reset all channels.