SNVAA05 October   2020 LM60430-Q1 , LM60440-Q1

 

  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the LM60430-Q1 and LM60440-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of critical functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the LM60430-Q1 and LM60440-Q1 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the LM60430-Q1 and LM60440-Q1 data sheet.

GUID-20200922-CA0I-RQ2M-RZZF-LC9SG9WHVSJZ-low.pngFigure 4-1 Pin Diagram: LM60430-Q1, LM60440-Q1

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin NoDescription of Potential Failure Effect(s)Failure Effect Class
PGND1Normal OperationD
VIN2,10Input supply would collapse and as a result there will be no output voltageB
SW3,12Damage to power switches likely; loss of VOUT regulationA
BOOT4No switchingB
VCC5No switching; loss of all functionalityB
AGND6Normal operationD
FB7Loss of VOUT regulationB
PG8Loss of power good indicator if usedC
EN9IC will not startB
PGND11Normal operationD
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin NoDescription of Potential Failure Effect(s)Failure Effect Class
PGND1Vout normal; current distribution in power switched will be affected, potentially degrading jitter/EMI/reliabilityC
VIN2,10Vout normal; current distribution in power switched will be affected, potentially degrading jitter/EMI/reliabilityC
SW3Loss of VOUT regulationB
BOOT4No switchingB
VCC5Internal VCC supply will be unstable without VCC bypass capacitor; abs max maybe exceeded; possibly loss of VOUT regulationA
AGND6May increase noise/jitter and possibly loss of regulationB
FB7Loss of VOUT regulationB
PG8Loss of power good indicator if usedC
EN9Possible loss of VOUT regulationB
PGND11Vout normal; current distribution in power switched will be affected, potentially degrading jitter/EMI/reliabilitC
SW12No switching, if CB returns via this pinB
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin NoDescription of Potential Failure Effect(s)Failure Effect Class
PGND1Input supply would collapse and as a result there will be no output voltageB
VIN2Damage to power siwtches likely; loss of VOUT regulationA
SW3Loss of VOUT regulationB
BOOT4No switchingB
VCC5No switching; loss of all functionalityB
AGND6Loss of VOUT regulationB
FB7Abs max may be exceeded, and loss of VOUT regulationA
PG8Abs max may be exceeded, and possibly unable to startA
EN9Normal operation; IC will not shut downC
VIN10Input supply would collapse and as a result there will be no output voltageB
PGND11Damage to the power switches likely; loss of VOUT regulationA
SW12Damage to the power switches likely; loss of VOUT regulationA
Table 4-5 Pin FMA for Device Pins Short-Circuited to Input
Pin NamePin NoDescription of Potential Failure Effect(s)Failure Effect Class
PGND1Input supply would collapse and as a result there will be no output voltageB
VIN2,10Normal operationD
SW3,12Damage to the power switches likely; loss of VOUT regulationA
BOOT4Damage to the driver circuitry likely; loss of VOUT regulationA
VCC5Abs max may be exceededA
AGND6Input supply would collapse and as a result there will be no output voltageB
FB7Abs max may be exceeded; loss of VOUT regulationA
PG8Abs max may be exceededA
EN9Normal operation; IC will not shut offC
PGND11Input supply would collapse and as a result there will be no output voltageB