SNVAA92 November   2023 LM63625-Q1 , TPS37-Q1 , TPS3703-Q1 , TPS3850-Q1

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2Power Designs for Safety MCUs With Functional Safety Requirements
  5. 3ASIL B Power-Supply Design Example and FMEDA Analysis
    1. 3.1 Functional Safety Requirements
    2. 3.2 Proposed Power Design
    3. 3.3 FMD and Pin FMA
    4. 3.4 LM63625-Q1 and TPS37A-Q1 FMEDA Analysis at the Die Level
    5. 3.5 LM63625-Q1 and TPS37A-Q1 FMEDA Analysis at the Pin Level
      1.      11
    6. 3.6 Total FMEDA Analysis of the LM63625-Q1 and TPS37A-Q1
  6. 4Summary
  7. 5Additional Resources

3.4 LM63625-Q1 and TPS37A-Q1 FMEDA Analysis at the Die Level

The calculations in the following sections are based on IEC TR 62380. The FMEDA tables list the die and package faults separately.

Table 3-2 shows the calculation of the single-point fault metric (SPFM) and latent fault metric (LFM) for the LM63625-Q1 and TPS37A-Q1 at the die level to prove that the design meets ASIL B criteria: SPFM ≥ 90% and LFM ≥ 60%, leaving any passive components needed for this circuitry out of consideration.

Table 3-2 LM63625-Q1 and TPS37A-Q1 FMEDA Analysis at the Die Level
Single Point Fault Latent Fault
Component Failure Rate Safety-related component to be considered in the calculation? Failure Mode Failure Mode Distribution Failure mode that has the potential to violate the safety goal in absence of safety mechanisms Safety mechanism allowing to prevent the failure mode from violating safety goal Failure mode coverage with regard to violation of safety goal Residual or Single-Point Fault Failure Rate Failure mode that can lead to the violation of safety goal in combination with an independent failure of another component Detection means? Safety mechanism allowing to prevent the failure mode from being latent? Failure mode coverage with respect to latent failures Latent multiple-point fault failure rate
FIT SR/NSR % V/NV SM/NSM % FIT V/NV SM/NSM % FIT
LM63625-Q1 7.00 SR SW no output 35% NV 0.0000 NV 0.00
7.00 SR SW output not in specification - voltage or timing 45% V SM 99% 0.0315 V SM 100% 0.00
7.00 SR SW driver FET suck on 10% V SM 99% 0.0070 V SM 100% 0.00
7.00 SR RESET false trip or fails to trip 5% NV 0.0000 NV 0.00
7.00 SR Short circuit any two pins 5% V SM 99% 0.0035 V SM 100% 0.00
TPS37A-Q1 2.00 SR RESET1/ fails to trip 8% NV 0.0000 V NSM 0% 0.16
2.00 SR RESET1/ false trip 8% NV 0.0000 NV 0.00
2.00 SR RESET1/ trip outside specification (voltage or time) 31% NV 0.0000 V NSM 0% 0.62
2.00 SR RESET1/ delay outside specification 3% NV 0.0000 NV 0.00
2.00 SR RESET2/ fails to trip 8% NV 0.0000 V NSM 0% 0.16
2.00 SR RESET2/ false trip 8% NV 0.0000 NV 0.00
2.00 SR RESET2/ trip outside specification (voltage or time) 31% NV 0.0000 V NSM 0% 0.62
2.00 SR RESET2/ delay outside specification 3% NV 0.0000 NV 0.00
9.0000 0.0420 1.5600
Total failure rate (die): 9 FIT S i n g l e   P o i n t   F a u l t   M e t r i c = 1 - ∑ λ S P F + λ R F ∑ λ S R L a t e n t   F a u l t   M e t r i c = 1 - ∑ λ M P F . L a t e n t ∑ λ S R - ∑ λ S P F + λ R F
Total residual and single-point failure rate: 0.042 FIT
Total latent fault: 1.56 FIT
SPFM = 1 – (0.042 / 9) = 99.5%
LFM = 1 – (1.56 / (9 – 0.042)) = 82.6%