SNVU773A March   2021  – April 2022 LM25148 , LM25148-Q1 , LM25149 , LM25149-Q1 , LM5148 , LM5148-Q1 , LM5149 , LM5149-Q1

 

  1.   Trademarks
  2. 1High Density EVM Description
    1. 1.1 Typical Applications
    2. 1.2 Features and Electrical Performance
  3. 2EVM Characteristics
  4. 3Application Circuit Diagram
  5. 4EVM Photo
  6. 5Test Setup and Procedure
    1. 5.1 EVM Connections
    2. 5.2 Test Equipment
    3. 5.3 Recommended Test Setup
      1. 5.3.1 Input Connections
      2. 5.3.2 Output Connections
    4. 5.4 Test Procedure
      1. 5.4.1 Line and Load Regulation, Efficiency
  7. 6Test Data and Performance Curves
    1. 6.1 Conversion Efficiency
    2. 6.2 Operating Waveforms
      1. 6.2.1 Switching
      2. 6.2.2 Load Transient Response
      3. 6.2.3 Line Transient Response
      4. 6.2.4 Start-Up and Shutdown With ENABLE ON and OFF
      5. 6.2.5 Start-Up and Shutdown with EN Tied to VIN
    3. 6.3 Bode Plot
    4. 6.4 CISPR 25 EMI Performance
    5. 6.5 Thermal Performance
  8. 7EVM Documentation
    1. 7.1 Schematic
    2. 7.2 Bill of Materials
    3. 7.3 PCB Layout
    4. 7.4 Component Drawings
  9. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 PCB Layout Resources
        2. 8.2.1.2 Thermal Design Resources
  10. 9Revision History

1.2 Features and Electrical Performance

  • Wide input voltage operating range of 5.5 V to 36 V

  • 1% accurate fixed 3.3 V, 5 V, or adjustable output down to 0.8 V

  • Switching frequency of 2.1 MHz externally synchronizable up or down by 20%
  • Full-load efficiency of 92.8% at VIN = 12 V
  • 12-µA controller standby current at VIN = 12 V
  • Optimized for ultra-low EMI
    • Dual-Random Spread Spectrum and Active EMI filtering
    • Meets CISPR 25 and UNECE Reg 10 EMI standards
  • Peak current-mode control architecture provides fast line and load transient response
    • Integrated slope compensation adaptive with switching frequency
    • Forced PWM (FPWM) or Pulsed-Frequency Modulation (PFM) operation
    • Optional internal or external loop compensation
  • Integrated high-side and low-side power MOSFET gate drivers
    • 2.2-A and 3.2-A sink and source gate drive current capability
    • 13-ns adaptive dead-time control reduces power dissipation and MOSFET temperature rise
  • Overcurrent protection (OCP) with hiccup mode for sustained overload conditions
  • SYNCOUT signal 180° out-of-phase with internal clock
  • Power Good signal with 100-kΩ pullup resistor to VCC
  • Internal 3-ms soft start
  • Fully assembled, tested, and proven PCB layout with 70-mm × 40-mm total footprint