SPRAA85E November   2005  – December 2017 SM320F2812 , SM320F2812-EP , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F2801 , TMS320F2801-Q1 , TMS320F2802 , TMS320F2802-Q1 , TMS320F28044 , TMS320F2806 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1 , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320R2811

 

  1.   Programming TMS320x28xx and TMS320x28xxx Peripherals in C/C++
    1.     Trademarks
    2. 1  Introduction
    3. 2  Traditional #define Approach
      1.      Example 1. Traditional #define Macros
      2.      Example 2. Accessing Registers Using #define Macros
    4. 3  Bit Field and Register-File Structure Approach
      1. 3.1 Defining A Register-File Structure
        1.       Example 3. SCI Register-File Structure Definition
        2.       Example 4. SCI Register-File Structure Variables
      2. 3.2 Using the DATA_SECTION Pragma to Map a Register-File Structure to Memory
        1.       Example 5. Assigning Variables to Data Sections
        2.       Example 6. Mapping Data Sections to Register Memory Locations
        3.       Example 7. Accessing a Member of the SCI Register-File Structure
      3. 3.3 Adding Bit-Field Definitions
        1.       Example 8. SCI Control Registers Defined Using Bit Fields
      4. 3.4 Using Unions
        1.       Example 9. Union Definition to Provide Access to Bit Fields and the Whole Register
        2.       Example 10. SCI Register-File Structure Using Unions
        3.       Example 11. Accessing Bit Fields in C/C++
    5. 4  Bit Field and Register-File Structure Advantages
    6. 5  Code Size and Performance Using Bit Fields
      1.      Example 12. TMS320x280x PCLKCR0 Bit-Field Definition
      2.      Example 13. Assembly Code Generated by Bit Field Accesses
      3.      Example 14. Optimization Using the .all Union Member
      4.      Example 15. Optimization Using a Shadow Register
    7. 6  Read-Modify-Write Considerations When Using Bit Fields
      1.      Example 16. A Few Read-Modify-Write Operations
      2. 6.1 Registers That Hardware Can Modify During Read-Modify-Write Operations
        1. 6.1.1 PIEIFRx Registers
          1.        Example 17. Clearing PIEIFRx (x = 1, 2...12) Registers
        2. 6.1.2 GPxDAT Registers
          1.        Example 18. Read-Modify-Write Effects on GPxDAT Registers
          2.        Example 19. Using GPxSET and GPxCLEAR Registers
      3. 6.2 Registers With Write 1-to-Clear Bits.
        1.       Example 20. Read-Modify-Write Operation Inadvertently Modifies Write 1-to-Clear Bits (TCR[TIF])
        2.       Example 21. Using a Shadow Register to Preserve Write 1-to-Clear Bits
      4. 6.3 Register Bits Requiring a Specific Value
        1.       Example 22. Watchdog Check Bits (WDCR[WDCHK])
      5. 6.4 Read-Modify-Write Sensitive Registers
    8. 7  Special Case Peripherals
      1. 7.1 eCAN Control Registers
        1.       Example 23. Invalid eCAN Control Register 16-Bit Write
        2.       Example 24. Using a Shadow Register to Force a 32-Bit Access
      2. 7.2 Byte Peripheral Registers
        1.       Example 25. Invalid Byte Peripheral Register Access
        2.       Example 26. Byte Peripheral Register Access Using “byte_peripheral” Attribute
    9. 8  C2000 Peripheral Driver Library Approach
      1. 8.1 Using the Peripheral Driver Library
        1.       Example 27. SCI-A Driverlib Function Prototype
          1.        Example 28. SCI-A Configuration Using the Driverlib
      2. 8.2 Construction of a Driver Library Function
        1.       Example 29. SCI Register Description Header File (hw_sci.h)
          1.        Example 30. SCI Function Implementation
      3. 8.3 Peripheral Driver Library Advantages
    10. 9  Code Size and Performance Using Driverlib
      1.      Example 31. Inlined ADC_readResult() Function Calls
      2.      Example 32. ADC Function Implementation to be Optimized
      3.      Example 33. Inlined ADC_setupSOC() Function Call
    11. 10 Comparing and Combining Approaches
      1.      Example 34. CPU Timer Bit-Field (Left) and Driverlib (Right) Disassembly Comparison
      2.      Example 35. ADC Bit-Field (Left) and Driverlib (Right) Disassembly Comparison
    12. 11 References
  2.   Revision History

Example 27. SCI-A Driverlib Function Prototype

///////////////////////////////////////////////////////////////////// // // Snippet from hw_memmap.h showing base address #defines // ///////////////////////////////////////////////////////////////////// ... #define SCIA_BASE 0x00007050U // SCI A Registers #define SCIB_BASE 0x00007750U // SCI B Registers ... ///////////////////////////////////////////////////////////////////// // // Snippet from sci.h showing API description and base parameter // ///////////////////////////////////////////////////////////////////// // //! Sets the FIFO interrupt level at which interrupts are generated. //! //! \param base is the base address of the SCI port. //! //! \param txLevel is the transmit FIFO interrupt level, specified as //! one of the following: //! SCI_FIFO_TX0, SCI_FIFO_TX1, SCI_FIFO_TX2, ... or SCI_FIFO_TX16. //! //! \param rxLevel is the receive FIFO interrupt level, specified as one //! of the following: //! SCI_FIFO_RX0, SCI_FIFO_RX1, SCI_FIFO_RX2, ... or SCI_FIFO_RX16. //! //! This function sets the FIFO level at which transmit and receive //! interrupts are generated. //! //! \return None. // static inline void SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, SCI_RxFIFOLevel rxLevel)

For the other parameters, #defines or enumerated types are often supplied to provide a readable way to specify the desired value. Typically #defines are used when a parameter is a uint32_t or uint16_t and able to take a bitwise OR of several #defined values. Enumerated types are used when only a single value is applicable.

These values determine what is written to the peripheral registers to configure the peripheral. The function will determine which register or registers to write to and what value to write. The function will also perform any necessary EALLOW or EDIS instructions. Since these details are hidden by the functions, it is not required for the user to have complete knowledge of the hardware to program a peripheral. Example 28 shows code that could be found in a user application that demonstrates this; given a source clock rate and a desired baud rate, the function calculates the necessary prescalers and writes them to the appropriate registers.