SPRAA85E November 2005 – December 2017 SM320F2812 , SM320F2812-EP , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F2801 , TMS320F2801-Q1 , TMS320F2802 , TMS320F2802-Q1 , TMS320F28044 , TMS320F2806 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1 , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320R2811
/********************************************************************
* SCI header file
********************************************************************/
//---------------------------------------------------------------------------
// SCI Register File:
//
struct SCI_REGS {
union SCICCR_REG SCICCR; // Communications control register
union SCICTL1_REG SCICTL1; // Control register 1
Uint16 SCIHBAUD; // Baud rate (high) register
Uint16 SCILBAUD; // Baud rate (low) register
union SCICTL2_REG SCICTL2; // Control register 2
union SCIRXST_REG SCIRXST; // Receive status register
Uint16 SCIRXEMU; // Receive emulation buffer register
union SCIRXBUF_REG SCIRXBUF; // Receive data buffer
Uint16 rsvd1; // reserved
Uint16 SCITXBUF; // Transmit data buffer
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
union SCIFFRX_REG SCIFFRX; // FIFO receive register
union SCIFFCT_REG SCIFFCT; // FIFO control register
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
union SCIPRI_REG SCIPRI; // FIFO Priority control
};
As with other structures, each member (.all or .bit) is accessed using the dot operator in C/C++ as shown in Example 11. When the .all member is specified, the entire register is accessed. When the .bit member is specified, then the defined bit fields can be directly accessed.
NOTE
Writing to a bit field has the appearance of writing to only the specified field. In reality, however, the CPU performs what is called a read-modify-write operation; the entire register is read, its contents are modified and the entire value is written back. Possible side effects of read-modify-write instructions are discussed in Section 6.