VREFHI is sampled several times during each conversion of a SAR ADC, and high-current transients occur when the ADC’s internal capacitor array is switched and charged as the bit decisions are made. VREFHI must remain stable and settle appropriately to avoid conversion errors. Because of these dynamic currents, the reference pin requires good decoupling using a high-quality bypass capacitor (C_REF). In the below figure, the inductance between the reference capacitor and the REF pin is minimized by placing the capacitor close to the pin and connecting it with wide traces. The design also uses a small 0.1-Ω series resistor (R_REF) to keep the overall impedance low and constant at high frequencies.

Figure 1-1 Example Layout