SPRACC0A November   2017  – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Trademarks
  2. 1 Introduction and Scope
  3. 2 SRAM Bit Array
  4. 3 Sources of SRAM Failures
    1. 3.1 Manufacturing Defects
      1. 3.1.1 Time Zero Fails
      2. 3.1.2 Latent Fails
    2. 3.2 Circuit Drift With Usage
    3. 3.3 Circuit Overstress
    4. 3.4 Soft Errors
      1. 3.4.1 Radioactive Events
      2. 3.4.2 Dynamic Voltage Events
      3. 3.4.3 Summary of Error Sources
  5. 4 Methods for Managing Memory Failures in Electronic Systems
    1. 4.1 Start-Up Testing
    2. 4.2 In-System Testing
    3. 4.3 Parity Detection
    4. 4.4 Error Detection and Correction (EDAC)
    5. 4.5 Redundancy
  6. 5 Comparisons and Conclusions
  7. 6  C2000 Memory Types Example
    1. 6.1 TMS320F2837xD
  8. 7 Memory Types
    1. 7.1 Dedicated RAM (Mx and Dx RAM)
    2. 7.2 Local Shared RAM (LSx RAM)
    3. 7.3 Global Shared RAM (GSx RAM)
    4. 7.4 CPU Message RAM (CPU MSGRAM)
    5. 7.5 CLA Message RAM (CLA MSGRAM)
  9. 8 Summary
  10. 9 References
  11. 10Revision History

4.2 In-System Testing

In-system testing involves testing a targeted circuit while the system is in full operation. This involves taking a time slice for the CPU’s attention to test a portion of the circuitry. This time slice must be small enough to not affect the CPU’s system responsibility. In a real-time control system this can be restrictive. With respect to the Safe State perspective, the complete range of the SRAM must be tested within each safety interval.

In-system testing of SRAM involves:

  • Context Save of the targeted SRAM
  • Running a SRAM test algorithm over the SRAM
  • Restoring the previous context of the SRAM

This has to be done before the system requires access to the SRAM under test. It is difficult to do this for a full SRAM instance within a device. However, it is possible to do this on a small slice of SRAM at a time, for example 16 or 32 words. As stated in Section 3.1.1, most defect related failures in-system can be detected with a simple March algorithm (March13n or even March7). In newer process nodes (45 nm and smaller), there is a need for more advanced algorithms to get the same coverage.

This method does not detect a failure on a system read of the SRAM, but can catch errors developing in the memory before the system reads a failing location. The method is used in cases where the SRAM in devices has no other detection methods available.