SPRACC0A November 2017 – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1
In closing, here are a couple more points of clarification.
Many newer chips in the newest semiconductor process nodes make more extensive use of EDAC in their SRAMs than earlier devices in older process nodes. While this does provide better coverage than older devices with parity or no automated detection in the memory, it may be due more to process requirements than safety. The newer process nodes, with more aggressive structural geometries, are more susceptible to both soft errors and process degradation and it is necessary to add EDAC to meet reasonable device life times. This is not a concern for the newer devices so long as they include the EDAC. However, the need for EDAC is greater in devices making use of these new processes.
A second point to consider is the available history for the process node. If the targeted market requires a 10 year life time, then from a safety perspective, it is advantageous to have greater than 10 years of volume production in the process node that services markets while carefully monitoring field failures. This is because the advancements in each new process bring with them new and unique problems.