SPRACP4A December 2019 – June 2024 AM67 , AM67A , AM68 , AM69 , DRA829J , DRA829V , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VM , TDA4VM-Q1
The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 4-2. This involves running a channel simulation for the serial link. The methodology uses IBIS-AMI (Algorithmic Modeling Interface) models for the Tx/Rx blocks. The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators. This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.