6 Revision History
Changes from January 1, 2023 to November 2, 2024 (from Revision A (January 2023) to Revision B (November 2024))
- Specified power aware simulation should be used to determine
decoupling capacitor count and total valuesGo
- Clarified DDR4 supported topologies.Go
- Updated DDR4 Schematics to include info on VTT and dual
rankGo
- Updated info on DDR4 Signal TerminationGo
- Updated VTT as optional for point to point designsGo
- Updated CK and ADDR_CTRL Routing
Limits and Routing Specifications
tableGo
- Updated Data Group Routing Limits and Data Group Routing Specifications
tables.Go
- Added support for DDR4 data bit swapping and byte swappingGo
- Clarified LPDDR4 supported topologies.Go
- Updated LPDDR4 Data Group TopologiesGo
- Updated LPDDR4 CK and ADDR_CTRL Routing
specificationsGo
- Updated LPDDR4 Data Group Routing Specifications.Go
- Allowing DQ/DM bit swapping and byte swapping.Go
- Added LPDDR4 Simulation section for AM62xGo
- Removed
Waveform Quality section (ring-back
margins).Go
- LPDDR4-3733 Read eye mask VdlVW corrected to 140mV in Table 4-3.Go
- Add eye masks for LPDDR4-1600Go
- Added AM62Px SK EVM stackup
into Table 4-6
.Go
- Corrected Impedance Mismatch calculation in Table 4-11.Go
- Removed Minimum ring-back margins at high/low levels
(JEDEC)Go
- Added package delay section.Go