GLBCE module needs certain number of cycles (554 cycles) of PCLK input after reset to regenerate the default table internally. Therefore, it requires special procedure after reset process (HW reset, ISP-Top level SW reset, and GLBCE level SW reset).
Typical procedure is as following, but other sources of PCLK may be used
- SW make sure PCLK is not provided to GLBCE right after reset (ISS Video Mux [VMUX] does not connect CAL and GLBCE)
- After GLBCE is reset, wait until GLBCE returns to normal status
- SW write ISP_SWT_SEL[9:8] GLBCE_SEL=1 (select GLBCE-CAL at ISP-Top) and Write "1" to ISP5_CTRL[19] GLBCE_CLK_ENABLE (Enable GLBCE clock)
- CAL starts generating PCLK in a dummy frame
- VMUX is switched to feed PCLK from CAL to GLBCE (This is after HS/VS, so GLBCE won't see them)
- Eventually GLBCE finishes initialization process, and generates filtering_done interrupt after ~5500 cycles (accurate cycle should be updated after DV completion). GLBCE is ready.
- SW detects filtering_done and stops PCLK generation by CAL
- SW may switch GLBCE_SEL to other values. Move to the next steps