SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | GLBCE eFuse enable. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | KEY2_EN | KEY1_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1 | KEY2_EN | EFUSE enable Equals 1 when ISP5_EFUSE6_EN = 1. Equals 0 otherwise. 1'b1 means GLBCE Decomapding function is present in HW 1'b0 means GLBCE Decomapding function is not present in HW | R | 0x1 |
0x0: GLBCE Disable | ||||
0x1: GLBCE Enable | ||||
0 | KEY1_EN | EFUSE Enable. Equals 1 when ISP5_EFUSE5_EN = 1. Equals 0 otherwise. 1'b1 means GLBCE function is present in HW 1'b0 means GLBCE function is not present in HW | R | 0x1 |
0x0: GLBCE Disable | ||||
0x1: GLBCE Enable |
ISS ISP |
Address Offset | 0x0000 0004 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Controls the Switch block in ISP-Top. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GLBCE_SEL | RESERVED | DPC_SEL | RESERVED | NSF3V_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9:8 | GLBCE_SEL | Select GLBCE Module processing order | RW | 0x0 |
0x0: Disable data passing to GLBCE ISP6 works same way as ISP6 without GLBCE function. | ||||
0x1: Enable GLBCE with CAL | ||||
0x3: reserved | ||||
0x2: Enable GLBCE before IPIPE (VP-2 path) | ||||
7:5 | RESERVED | R | 0x0 | |
4 | DPC_SEL | RW | 0x0 | |
0x0: DPC before NSF3V is disabled. | ||||
0x1: DPC in NSF3V path is enabled. valid only if NSF3V_SEL=1 or 2. To actually activate the function, dpc function in IPIPE must be properly configured. | ||||
3:2 | RESERVED | R | 0x0 | |
1:0 | NSF3V_SEL | Select NSF3V Module processing order | RW | 0x0 |
0x0: Disable data passing to NSF3V. ISP6 works same way as ISP6 without NSF3V function. | ||||
0x1: Enable NSF3V with CAL | ||||
0x3: Reserved | ||||
0x2: Enable NSF3V before ISIF in VP-1 path |
Address Offset | 0x0000 000C | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Note: This entry is not shadowed | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INPMOD | RESERVED | DPOL | RESERVED | HDPOL | VDPOL | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:14 | RESERVED | R | 0x0 | |
13:12 | INPMOD | Data input mode for NSF3V (VP-1 and CAL-1) For CAL, this value must be either 0 (RAW) or 1 (8bit) This bit can be changed only when NSF3V is in idle. When switching to 16bit-YCbCr, PCLK must be equal to or less than 1/2 of FCLK. | RW | 0x0 |
0x0: RAW data | ||||
0x1: YCbCr 16bit - VP-1 YUV422 16bit YUV420-Y 8bit (although this is 8bit, it is treated as 16bit mode since Y is mapeed to MSB 8bit of 16bit bus) - CAL This value is not valid | ||||
0x3: Reserved | ||||
0x2: YCbCr 8bit - CAL YUV422 8bit YUV420-Y 8bit YUV420-C 8bit - VP-1: YUV422 8bit YUV420-C 8bit | ||||
11:7 | RESERVED | R | 0x0 | |
6 | DPOL | Image sensor input data polarity (only for VP-1) | RW | 0x0 |
0x0: No change | ||||
0x1: One's complement | ||||
5:4 | RESERVED | R | 0x0 | |
3 | HDPOL | HD Sync Signal Polarity of input signal (only for VP-1) Switch will convert HD polarity to high active regardless of the input polarity | RW | 0x0 |
0x0: Positive | ||||
0x1: Negative | ||||
2 | VDPOL | VD Sync Signal Polarity of input signal (Only for VP-1) Switch will convert VD polarity to high active regardless of the input polarity | RW | 0x0 |
0x0: Positive | ||||
0x1: Negative | ||||
1:0 | RESERVED | R | 0x0 |
Address Offset | 0x0000 0010 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Start Pixel Horizontal | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | SPH | The location of the first active pixel in a line. This is specified by the number of cycles. This register is latched at VD or at corresponding SYNCEN rising edge | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0014 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | This register is latched at VD or at corresponding SYNCEN rising edge | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LNH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | LNH | Number of active pixels in an line Number of pixels = LNH + 1. This number is specified by the number of cycles. Therefore, for YUV422 8bit mode, the number of pixels is (LNH+1)/2. This register is latched at VD or at corresponding SYNCEN rising edge | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0018 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Start Line, Vertical | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLV |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | SLV | Start Line, Vertical Sets line at which active data will begin, measured from the start of VD This register is latched at VD or at corresponding SYNCEN rising edge | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 001C | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LNV |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | LNV | The number of active lines Number of lines = LNV + 1 This register is latched at VD or at corresponding SYNCEN rising edge | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0020 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GWDI | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:5 | RESERVED | R | 0x0 | |
4:1 | GWDI | Selects MSB position of Input Data for NSF3V (VP-1 and CAL) For input of IN[15..0], corresponding output is given to DPC and/or NSF3V. This bit is only valid in Bayer (RAW) mode. In YUV input, this bit is ignored. There is no GWDO for NSF3V process, since 12 bit is always mapped to LSB. | RW | 0x0 |
0x6: OUTPUT: (IN[9..0] 2) | ||||
0x1: OUTPUT: IN[14..3] | ||||
0x7: OUTPUT: (IN[8..0] 3) | ||||
0x0: OUTPUT: IN[15..4] | ||||
0x2: OUTPUT: IN[13..2] | ||||
0x8: OUTPUT: (IN[7..0] 4) | ||||
0x9: Reserved | ||||
0x4: OUTPUT: IN[11..0] | ||||
0x5: OUTPUT: (IN[10..0] 1) | ||||
0x3: OUTPUT: IN[12..1] | ||||
0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 0024 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OO | OE | EO | EE | RESERVED | Y8POS | RESERVED | YCINSWP | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23:22 | OO | The color pattern of the odd line and odd pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2, and DPC_SEL=1. | RW | 0x0 |
0x0: R | ||||
0x1: GR | ||||
0x3: B | ||||
0x2: GB | ||||
21:20 | OE | The color pattern of the odd line and even pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2, and DPC_SEL=1. | RW | 0x0 |
0x0: R | ||||
0x1: GR | ||||
0x3: B | ||||
0x2: GB | ||||
19:18 | EO | The color pattern of the even line and odd pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2, and DPC_SEL=1. | RW | 0x0 |
0x0: R | ||||
0x1: GR | ||||
0x3: B | ||||
0x2: GB | ||||
17:16 | EE | The color pattern of the even line and even pixel used in DPC This parameter is valid when NSF3V_SEL=1 or 2, and DPC_SEL=1. | RW | 0x0 |
0x0: R | ||||
0x1: GR | ||||
0x3: B | ||||
0x2: GB | ||||
15:12 | RESERVED | R | 0x0 | |
11 | Y8POS | Selects Y signal position when in 8bit input mode | RW | 0x0 |
0x0: Y is at even pixel Y is at 0th, 2nd, 4th, ... pixels. Cb is at 1st, 5th, ... pixels. Cr is at 3rd, 7th, ... pixels. | ||||
0x1: Y is at odd pixel Cb is at 0th, 4th, 8th, ... pixels Cr is at 2nd, 6th, 10th, ... pixels Y is at 1st, 3rd, 5th, ... pixels | ||||
10:5 | RESERVED | R | 0x0 | |
4 | YCINSWP | The ISIF module has a 16-bit interface. When 16-bit YUV data are input, the luma data (YIN7-0) are expected to be on the 8 MS bits and the chroma (CIN7-0) data are expected to be on the LS bits. This bit enables to swap the 8 MS bits with the 8 LS bits of the interface in case the luma and chroma do not come in the correct order. (This function is same as ISIF's. Refer to the top-level ISIF block diagram.) | RW | 0x0 |
0x0: YIN7-0 = Y signal / CIN7-0 = C signal | ||||
0x1: YIN7-0 = C signal / CIN7-0 = Y signal | ||||
3:0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 0028 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Horizontal/Vertical Delay of VP1 port | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DELAY_SWT | RESERVED | DLV | RESERVED | DLH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | R | 0x0 | |
30 | DELAY_SWT | This bit changes the delay between NSF3V input VD/HD and output VD/HD Usually, this bit is '0'. This bit is supposed to be used when NSF3V works with ISP (VP1), and IPIPEIF is in DFS/WDR mode. In this case VD must be at least one line earlier than the first valid line. | RW | 0x0 |
0x0: The output of VD (VD_OUT) is at the same clock as the first pixel output of the frame. The output of HD (HD_OUT)is at the same clock as the firlst pixel output in each line. | ||||
0x1: The VD/HD timing is controlled by DLV/DLH. VD output (VD_OUT) timing is DLV lines after VD input (VD_IN), on the same clock as HD output (HD_OUT) HD output (HD_OUT) timing is DLH pixel clocks after HD input (HD_IN) | ||||
29:24 | RESERVED | R | 0x0 | |
23:16 | DLV | Vertical Delay of VP1 port from VS_IN to VD_OUT. This field is only used if DELAY_SWT=='1', and ignored if DELAY_SWT=='0' This register is latched at VS. If DELAY_SWT is '1', after number of lines specified here following VD_IN, VD_OUT is output. This value should be equalt to or smaller than NSF3V line latency for meaningfull operation. The only possible case that this field is used is when NSF3V is used with ISP, and IPIPEIF is in DFS or WDR mode. A value between 0 and 3 should be specified for TB_BORDER=00 or 10 case. A value between 0 and 17 should be specified for TB_BODER=01 or 11 case. Since there is DLV lines between VD and the first valid line, the down stream modules need to be programmed accordingly. | RW | 0x0 |
15:8 | RESERVED | R | 0x0 | |
7:0 | DLH | This field is only used if DELAY_SWT=='1', and ignored if DELAY_SWT=='0' VP1 port horizontal delay from HS_IN (derived from HD_IN) to HD_OUT, which affect the cycles between HD_OUT and first valid pixel. This register is latched at VS. The meaning of this value changes depending on the input format (ISP_NSF3V_MODESET.INPMOD). For YCbCr-16bit (ISP_NSF3V_MODESET.INPMOD==1) The maximum DLH value allowed is 8. If DLH=8, HD output is at the same clock as the first pixel output in each line. If DLH 8, HD output is (8-DLH) clock before the first pixel output. For Bayer input or YCbCr-8bit input (ISP_NSF3V_MODESET.INPMOD==0 or 2) Maximum DLH allowed is 16. If DLH=16, HD output is at the same clock as the first pixel output in each line. If DLH 16, HD output is (16-DLH) clock before the first pixel output. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0030 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Start Pixel Horizontal | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | SPH | The location of the first active pixel in a line | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0034 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Reserved | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 0038 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Start Line, Vertical | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLV |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:15 | RESERVED | R | 0x0 | |
14:0 | SLV | Start Line, Vertical Sets line at which active data will begin, measured from the start of VD This register is latched at VD or at corresponding SYNCEN rising edge | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0040 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GWDO | RESERVED | GWDI | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:8 | GWDO | Selects MSB position of output data from GLBCE (VP2/CAL2) This value is only used at GLBCE output, and does not affect if GLBCE is skipped (IPIPEIF to IPIPE case). | RW | 0x0 |
0x6: '000000' [15..6] | ||||
0x1: '0' [15..1] | ||||
0x7: '0000000' [15..7] | ||||
0x0: [15..0] | ||||
0x2: '00' [15..2] | ||||
0x8: '00000000' [15..8] | ||||
0x9: Reserved | ||||
0x4: '0000' [15..4] | ||||
0x5: '00000' [15..5] | ||||
0x3: '000' [15..3] | ||||
7:5 | RESERVED | R | 0x0 | |
4:1 | GWDI | Selects MSB position of Input Data for GLBCE (VP2/CAL2) This value is only used at GLBCE input, and does not affect if GLBCE is skipped (IPIPEIF to IPIPE case). | RW | 0x0 |
0x6: [9..0] '000000' | ||||
0x1: [14..0] '0' | ||||
0x7: [8..0] '0000000' | ||||
0x0: [15..0] | ||||
0x2: [13..0] '00' | ||||
0x8: [7..0]*'00000000' | ||||
0x9: Reserved | ||||
0x4: [11..0] '0000' | ||||
0x5: [10..0] '00000' | ||||
0x3: [12..0] '000' | ||||
0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 0044 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | Horizontal/Vertical Delay of VP2 port | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DLV | RESERVED | DLH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23:16 | DLV | Vertical Delay of VP1 port from VS_IN to VD_IN. After number of lines specified here following VD_IN, VD_IN is output. This value should be equalt to or smaller than GLBCE line latency for meaningfull operation. This register is latched at VS or at corresponding SYNCEN rising edge Usually, this value should be left as default (1) | RW | 0x1 |
15:8 | RESERVED | R | 0x0 | |
7:0 | DLH | VP1 port horizontal delay from HS_IN (derived from HD_IN) to HD_OUT. The latency of NSF3V should be set in this field. This register is latched at VS or at corresponding SYNCEN rising edge Usually, this value should be left as default (67) | RW | 0x3b |
ISS ISP |
Address Offset | 0x0000 0050 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNFB_CDSEN | CNFB_EN | RESERVED | CNFA_CDSEN | CNFA_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x0 | |
5 | CNFB_CDSEN | Note: This is don't care in ISP6.5 since CNF-B is removed. CDS (Chroma down sample) is enabled in CNF process on RZB path. This is only valid if CNF is enabled (RZB_CNFEN=1). | RW | 0x0 |
0x0: CDS is disabled in CNF process on RZB output | ||||
0x1: CDS is enabled in CNF process on RZB output | ||||
4 | CNFB_EN | WARNING This shouldn't be enabled in ISP6.5 (ADAS-LOW Program) since CNF-B is removed. Enable CNF (Chroma noise filter) on RZB path. This is only valid if the output is 420, and UV pass is active. In other case, this bit must be zero. In specific, this bit is valid in the following cases. 1. YUV420-UV input RSZ_SRC_FMT1.IN420=1 RSZ_SRC_FMT1.COL=1 2. YUV422 input, YUV420-YUV or YUV420-UV output RSZ_SRC_FMT1.IN420=0 RZB_420.CEN = 1 (RZB_420.YEN can be 0 or 1) | RW | 0x0 |
0x0: CNF is disabled on RZB output | ||||
0x1: CNF is enabled on RZB output | ||||
3:2 | RESERVED | R | 0x0 | |
1 | CNFA_CDSEN | CDS (Chroma down sample) is enabled in CNF process on RZA path. This is only valid if CNF is enabled (RZA_CNFEN=1). | RW | 0x0 |
0x0: CDS is disabled in CNF process on RZA output | ||||
0x1: CDS is enabled in CNF process on RZA output | ||||
0 | CNFA_EN | Enable CNF (Chroma noise filter) on RZA path This is only valid if the output is 420, and UV pass is active. In other case, this bit must be zero. In specific, this bit is valid in the following cases. 1. YUV420-UV input RSZ_SRC_FMT1.IN420=1 RSZ_SRC_FMT1.COL=1 2. YUV422 input, YUV420-YUV or YUV420-UV output RSZ_SRC_FMT1.IN420=0 RZA_420.CEN = 1 (RZA_420.YEN can be 0 or 1) | RW | 0x0 |
0x0: CNF is disabled on RZA output | ||||
0x1: CNF is enabled on RZA output |
ISS ISP |
Address Offset | 0x0000 0054 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HEIGHT | RESERVED | WIDTH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29:16 | HEIGHT | The height of CNFA output. This number MUST be - Same as Resizer-A chroma output height, if CDS is off - 1/2 of Resizer-A output height, if CDS is on Therefore, the Resizer-A chroma output height must be even if CDS is on. Resizer-A's MMR must be programmed accordingly. This number MUST be the same as CNFA-Core's input height. CNF-A's MMR must be programmed accordingly. | RW | 0x0 |
15:14 | RESERVED | R | 0x0 | |
13:0 | WIDTH | The width of CNFA output. This number MUST be even. This number MUST be - Same as Resizer-A output width, if CDS is off - 1/2 of Resizer-A output width, if CDS is on Therefore, the Resizer-A output width must be a multiple of 4 if CDS is on. Resizer-A's MMR must be programmed accordingly. This number MUST be the same as CNFA-Core's input width. CNF-A's MMR must be programmed accordingly. | RW | 0x0 |
Address Offset | 0x0000 0058 | ||
Physical Address | Please refer to Table 9-1535 | Instance | ISS_TARGET__ISP6P5__i_ISP6_SYS3 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HEIGHT | RESERVED | WIDTH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29:16 | HEIGHT | Note: This is don't care in ISP6.5 since CNF-B is removed. The height of CNFB output. This number MUST be - Same as Resizer-B chroma output height, if CDS is off - 1/2 of Resizer-B chroma output height, if CDS is on Therefore, the Resizer-B chroma output height must be even if CDS is on. Resizer-B's MMR must be programmed accordingly. This number MUST be the same as CNFB-Core's input height. CNF's MMR must be programmed accordingly. | RW | 0x0 |
15:14 | RESERVED | R | 0x0 | |
13:0 | WIDTH | Note: This is don't care in ISP6.5 since CNF-B is removed. The width of CNFB output. This number MUST be even. This number MUST be - Same as Resizer-B output width if CDS is off - 1/2 of Resizer-B output width if CDS is on Therefore, the Resizer-B output width must be a multiple of 4 if CDS is on. Resizer-B's MMR must be programmed accordingly. This number MUST be the same as CNFB-Core's input width. CNF-B's MMR must be programmed accordingly. | RW | 0x0 |