SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Table 18-80 through Table 18-90 summarize the EDMA_TPCC, EDMA_TPTC0 and EDMA_TPTC1 registers.
All EDMA modules in the SoC are functionally identical. Note that some of the configuration parameters may be different for the various EDMA instances (see Section 18.2.1.3, EDMA Controllers Configuration).
Register Name | Type | Register Width (Bits) | Address Offset | SYS_EDMA_TPCC Physical Address (L3_MAIN Access) |
---|---|---|---|---|
EDMA_TPCC_PID | R | 32 | 0x0000 0000 | 0x4330 0000 |
EDMA_TPCC_CCCFG | R | 32 | 0x0000 0004 | 0x4330 0004 |
EDMA_TPCC_CLKGDIS | RW | 32 | 0x0000 00FC | 0x4330 00FC |
EDMA_TPCC_DCHMAPN_m (5) | RW | 32 | 0x0000 0100 + (0x4 * m) | 0x4330 0100 + (0x4 * m) |
EDMA_TPCC_QCHMAPN_j (2) | RW | 32 | 0x0000 0200 + (0x4 * j) | 0x4330 0200 + (0x4 * j) |
EDMA_TPCC_DMAQNUMN_k (3) | RW | 32 | 0x0000 0240 + (0x4 * k) | 0x4330 0240 + (0x4 * k) |
EDMA_TPCC_QDMAQNUM | RW | 32 | 0x0000 0260 | 0x4330 0260 |
EDMA_TPCC_QUETCMAP | RW | 32 | 0x0000 0280 | 0x4330 0280 |
EDMA_TPCC_QUEPRI | RW | 32 | 0x0000 0284 | 0x4330 0284 |
EDMA_TPCC_EMR | R | 32 | 0x0000 0300 | 0x4330 0300 |
EDMA_TPCC_EMRH | R | 32 | 0x0000 0304 | 0x4330 0304 |
EDMA_TPCC_EMCR | W | 32 | 0x0000 0308 | 0x4330 0308 |
EDMA_TPCC_EMCRH | W | 32 | 0x0000 030C | 0x4330 030C |
EDMA_TPCC_QEMR | R | 32 | 0x0000 0310 | 0x4330 0310 |
EDMA_TPCC_QEMCR | W | 32 | 0x0000 0314 | 0x4330 0314 |
EDMA_TPCC_CCERR | R | 32 | 0x0000 0318 | 0x4330 0318 |
EDMA_TPCC_CCERRCLR | W | 32 | 0x0000 031C | 0x4330 031C |
EDMA_TPCC_EEVAL | W | 32 | 0x0000 0320 | 0x4330 0320 |
EDMA_TPCC_DRAEM_k (3) | RW | 32 | 0x0000 0340 + (0x8 * k) | 0x4330 0340 + (0x8 * k) |
EDMA_TPCC_DRAEHM_k (3) | RW | 32 | 0x0000 0344 + (0x8 * k) | 0x4330 0344 + (0x8 * k) |
EDMA_TPCC_QRAEN_k (3) | RW | 32 | 0x0000 0380 + (0x4 * k) | 0x4330 0380 + (0x4 * k) |
EDMA_TPCC_Q0E_p (4) | R | 32 | 0x0000 0400 + (0x4 *pl) | 0x4330 0400 + (0x4 * p) |
EDMA_TPCC_Q1E_p (4) | R | 32 | 0x0000 0440 + (0x4 * p) | 0x4330 0440 + (0x4 * p) |
EDMA_TPCC_QSTATN_i (1) | R | 32 | 0x0000 0600 + (0x4 * i) | 0x4330 0600 + (0x4 * i) |
EDMA_TPCC_QWMTHRA | RW | 32 | 0x0000 0620 | 0x4330 0620 |
EDMA_TPCC_QWMTHRB | RW | 32 | 0x0000 0624 | 0x4330 0624 |
EDMA_TPCC_CCSTAT | R | 32 | 0x0000 0640 | 0x4330 0640 |
EDMA_TPCC_AETCTL | RW | 32 | 0x0000 0700 | 0x4330 0700 |
EDMA_TPCC_AETSTAT | R | 32 | 0x0000 0704 | 0x4330 0704 |
EDMA_TPCC_AETCMD | W | 32 | 0x0000 0708 | 0x4330 0708 |
EDMA_TPCC_MPFAR | R | 32 | 0x0000 0800 | 0x4330 0800 |
EDMA_TPCC_MPFSR | R | 32 | 0x0000 0804 | 0x4330 0804 |
EDMA_TPCC_MPFCR | W | 32 | 0x0000 0808 | 0x4330 0808 |
EDMA_TPCC_MPPAG | RW | 32 | 0x0000 080C | 0x4330 080C |
EDMA_TPCC_MPPAN_k (3) | RW | 32 | 0x0000 0810 + (0x4 * k) | 0x4330 0810 + (0x4 * k) |
EDMA_TPCC_ER | R | 32 | 0x0000 1000 | 0x4330 1000 |
EDMA_TPCC_ERH | R | 32 | 0x0000 1004 | 0x4330 1004 |
EDMA_TPCC_ECR | W | 32 | 0x0000 1008 | 0x4330 1008 |
EDMA_TPCC_ECRH | W | 32 | 0x0000 100C | 0x4330 100C |
EDMA_TPCC_ESR | W | 32 | 0x0000 1010 | 0x4330 1010 |
EDMA_TPCC_ESRH | W | 32 | 0x0000 1014 | 0x4330 1014 |
EDMA_TPCC_CER | R | 32 | 0x0000 1018 | 0x4330 1018 |
EDMA_TPCC_CERH | R | 32 | 0x0000 101C | 0x4330 101C |
EDMA_TPCC_EER | R | 32 | 0x0000 1020 | 0x4330 1020 |
EDMA_TPCC_EERH | R | 32 | 0x0000 1024 | 0x4330 1024 |
EDMA_TPCC_EECR | W | 32 | 0x0000 1028 | 0x4330 1028 |
EDMA_TPCC_EECRH | W | 32 | 0x0000 102C | 0x4330 102C |
EDMA_TPCC_EESR | W | 32 | 0x0000 1030 | 0x4330 1030 |
EDMA_TPCC_EESRH | W | 32 | 0x0000 1034 | 0x4330 1034 |
EDMA_TPCC_SER | R | 32 | 0x0000 1038 | 0x4330 1038 |
EDMA_TPCC_SERH | R | 32 | 0x0000 103C | 0x4330 103C |
EDMA_TPCC_SECR | W | 32 | 0x0000 1040 | 0x4330 1040 |
EDMA_TPCC_SECRH | W | 32 | 0x0000 1044 | 0x4330 1044 |
EDMA_TPCC_IER | R | 32 | 0x0000 1050 | 0x4330 1050 |
EDMA_TPCC_IERH | R | 32 | 0x0000 1054 | 0x4330 1054 |
EDMA_TPCC_IECR | W | 32 | 0x0000 1058 | 0x4330 1058 |
EDMA_TPCC_IECRH | W | 32 | 0x0000 105C | 0x4330 105C |
EDMA_TPCC_IESR | W | 32 | 0x0000 1060 | 0x4330 1060 |
EDMA_TPCC_IESRH | W | 32 | 0x0000 1064 | 0x4330 1064 |
EDMA_TPCC_IPR | R | 32 | 0x0000 1068 | 0x4330 1068 |
EDMA_TPCC_IPRH | R | 32 | 0x0000 106C | 0x4330 106C |
EDMA_TPCC_ICR | W | 32 | 0x0000 1070 | 0x4330 1070 |
EDMA_TPCC_ICRH | W | 32 | 0x0000 1074 | 0x4330 1074 |
EDMA_TPCC_IEVAL | W | 32 | 0x0000 1078 | 0x4330 1078 |
EDMA_TPCC_QER | R | 32 | 0x0000 1080 | 0x4330 1080 |
EDMA_TPCC_QEER | R | 32 | 0x0000 1084 | 0x4330 1084 |
EDMA_TPCC_QEECR | W | 32 | 0x0000 1088 | 0x4330 1088 |
EDMA_TPCC_QEESR | W | 32 | 0x0000 108C | 0x4330 108C |
EDMA_TPCC_QSER | R | 32 | 0x0000 1090 | 0x4330 1090 |
EDMA_TPCC_QSECR | W | 32 | 0x0000 1094 | 0x4330 1094 |
EDMA_TPCC_ER_RN_k (3) | R | 32 | 0x0000 2000 + (0x200 * k) | 0x4330 2000 + (0x200 * k) |
EDMA_TPCC_ERH_RN_k (3) | R | 32 | 0x0000 2004 + (0x200 * k) | 0x4330 2004 + (0x200 * k) |
EDMA_TPCC_ECR_RN_k (3) | W | 32 | 0x0000 2008 + (0x200 * k) | 0x4330 2008 + (0x200 * k) |
EDMA_TPCC_ECRH_RN_k (3) | W | 32 | 0x0000 200C + (0x200 * k) | 0x4330 200C + (0x200 * k) |
EDMA_TPCC_ESR_RN_k (3) | W | 32 | 0x0000 2010 + (0x200 * k) | 0x4330 2010 + (0x200 * k) |
EDMA_TPCC_ESRH_RN_k (3) | W | 32 | 0x0000 2014 + (0x200 * k) | 0x4330 2014 + (0x200 * k) |
EDMA_TPCC_CER_RN_k (3) | R | 32 | 0x0000 2018 + (0x200 * k) | 0x4330 2018 + (0x200 * k) |
EDMA_TPCC_CERH_RN_k (3) | R | 32 | 0x0000 201C + (0x200 * k) | 0x4330 201C + (0x200 * k) |
EDMA_TPCC_EER_RN_k (3) | R | 32 | 0x0000 2020 + (0x200 * k) | 0x4330 2020 + (0x200 * k) |
EDMA_TPCC_EERH_RN_k (3) | R | 32 | 0x0000 2024 + (0x200 * k) | 0x4330 2024 + (0x200 * k) |
EDMA_TPCC_EECR_RN_k (3) | W | 32 | 0x0000 2028 + (0x200 * k) | 0x4330 2028 + (0x200 * k) |
EDMA_TPCC_EECRH_RN_k (3) | W | 32 | 0x0000 202C + (0x200 * k) | 0x4330 202C + (0x200 * k) |
EDMA_TPCC_EESR_RN_k (3) | W | 32 | 0x0000 2030 + (0x200 * k) | 0x4330 2030 + (0x200 * k) |
EDMA_TPCC_EESRH_RN_k (3) | W | 32 | 0x0000 2034 + (0x200 * k) | 0x4330 2034 + (0x200 * k) |
EDMA_TPCC_SER_RN_k (3) | R | 32 | 0x0000 2038 + (0x200 * k) | 0x4330 2038 + (0x200 * k) |
EDMA_TPCC_SERH_RN_k (3) | R | 32 | 0x0000 203C + (0x200 * k) | 0x4330 203C + (0x200 * k) |
EDMA_TPCC_SECR_RN_k (3) | W | 32 | 0x0000 2040 + (0x200 * k) | 0x4330 2040 + (0x200 * k) |
EDMA_TPCC_SECRH_RN_k (3) | W | 32 | 0x0000 2044 + (0x200 * k) | 0x4330 2044 + (0x200 * k) |
EDMA_TPCC_IER_RN_k (3) | R | 32 | 0x0000 2050 + (0x200 * k) | 0x4330 2050 + (0x200 * k) |
EDMA_TPCC_IERH_RN_k (3) | R | 32 | 0x0000 2054 + (0x200 * k) | 0x4330 2054 + (0x200 * k) |
EDMA_TPCC_IECR_RN_k (3) | W | 32 | 0x0000 2058 + (0x200 * k) | 0x4330 2058 + (0x200 * k) |
EDMA_TPCC_IECRH_RN_k (3) | W | 32 | 0x0000 205C + (0x200 * k) | 0x4330 205C + (0x200 * k) |
EDMA_TPCC_IESR_RN_k (3) | W | 32 | 0x0000 2060 + (0x200 * k) | 0x4330 2060 + (0x200 * k) |
EDMA_TPCC_IESRH_RN_k (3) | W | 32 | 0x0000 2064 + (0x200 * k) | 0x4330 2064 + (0x200 * k) |
EDMA_TPCC_IPR_RN_k (3) | R | 32 | 0x0000 2068 + (0x200 * k) | 0x4330 2068 + (0x200 * k) |
EDMA_TPCC_IPRH_RN_k (3) | R | 32 | 0x0000 206C + (0x200 * k) | 0x4330 206C + (0x200 * k) |
EDMA_TPCC_ICR_RN_k (3) | W | 32 | 0x0000 2070 + (0x200 * k) | 0x4330 2070 + (0x200 * k) |
EDMA_TPCC_ICRH_RN_k (3) | W | 32 | 0x0000 2074 + (0x200 * k) | 0x4330 2074 + (0x200 * k) |
EDMA_TPCC_IEVAL_RN_k (3) | W | 32 | 0x0000 2078 + (0x200 * k) | 0x4330 2078 + (0x200 * k) |
EDMA_TPCC_QER_RN_k (3) | R | 32 | 0x0000 2080 + (0x200 * k) | 0x4330 2080 + (0x200 * k) |
EDMA_TPCC_QEER_RN_k (3) | R | 32 | 0x0000 2084 + (0x200 * k) | 0x4330 2084 + (0x200 * k) |
EDMA_TPCC_QEECR_RN_k (3) | W | 32 | 0x0000 2088 + (0x200 * k) | 0x4330 2088 + (0x200 * k) |
EDMA_TPCC_QEESR_RN_k (3) | W | 32 | 0x0000 208C + (0x200 * k) | 0x4330 208C + (0x200 * k) |
EDMA_TPCC_QSER_RN_k (3) | R | 32 | 0x0000 2090 + (0x200 * k) | 0x4330 2090 + (0x200 * k) |
EDMA_TPCC_QSECR_RN_k (3) | W | 32 | 0x0000 2094 + (0x200 * k) | 0x4330 2094 + (0x200 * k) |
EDMA_TPCC_OPT_n(6) | RW | 32 | 0x0000 4000 + (0x20 * n) | 0x4330 4000 + (0x20 * n) |
EDMA_TPCC_SRC_n (6) | RW | 32 | 0x0000 4004 + (0x20 * n) | 0x4330 4004 + (0x20 * n) |
EDMA_TPCC_ABCNT_n (6) | RW | 32 | 0x0000 4008 + (0x20 * n) | 0x4330 4008 + (0x20 * n) |
EDMA_TPCC_DST_n (6) | RW | 32 | 0x0000 400C + (0x20 * n) | 0x4330 400C + (0x20 * n) |
EDMA_TPCC_BIDX_n (6) | RW | 32 | 0x0000 4010 + (0x20 * n) | 0x4330 4010 + (0x20 * n) |
EDMA_TPCC_LNK_n (6) | RW | 32 | 0x0000 4014 + (0x20 * n) | 0x4330 4014 + (0x20 * n) |
EDMA_TPCC_CIDX_n (6) | RW | 32 | 0x0000 4018 + (0x20 * n) | 0x4330 4018 + (0x20 * n) |
EDMA_TPCC_CCNT_n (6) | RW | 32 | 0x0000 401C + (0x20 * n) | 0x4330 401C + (0x20 * n) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP1_EDMA_TPCC Physical Address (L3_MAIN Access) |
---|---|---|---|---|
EDMA_TPCC_PID | R | 32 | 0x0000 0000 | 0x40D1 0000 |
EDMA_TPCC_CCCFG | R | 32 | 0x0000 0004 | 0x40D1 0004 |
EDMA_TPCC_CLKGDIS | RW | 32 | 0x0000 00FC | 0x40D1 00FC |
EDMA_TPCC_DCHMAPN_m (5) | RW | 32 | 0x0000 0100 + (0x4 * m) | 0x40D1 0100 + (0x4 * m) |
EDMA_TPCC_QCHMAPN_j (2) | RW | 32 | 0x0000 0200 + (0x4 * j) | 0x40D1 0200 + (0x4 * j) |
EDMA_TPCC_DMAQNUMN_k (3) | RW | 32 | 0x0000 0240 + (0x4 * k) | 0x40D1 0240 + (0x4 * k) |
EDMA_TPCC_QDMAQNUM | RW | 32 | 0x0000 0260 | 0x40D1 0260 |
EDMA_TPCC_QUETCMAP | RW | 32 | 0x0000 0280 | 0x40D1 0280 |
EDMA_TPCC_QUEPRI | RW | 32 | 0x0000 0284 | 0x40D1 0284 |
EDMA_TPCC_EMR | R | 32 | 0x0000 0300 | 0x40D1 0300 |
EDMA_TPCC_EMRH | R | 32 | 0x0000 0304 | 0x40D1 0304 |
EDMA_TPCC_EMCR | W | 32 | 0x0000 0308 | 0x40D1 0308 |
EDMA_TPCC_EMCRH | W | 32 | 0x0000 030C | 0x40D1 030C |
EDMA_TPCC_QEMR | R | 32 | 0x0000 0310 | 0x40D1 0310 |
EDMA_TPCC_QEMCR | W | 32 | 0x0000 0314 | 0x40D1 0314 |
EDMA_TPCC_CCERR | R | 32 | 0x0000 0318 | 0x40D1 0318 |
EDMA_TPCC_CCERRCLR | W | 32 | 0x0000 031C | 0x40D1 031C |
EDMA_TPCC_EEVAL | W | 32 | 0x0000 0320 | 0x40D1 0320 |
EDMA_TPCC_DRAEM_k (3) | RW | 32 | 0x0000 0340 + (0x8 * k) | 0x40D1 0340 + (0x8 * k) |
EDMA_TPCC_DRAEHM_k (3) | RW | 32 | 0x0000 0344 + (0x8 * k) | 0x40D1 0344 + (0x8 * k) |
EDMA_TPCC_QRAEN_k (3) | RW | 32 | 0x0000 0380 + (0x4 * k) | 0x40D1 0380 + (0x4 * k) |
EDMA_TPCC_Q0E_p (4) | R | 32 | 0x0000 0400 + (0x4 *pl) | 0x40D1 0400 + (0x4 * p) |
EDMA_TPCC_Q1E_p (4) | R | 32 | 0x0000 0440 + (0x4 * p) | 0x40D1 0440 + (0x4 * p) |
EDMA_TPCC_QSTATN_i (1) | R | 32 | 0x0000 0600 + (0x4 * i) | 0x40D1 0600 + (0x4 * i) |
EDMA_TPCC_QWMTHRA | RW | 32 | 0x0000 0620 | 0x40D1 0620 |
EDMA_TPCC_QWMTHRB | RW | 32 | 0x0000 0624 | 0x40D1 0624 |
EDMA_TPCC_CCSTAT | R | 32 | 0x0000 0640 | 0x40D1 0640 |
EDMA_TPCC_AETCTL | RW | 32 | 0x0000 0700 | 0x40D1 0700 |
EDMA_TPCC_AETSTAT | R | 32 | 0x0000 0704 | 0x40D1 0704 |
EDMA_TPCC_AETCMD | W | 32 | 0x0000 0708 | 0x40D1 0708 |
EDMA_TPCC_MPFAR | R | 32 | 0x0000 0800 | 0x40D1 0800 |
EDMA_TPCC_MPFSR | R | 32 | 0x0000 0804 | 0x40D1 0804 |
EDMA_TPCC_MPFCR | W | 32 | 0x0000 0808 | 0x40D1 0808 |
EDMA_TPCC_MPPAG | RW | 32 | 0x0000 080C | 0x40D1 080C |
EDMA_TPCC_MPPAN_k (3) | RW | 32 | 0x0000 0810 + (0x4 * k) | 0x40D1 0810 + (0x4 * k) |
EDMA_TPCC_ER | R | 32 | 0x0000 1000 | 0x40D1 1000 |
EDMA_TPCC_ERH | R | 32 | 0x0000 1004 | 0x40D1 1004 |
EDMA_TPCC_ECR | W | 32 | 0x0000 1008 | 0x40D1 1008 |
EDMA_TPCC_ECRH | W | 32 | 0x0000 100C | 0x40D1 100C |
EDMA_TPCC_ESR | W | 32 | 0x0000 1010 | 0x40D1 1010 |
EDMA_TPCC_ESRH | W | 32 | 0x0000 1014 | 0x40D1 1014 |
EDMA_TPCC_CER | R | 32 | 0x0000 1018 | 0x40D1 1018 |
EDMA_TPCC_CERH | R | 32 | 0x0000 101C | 0x40D1 101C |
EDMA_TPCC_EER | R | 32 | 0x0000 1020 | 0x40D1 1020 |
EDMA_TPCC_EERH | R | 32 | 0x0000 1024 | 0x40D1 1024 |
EDMA_TPCC_EECR | W | 32 | 0x0000 1028 | 0x40D1 1028 |
EDMA_TPCC_EECRH | W | 32 | 0x0000 102C | 0x40D1 102C |
EDMA_TPCC_EESR | W | 32 | 0x0000 1030 | 0x40D1 1030 |
EDMA_TPCC_EESRH | W | 32 | 0x0000 1034 | 0x40D1 1034 |
EDMA_TPCC_SER | R | 32 | 0x0000 1038 | 0x40D1 1038 |
EDMA_TPCC_SERH | R | 32 | 0x0000 103C | 0x40D1 103C |
EDMA_TPCC_SECR | W | 32 | 0x0000 1040 | 0x40D1 1040 |
EDMA_TPCC_SECRH | W | 32 | 0x0000 1044 | 0x40D1 1044 |
EDMA_TPCC_IER | R | 32 | 0x0000 1050 | 0x40D1 1050 |
EDMA_TPCC_IERH | R | 32 | 0x0000 1054 | 0x40D1 1054 |
EDMA_TPCC_IECR | W | 32 | 0x0000 1058 | 0x40D1 1058 |
EDMA_TPCC_IECRH | W | 32 | 0x0000 105C | 0x40D1 105C |
EDMA_TPCC_IESR | W | 32 | 0x0000 1060 | 0x40D1 1060 |
EDMA_TPCC_IESRH | W | 32 | 0x0000 1064 | 0x40D1 1064 |
EDMA_TPCC_IPR | R | 32 | 0x0000 1068 | 0x40D1 1068 |
EDMA_TPCC_IPRH | R | 32 | 0x0000 106C | 0x40D1 106C |
EDMA_TPCC_ICR | W | 32 | 0x0000 1070 | 0x40D1 1070 |
EDMA_TPCC_ICRH | W | 32 | 0x0000 1074 | 0x40D1 1074 |
EDMA_TPCC_IEVAL | W | 32 | 0x0000 1078 | 0x40D1 1078 |
EDMA_TPCC_QER | R | 32 | 0x0000 1080 | 0x40D1 1080 |
EDMA_TPCC_QEER | R | 32 | 0x0000 1084 | 0x40D1 1084 |
EDMA_TPCC_QEECR | W | 32 | 0x0000 1088 | 0x40D1 1088 |
EDMA_TPCC_QEESR | W | 32 | 0x0000 108C | 0x40D1 108C |
EDMA_TPCC_QSER | R | 32 | 0x0000 1090 | 0x40D1 1090 |
EDMA_TPCC_QSECR | W | 32 | 0x0000 1094 | 0x40D1 1094 |
EDMA_TPCC_ER_RN_k (3) | R | 32 | 0x0000 2000 + (0x200 * k) | 0x40D1 2000 + (0x200 * k) |
EDMA_TPCC_ERH_RN_k (3) | R | 32 | 0x0000 2004 + (0x200 * k) | 0x40D1 2004 + (0x200 * k) |
EDMA_TPCC_ECR_RN_k (3) | W | 32 | 0x0000 2008 + (0x200 * k) | 0x40D1 2008 + (0x200 * k) |
EDMA_TPCC_ECRH_RN_k (3) | W | 32 | 0x0000 200C + (0x200 * k) | 0x40D1 200C + (0x200 * k) |
EDMA_TPCC_ESR_RN_k (3) | W | 32 | 0x0000 2010 + (0x200 * k) | 0x40D1 2010 + (0x200 * k) |
EDMA_TPCC_ESRH_RN_k (3) | W | 32 | 0x0000 2014 + (0x200 * k) | 0x40D1 2014 + (0x200 * k) |
EDMA_TPCC_CER_RN_k (3) | R | 32 | 0x0000 2018 + (0x200 * k) | 0x40D1 2018 + (0x200 * k) |
EDMA_TPCC_CERH_RN_k (3) | R | 32 | 0x0000 201C + (0x200 * k) | 0x40D1 201C + (0x200 * k) |
EDMA_TPCC_EER_RN_k (3) | R | 32 | 0x0000 2020 + (0x200 * k) | 0x40D1 2020 + (0x200 * k) |
EDMA_TPCC_EERH_RN_k (3) | R | 32 | 0x0000 2024 + (0x200 * k) | 0x40D1 2024 + (0x200 * k) |
EDMA_TPCC_EECR_RN_k (3) | W | 32 | 0x0000 2028 + (0x200 * k) | 0x40D1 2028 + (0x200 * k) |
EDMA_TPCC_EECRH_RN_k (3) | W | 32 | 0x0000 202C + (0x200 * k) | 0x40D1 202C + (0x200 * k) |
EDMA_TPCC_EESR_RN_k (3) | W | 32 | 0x0000 2030 + (0x200 * k) | 0x40D1 2030 + (0x200 * k) |
EDMA_TPCC_EESRH_RN_k (3) | W | 32 | 0x0000 2034 + (0x200 * k) | 0x40D1 2034 + (0x200 * k) |
EDMA_TPCC_SER_RN_k (3) | R | 32 | 0x0000 2038 + (0x200 * k) | 0x40D1 2038 + (0x200 * k) |
EDMA_TPCC_SERH_RN_k (3) | R | 32 | 0x0000 203C + (0x200 * k) | 0x40D1 203C + (0x200 * k) |
EDMA_TPCC_SECR_RN_k (3) | W | 32 | 0x0000 2040 + (0x200 * k) | 0x40D1 2040 + (0x200 * k) |
EDMA_TPCC_SECRH_RN_k (3) | W | 32 | 0x0000 2044 + (0x200 * k) | 0x40D1 2044 + (0x200 * k) |
EDMA_TPCC_IER_RN_k (3) | R | 32 | 0x0000 2050 + (0x200 * k) | 0x40D1 2050 + (0x200 * k) |
EDMA_TPCC_IERH_RN_k (3) | R | 32 | 0x0000 2054 + (0x200 * k) | 0x40D1 2054 + (0x200 * k) |
EDMA_TPCC_IECR_RN_k (3) | W | 32 | 0x0000 2058 + (0x200 * k) | 0x40D1 2058 + (0x200 * k) |
EDMA_TPCC_IECRH_RN_k (3) | W | 32 | 0x0000 205C + (0x200 * k) | 0x40D1 205C + (0x200 * k) |
EDMA_TPCC_IESR_RN_k (3) | W | 32 | 0x0000 2060 + (0x200 * k) | 0x40D1 2060 + (0x200 * k) |
EDMA_TPCC_IESRH_RN_k (3) | W | 32 | 0x0000 2064 + (0x200 * k) | 0x40D1 2064 + (0x200 * k) |
EDMA_TPCC_IPR_RN_k (3) | R | 32 | 0x0000 2068 + (0x200 * k) | 0x40D1 2068 + (0x200 * k) |
EDMA_TPCC_IPRH_RN_k (3) | R | 32 | 0x0000 206C + (0x200 * k) | 0x40D1 206C + (0x200 * k) |
EDMA_TPCC_ICR_RN_k (3) | W | 32 | 0x0000 2070 + (0x200 * k) | 0x40D1 2070 + (0x200 * k) |
EDMA_TPCC_ICRH_RN_k (3) | W | 32 | 0x0000 2074 + (0x200 * k) | 0x40D1 2074 + (0x200 * k) |
EDMA_TPCC_IEVAL_RN_k (3) | W | 32 | 0x0000 2078 + (0x200 * k) | 0x40D1 2078 + (0x200 * k) |
EDMA_TPCC_QER_RN_k (3) | R | 32 | 0x0000 2080 + (0x200 * k) | 0x40D1 2080 + (0x200 * k) |
EDMA_TPCC_QEER_RN_k (3) | R | 32 | 0x0000 2084 + (0x200 * k) | 0x40D1 2084 + (0x200 * k) |
EDMA_TPCC_QEECR_RN_k (3) | W | 32 | 0x0000 2088 + (0x200 * k) | 0x40D1 2088 + (0x200 * k) |
EDMA_TPCC_QEESR_RN_k (3) | W | 32 | 0x0000 208C + (0x200 * k) | 0x40D1 208C + (0x200 * k) |
EDMA_TPCC_QSER_RN_k (3) | R | 32 | 0x0000 2090 + (0x200 * k) | 0x40D1 2090 + (0x200 * k) |
EDMA_TPCC_QSECR_RN_k (3) | W | 32 | 0x0000 2094 + (0x200 * k) | 0x40D1 2094 + (0x200 * k) |
EDMA_TPCC_OPT_n(6) | RW | 32 | 0x0000 4000 + (0x20 * n) | 0x40D1 4000 + (0x20 * n) |
EDMA_TPCC_SRC_n (6) | RW | 32 | 0x0000 4004 + (0x20 * n) | 0x40D1 4004 + (0x20 * n) |
EDMA_TPCC_ABCNT_n (6) | RW | 32 | 0x0000 4008 + (0x20 * n) | 0x40D1 4008 + (0x20 * n) |
EDMA_TPCC_DST_n (6) | RW | 32 | 0x0000 400C + (0x20 * n) | 0x40D1 400C + (0x20 * n) |
EDMA_TPCC_BIDX_n (6) | RW | 32 | 0x0000 4010 + (0x20 * n) | 0x40D1 4010 + (0x20 * n) |
EDMA_TPCC_LNK_n (6) | RW | 32 | 0x0000 4014 + (0x20 * n) | 0x40D1 4014 + (0x20 * n) |
EDMA_TPCC_CIDX_n (6) | RW | 32 | 0x0000 4018 + (0x20 * n) | 0x40D1 4018 + (0x20 * n) |
EDMA_TPCC_CCNT_n (6) | RW | 32 | 0x0000 401C + (0x20 * n) | 0x40D1 401C + (0x20 * n) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP2_EDMA_TPCC Physical Address (L3_MAIN Access) |
---|---|---|---|---|
EDMA_TPCC_PID | R | 32 | 0x0000 0000 | 0x4151 0000 |
EDMA_TPCC_CCCFG | R | 32 | 0x0000 0004 | 0x4151 0004 |
EDMA_TPCC_CLKGDIS | RW | 32 | 0x0000 00FC | 0x4151 00FC |
EDMA_TPCC_DCHMAPN_m (5) | RW | 32 | 0x0000 0100 + (0x4 * m) | 0x4151 0100 + (0x4 * m) |
EDMA_TPCC_QCHMAPN_j (2) | RW | 32 | 0x0000 0200 + (0x4 * j) | 0x4151 0200 + (0x4 * j) |
EDMA_TPCC_DMAQNUMN_k (3) | RW | 32 | 0x0000 0240 + (0x4 * k) | 0x4151 0240 + (0x4 * k) |
EDMA_TPCC_QDMAQNUM | RW | 32 | 0x0000 0260 | 0x4151 0260 |
EDMA_TPCC_QUETCMAP | RW | 32 | 0x0000 0280 | 0x4151 0280 |
EDMA_TPCC_QUEPRI | RW | 32 | 0x0000 0284 | 0x4151 0284 |
EDMA_TPCC_EMR | R | 32 | 0x0000 0300 | 0x4151 0300 |
EDMA_TPCC_EMRH | R | 32 | 0x0000 0304 | 0x4151 0304 |
EDMA_TPCC_EMCR | W | 32 | 0x0000 0308 | 0x4151 0308 |
EDMA_TPCC_EMCRH | W | 32 | 0x0000 030C | 0x4151 030C |
EDMA_TPCC_QEMR | R | 32 | 0x0000 0310 | 0x4151 0310 |
EDMA_TPCC_QEMCR | W | 32 | 0x0000 0314 | 0x4151 0314 |
EDMA_TPCC_CCERR | R | 32 | 0x0000 0318 | 0x4151 0318 |
EDMA_TPCC_CCERRCLR | W | 32 | 0x0000 031C | 0x4151 031C |
EDMA_TPCC_EEVAL | W | 32 | 0x0000 0320 | 0x4151 0320 |
EDMA_TPCC_DRAEM_k (3) | RW | 32 | 0x0000 0340 + (0x8 * k) | 0x4151 0340 + (0x8 * k) |
EDMA_TPCC_DRAEHM_k (3) | RW | 32 | 0x0000 0344 + (0x8 * k) | 0x4151 0344 + (0x8 * k) |
EDMA_TPCC_QRAEN_k (3) | RW | 32 | 0x0000 0380 + (0x4 * k) | 0x4151 0380 + (0x4 * k) |
EDMA_TPCC_Q0E_p (4) | R | 32 | 0x0000 0400 + (0x4 * p) | 0x4151 0400 + (0x4 * p) |
EDMA_TPCC_Q1E_p (4) | R | 32 | 0x0000 0440 + (0x4 * p) | 0x4151 0440 + (0x4 * p) |
EDMA_TPCC_QSTATN_i (1) | R | 32 | 0x0000 0600 + (0x4 * i) | 0x4151 0600 + (0x4 * i) |
EDMA_TPCC_QWMTHRA | RW | 32 | 0x0000 0620 | 0x4151 0620 |
EDMA_TPCC_QWMTHRB | RW | 32 | 0x0000 0624 | 0x4151 0624 |
EDMA_TPCC_CCSTAT | R | 32 | 0x0000 0640 | 0x4151 0640 |
EDMA_TPCC_AETCTL | RW | 32 | 0x0000 0700 | 0x4151 0700 |
EDMA_TPCC_AETSTAT | R | 32 | 0x0000 0704 | 0x4151 0704 |
EDMA_TPCC_AETCMD | W | 32 | 0x0000 0708 | 0x4151 0708 |
EDMA_TPCC_MPFAR | R | 32 | 0x0000 0800 | 0x4151 0800 |
EDMA_TPCC_MPFSR | R | 32 | 0x0000 0804 | 0x4151 0804 |
EDMA_TPCC_MPFCR | W | 32 | 0x0000 0808 | 0x4151 0808 |
EDMA_TPCC_MPPAG | RW | 32 | 0x0000 080C | 0x4151 080C |
EDMA_TPCC_MPPAN_k (3) | RW | 32 | 0x0000 0810 + (0x4 * k) | 0x4151 0810 + (0x4 * k) |
EDMA_TPCC_ER | R | 32 | 0x0000 1000 | 0x4151 1000 |
EDMA_TPCC_ERH | R | 32 | 0x0000 1004 | 0x4151 1004 |
EDMA_TPCC_ECR | W | 32 | 0x0000 1008 | 0x4151 1008 |
EDMA_TPCC_ECRH | W | 32 | 0x0000 100C | 0x4151 100C |
EDMA_TPCC_ESR | W | 32 | 0x0000 1010 | 0x4151 1010 |
EDMA_TPCC_ESRH | W | 32 | 0x0000 1014 | 0x4151 1014 |
EDMA_TPCC_CER | R | 32 | 0x0000 1018 | 0x4151 1018 |
EDMA_TPCC_CERH | R | 32 | 0x0000 101C | 0x4151 101C |
EDMA_TPCC_EER | R | 32 | 0x0000 1020 | 0x4151 1020 |
EDMA_TPCC_EERH | R | 32 | 0x0000 1024 | 0x4151 1024 |
EDMA_TPCC_EECR | W | 32 | 0x0000 1028 | 0x4151 1028 |
EDMA_TPCC_EECRH | W | 32 | 0x0000 102C | 0x4151 102C |
EDMA_TPCC_EESR | W | 32 | 0x0000 1030 | 0x4151 1030 |
EDMA_TPCC_EESRH | W | 32 | 0x0000 1034 | 0x4151 1034 |
EDMA_TPCC_SER | R | 32 | 0x0000 1038 | 0x4151 1038 |
EDMA_TPCC_SERH | R | 32 | 0x0000 103C | 0x4151 103C |
EDMA_TPCC_SECR | W | 32 | 0x0000 1040 | 0x4151 1040 |
EDMA_TPCC_SECRH | W | 32 | 0x0000 1044 | 0x4151 1044 |
EDMA_TPCC_IER | R | 32 | 0x0000 1050 | 0x4151 1050 |
EDMA_TPCC_IERH | R | 32 | 0x0000 1054 | 0x4151 1054 |
EDMA_TPCC_IECR | W | 32 | 0x0000 1058 | 0x4151 1058 |
EDMA_TPCC_IECRH | W | 32 | 0x0000 105C | 0x4151 105C |
EDMA_TPCC_IESR | W | 32 | 0x0000 1060 | 0x4151 1060 |
EDMA_TPCC_IESRH | W | 32 | 0x0000 1064 | 0x4151 1064 |
EDMA_TPCC_IPR | R | 32 | 0x0000 1068 | 0x4151 1068 |
EDMA_TPCC_IPRH | R | 32 | 0x0000 106C | 0x4151 106C |
EDMA_TPCC_ICR | W | 32 | 0x0000 1070 | 0x4151 1070 |
EDMA_TPCC_ICRH | W | 32 | 0x0000 1074 | 0x4151 1074 |
EDMA_TPCC_IEVAL | W | 32 | 0x0000 1078 | 0x4151 1078 |
EDMA_TPCC_QER | R | 32 | 0x0000 1080 | 0x4151 1080 |
EDMA_TPCC_QEER | R | 32 | 0x0000 1084 | 0x4151 1084 |
EDMA_TPCC_QEECR | W | 32 | 0x0000 1088 | 0x4151 1088 |
EDMA_TPCC_QEESR | W | 32 | 0x0000 108C | 0x4151 108C |
EDMA_TPCC_QSER | R | 32 | 0x0000 1090 | 0x4151 1090 |
EDMA_TPCC_QSECR | W | 32 | 0x0000 1094 | 0x4151 1094 |
EDMA_TPCC_ER_RN_k (3) | R | 32 | 0x0000 2000 + (0x200 * k) | 0x4151 2000 + (0x200 * k) |
EDMA_TPCC_ERH_RN_k (3) | R | 32 | 0x0000 2004 + (0x200 * k) | 0x4151 2004 + (0x200 * k) |
EDMA_TPCC_ECR_RN_k (3) | W | 32 | 0x0000 2008 + (0x200 * k) | 0x4151 2008 + (0x200 * k) |
EDMA_TPCC_ECRH_RN_k (3) | W | 32 | 0x0000 200C + (0x200 * k) | 0x4151 200C + (0x200 * k) |
EDMA_TPCC_ESR_RN_k (3) | W | 32 | 0x0000 2010 + (0x200 * k) | 0x4151 2010 + (0x200 * k) |
EDMA_TPCC_ESRH_RN_k (3) | W | 32 | 0x0000 2014 + (0x200 * k) | 0x4151 2014 + (0x200 * k) |
EDMA_TPCC_CER_RN_k (3) | R | 32 | 0x0000 2018 + (0x200 * k) | 0x4151 2018 + (0x200 * k) |
EDMA_TPCC_CERH_RN_k (3) | R | 32 | 0x0000 201C + (0x200 * k) | 0x4151 201C + (0x200 * k) |
EDMA_TPCC_EER_RN_k (3) | R | 32 | 0x0000 2020 + (0x200 * k) | 0x4151 2020 + (0x200 * k) |
EDMA_TPCC_EERH_RN_k (3) | R | 32 | 0x0000 2024 + (0x200 * k) | 0x4151 2024 + (0x200 * k) |
EDMA_TPCC_EECR_RN_k (3) | W | 32 | 0x0000 2028 + (0x200 * k) | 0x4151 2028 + (0x200 * k) |
EDMA_TPCC_EECRH_RN_k (3) | W | 32 | 0x0000 202C + (0x200 * k) | 0x4151 202C + (0x200 * k) |
EDMA_TPCC_EESR_RN_k (3) | W | 32 | 0x0000 2030 + (0x200 * k) | 0x4151 2030 + (0x200 * k) |
EDMA_TPCC_EESRH_RN_k (3) | W | 32 | 0x0000 2034 + (0x200 * k) | 0x4151 2034 + (0x200 * k) |
EDMA_TPCC_SER_RN_k (3) | R | 32 | 0x0000 2038 + (0x200 * k) | 0x4151 2038 + (0x200 * k) |
EDMA_TPCC_SERH_RN_k (3) | R | 32 | 0x0000 203C + (0x200 * k) | 0x4151 203C + (0x200 * k) |
EDMA_TPCC_SECR_RN_k (3) | W | 32 | 0x0000 2040 + (0x200 * k) | 0x4151 2040 + (0x200 * k) |
EDMA_TPCC_SECRH_RN_k (3) | W | 32 | 0x0000 2044 + (0x200 * k) | 0x4151 2044 + (0x200 * k) |
EDMA_TPCC_IER_RN_k (3) | R | 32 | 0x0000 2050 + (0x200 * k) | 0x4151 2050 + (0x200 * k) |
EDMA_TPCC_IERH_RN_k (3) | R | 32 | 0x0000 2054 + (0x200 * k) | 0x4151 2054 + (0x200 * k) |
EDMA_TPCC_IECR_RN_k (3) | W | 32 | 0x0000 2058 + (0x200 * k) | 0x4151 2058 + (0x200 * k) |
EDMA_TPCC_IECRH_RN_k (3) | W | 32 | 0x0000 205C + (0x200 * k) | 0x4151 205C + (0x200 * k) |
EDMA_TPCC_IESR_RN_k (3) | W | 32 | 0x0000 2060 + (0x200 * k) | 0x4151 2060 + (0x200 * k) |
EDMA_TPCC_IESRH_RN_k (3) | W | 32 | 0x0000 2064 + (0x200 * k) | 0x4151 2064 + (0x200 * k) |
EDMA_TPCC_IPR_RN_k (3) | R | 32 | 0x0000 2068 + (0x200 * k) | 0x4151 2068 + (0x200 * k) |
EDMA_TPCC_IPRH_RN_k (3) | R | 32 | 0x0000 206C + (0x200 * k) | 0x4151 206C + (0x200 * k) |
EDMA_TPCC_ICR_RN_k (3) | W | 32 | 0x0000 2070 + (0x200 * k) | 0x4151 2070 + (0x200 * k) |
EDMA_TPCC_ICRH_RN_k (3) | W | 32 | 0x0000 2074 + (0x200 * k) | 0x4151 2074 + (0x200 * k) |
EDMA_TPCC_IEVAL_RN_k (3) | W | 32 | 0x0000 2078 + (0x200 * k) | 0x4151 2078 + (0x200 * k) |
EDMA_TPCC_QER_RN_k (3) | R | 32 | 0x0000 2080 + (0x200 * k) | 0x4151 2080 + (0x200 * k) |
EDMA_TPCC_QEER_RN_k (3) | R | 32 | 0x0000 2084 + (0x200 * k) | 0x4151 2084 + (0x200 * k) |
EDMA_TPCC_QEECR_RN_k (3) | W | 32 | 0x0000 2088 + (0x200 * k) | 0x4151 2088 + (0x200 * k) |
EDMA_TPCC_QEESR_RN_k (3) | W | 32 | 0x0000 208C + (0x200 * k) | 0x4151 208C + (0x200 * k) |
EDMA_TPCC_QSER_RN_k (3) | R | 32 | 0x0000 2090 + (0x200 * k) | 0x4151 2090 + (0x200 * k) |
EDMA_TPCC_QSECR_RN_k (3) | W | 32 | 0x0000 2094 + (0x200 * k) | 0x4151 2094 + (0x200 * k) |
EDMA_TPCC_OPT_n(6) | RW | 32 | 0x0000 4000 + (0x20 * n) | 0x4151 4000 + (0x20 * n) |
EDMA_TPCC_SRC_n (6) | RW | 32 | 0x0000 4004 + (0x20 * n) | 0x4151 4004 + (0x20 * n) |
EDMA_TPCC_ABCNT_n (6) | RW | 32 | 0x0000 4008 + (0x20 * n) | 0x4151 4008 + (0x20 * n) |
EDMA_TPCC_DST_n (6) | RW | 32 | 0x0000 400C + (0x20 * n) | 0x4151 400C + (0x20 * n) |
EDMA_TPCC_BIDX_n (6) | RW | 32 | 0x0000 4010 + (0x20 * n) | 0x4151 4010 + (0x20 * n) |
EDMA_TPCC_LNK_n (6) | RW | 32 | 0x0000 4014 + (0x20 * n) | 0x4151 4014 + (0x20 * n) |
EDMA_TPCC_CIDX_n (6) | RW | 32 | 0x0000 4018 + (0x20 * n) | 0x4151 4018 + (0x20 * n) |
EDMA_TPCC_CCNT_n (6) | RW | 32 | 0x0000 401C + (0x20 * n) | 0x4151 401C + (0x20 * n) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP_EDMA_TPCC Physical Address (DSP Private Access) |
---|---|---|---|---|
EDMA_TPCC_PID | R | 32 | 0x0000 0000 | 0x01D1 0000 |
EDMA_TPCC_CCCFG | R | 32 | 0x0000 0004 | 0x01D1 0004 |
EDMA_TPCC_CLKGDIS | RW | 32 | 0x0000 00FC | 0x01D1 00FC |
EDMA_TPCC_DCHMAPN_m (5) | RW | 32 | 0x0000 0100 + (0x4 * m) | 0x01D1 0100 + (0x4 * m) |
EDMA_TPCC_QCHMAPN_j (2) | RW | 32 | 0x0000 0200 + (0x4 * j) | 0x01D1 0200 + (0x4 * j) |
EDMA_TPCC_DMAQNUMN_k (3) | RW | 32 | 0x0000 0240 + (0x4 * k) | 0x01D1 0240 + (0x4 * k) |
EDMA_TPCC_QDMAQNUM | RW | 32 | 0x0000 0260 | 0x01D1 0260 |
EDMA_TPCC_QUETCMAP | RW | 32 | 0x0000 0280 | 0x01D1 0280 |
EDMA_TPCC_QUEPRI | RW | 32 | 0x0000 0284 | 0x01D1 0284 |
EDMA_TPCC_EMR | R | 32 | 0x0000 0300 | 0x01D1 0300 |
EDMA_TPCC_EMRH | R | 32 | 0x0000 0304 | 0x01D1 0304 |
EDMA_TPCC_EMCR | W | 32 | 0x0000 0308 | 0x01D1 0308 |
EDMA_TPCC_EMCRH | W | 32 | 0x0000 030C | 0x01D1 030C |
EDMA_TPCC_QEMR | R | 32 | 0x0000 0310 | 0x01D1 0310 |
EDMA_TPCC_QEMCR | W | 32 | 0x0000 0314 | 0x01D1 0314 |
EDMA_TPCC_CCERR | R | 32 | 0x0000 0318 | 0x01D1 0318 |
EDMA_TPCC_CCERRCLR | W | 32 | 0x0000 031C | 0x01D1 031C |
EDMA_TPCC_EEVAL | W | 32 | 0x0000 0320 | 0x01D1 0320 |
EDMA_TPCC_DRAEM_k (3) | RW | 32 | 0x0000 0340 + (0x8 * k) | 0x01D1 0340 + (0x8 * k) |
EDMA_TPCC_DRAEHM_k (3) | RW | 32 | 0x0000 0344 + (0x8 * k) | 0x01D1 0344 + (0x8 * k) |
EDMA_TPCC_QRAEN_k (3) | RW | 32 | 0x0000 0380 + (0x4 * k) | 0x01D1 0380 + (0x4 * k) |
EDMA_TPCC_Q0E_p (4) | R | 32 | 0x0000 0400 + (0x4 *pl) | 0x01D1 0400 + (0x4 * p) |
EDMA_TPCC_Q1E_p (4) | R | 32 | 0x0000 0440 + (0x4 * p) | 0x01D1 0440 + (0x4 * p) |
EDMA_TPCC_QSTATN_i (1) | R | 32 | 0x0000 0600 + (0x4 * i) | 0x01D1 0600 + (0x4 * i) |
EDMA_TPCC_QWMTHRA | RW | 32 | 0x0000 0620 | 0x01D1 0620 |
EDMA_TPCC_QWMTHRB | RW | 32 | 0x0000 0624 | 0x01D1 0624 |
EDMA_TPCC_CCSTAT | R | 32 | 0x0000 0640 | 0x01D1 0640 |
EDMA_TPCC_AETCTL | RW | 32 | 0x0000 0700 | 0x01D1 0700 |
EDMA_TPCC_AETSTAT | R | 32 | 0x0000 0704 | 0x01D1 0704 |
EDMA_TPCC_AETCMD | W | 32 | 0x0000 0708 | 0x01D1 0708 |
EDMA_TPCC_MPFAR | R | 32 | 0x0000 0800 | 0x01D1 0800 |
EDMA_TPCC_MPFSR | R | 32 | 0x0000 0804 | 0x01D1 0804 |
EDMA_TPCC_MPFCR | W | 32 | 0x0000 0808 | 0x01D1 0808 |
EDMA_TPCC_MPPAG | RW | 32 | 0x0000 080C | 0x01D1 080C |
EDMA_TPCC_MPPAN_k (3) | RW | 32 | 0x0000 0810 + (0x4 * k) | 0x01D1 0810 + (0x4 * k) |
EDMA_TPCC_ER | R | 32 | 0x0000 1000 | 0x01D1 1000 |
EDMA_TPCC_ERH | R | 32 | 0x0000 1004 | 0x01D1 1004 |
EDMA_TPCC_ECR | W | 32 | 0x0000 1008 | 0x01D1 1008 |
EDMA_TPCC_ECRH | W | 32 | 0x0000 100C | 0x01D1 100C |
EDMA_TPCC_ESR | W | 32 | 0x0000 1010 | 0x01D1 1010 |
EDMA_TPCC_ESRH | W | 32 | 0x0000 1014 | 0x01D1 1014 |
EDMA_TPCC_CER | R | 32 | 0x0000 1018 | 0x01D1 1018 |
EDMA_TPCC_CERH | R | 32 | 0x0000 101C | 0x01D1 101C |
EDMA_TPCC_EER | R | 32 | 0x0000 1020 | 0x01D1 1020 |
EDMA_TPCC_EERH | R | 32 | 0x0000 1024 | 0x01D1 1024 |
EDMA_TPCC_EECR | W | 32 | 0x0000 1028 | 0x01D1 1028 |
EDMA_TPCC_EECRH | W | 32 | 0x0000 102C | 0x01D1 102C |
EDMA_TPCC_EESR | W | 32 | 0x0000 1030 | 0x01D1 1030 |
EDMA_TPCC_EESRH | W | 32 | 0x0000 1034 | 0x01D1 1034 |
EDMA_TPCC_SER | R | 32 | 0x0000 1038 | 0x01D1 1038 |
EDMA_TPCC_SERH | R | 32 | 0x0000 103C | 0x01D1 103C |
EDMA_TPCC_SECR | W | 32 | 0x0000 1040 | 0x01D1 1040 |
EDMA_TPCC_SECRH | W | 32 | 0x0000 1044 | 0x01D1 1044 |
EDMA_TPCC_IER | R | 32 | 0x0000 1050 | 0x01D1 1050 |
EDMA_TPCC_IERH | R | 32 | 0x0000 1054 | 0x01D1 1054 |
EDMA_TPCC_IECR | W | 32 | 0x0000 1058 | 0x01D1 1058 |
EDMA_TPCC_IECRH | W | 32 | 0x0000 105C | 0x01D1 105C |
EDMA_TPCC_IESR | W | 32 | 0x0000 1060 | 0x01D1 1060 |
EDMA_TPCC_IESRH | W | 32 | 0x0000 1064 | 0x01D1 1064 |
EDMA_TPCC_IPR | R | 32 | 0x0000 1068 | 0x01D1 1068 |
EDMA_TPCC_IPRH | R | 32 | 0x0000 106C | 0x01D1 106C |
EDMA_TPCC_ICR | W | 32 | 0x0000 1070 | 0x01D1 1070 |
EDMA_TPCC_ICRH | W | 32 | 0x0000 1074 | 0x01D1 1074 |
EDMA_TPCC_IEVAL | W | 32 | 0x0000 1078 | 0x01D1 1078 |
EDMA_TPCC_QER | R | 32 | 0x0000 1080 | 0x01D1 1080 |
EDMA_TPCC_QEER | R | 32 | 0x0000 1084 | 0x01D1 1084 |
EDMA_TPCC_QEECR | W | 32 | 0x0000 1088 | 0x01D1 1088 |
EDMA_TPCC_QEESR | W | 32 | 0x0000 108C | 0x01D1 108C |
EDMA_TPCC_QSER | R | 32 | 0x0000 1090 | 0x01D1 1090 |
EDMA_TPCC_QSECR | W | 32 | 0x0000 1094 | 0x01D1 1094 |
EDMA_TPCC_ER_RN_k (3) | R | 32 | 0x0000 2000 + (0x200 * k) | 0x01D1 2000 + (0x200 * k) |
EDMA_TPCC_ERH_RN_k (3) | R | 32 | 0x0000 2004 + (0x200 * k) | 0x01D1 2004 + (0x200 * k) |
EDMA_TPCC_ECR_RN_k (3) | W | 32 | 0x0000 2008 + (0x200 * k) | 0x01D1 2008 + (0x200 * k) |
EDMA_TPCC_ECRH_RN_k (3) | W | 32 | 0x0000 200C + (0x200 * k) | 0x01D1 200C + (0x200 * k) |
EDMA_TPCC_ESR_RN_k (3) | W | 32 | 0x0000 2010 + (0x200 * k) | 0x01D1 2010 + (0x200 * k) |
EDMA_TPCC_ESRH_RN_k (3) | W | 32 | 0x0000 2014 + (0x200 * k) | 0x01D1 2014 + (0x200 * k) |
EDMA_TPCC_CER_RN_k (3) | R | 32 | 0x0000 2018 + (0x200 * k) | 0x01D1 2018 + (0x200 * k) |
EDMA_TPCC_CERH_RN_k (3) | R | 32 | 0x0000 201C + (0x200 * k) | 0x01D1 201C + (0x200 * k) |
EDMA_TPCC_EER_RN_k (3) | R | 32 | 0x0000 2020 + (0x200 * k) | 0x01D1 2020 + (0x200 * k) |
EDMA_TPCC_EERH_RN_k (3) | R | 32 | 0x0000 2024 + (0x200 * k) | 0x01D1 2024 + (0x200 * k) |
EDMA_TPCC_EECR_RN_k (3) | W | 32 | 0x0000 2028 + (0x200 * k) | 0x01D1 2028 + (0x200 * k) |
EDMA_TPCC_EECRH_RN_k (3) | W | 32 | 0x0000 202C + (0x200 * k) | 0x01D1 202C + (0x200 * k) |
EDMA_TPCC_EESR_RN_k (3) | W | 32 | 0x0000 2030 + (0x200 * k) | 0x01D1 2030 + (0x200 * k) |
EDMA_TPCC_EESRH_RN_k (3) | W | 32 | 0x0000 2034 + (0x200 * k) | 0x01D1 2034 + (0x200 * k) |
EDMA_TPCC_SER_RN_k (3) | R | 32 | 0x0000 2038 + (0x200 * k) | 0x01D1 2038 + (0x200 * k) |
EDMA_TPCC_SERH_RN_k (3) | R | 32 | 0x0000 203C + (0x200 * k) | 0x01D1 203C + (0x200 * k) |
EDMA_TPCC_SECR_RN_k (3) | W | 32 | 0x0000 2040 + (0x200 * k) | 0x01D1 2040 + (0x200 * k) |
EDMA_TPCC_SECRH_RN_k (3) | W | 32 | 0x0000 2044 + (0x200 * k) | 0x01D1 2044 + (0x200 * k) |
EDMA_TPCC_IER_RN_k (3) | R | 32 | 0x0000 2050 + (0x200 * k) | 0x01D1 2050 + (0x200 * k) |
EDMA_TPCC_IERH_RN_k (3) | R | 32 | 0x0000 2054 + (0x200 * k) | 0x01D1 2054 + (0x200 * k) |
EDMA_TPCC_IECR_RN_k (3) | W | 32 | 0x0000 2058 + (0x200 * k) | 0x01D1 2058 + (0x200 * k) |
EDMA_TPCC_IECRH_RN_k (3) | W | 32 | 0x0000 205C + (0x200 * k) | 0x01D1 205C + (0x200 * k) |
EDMA_TPCC_IESR_RN_k (3) | W | 32 | 0x0000 2060 + (0x200 * k) | 0x01D1 2060 + (0x200 * k) |
EDMA_TPCC_IESRH_RN_k (3) | W | 32 | 0x0000 2064 + (0x200 * k) | 0x01D1 2064 + (0x200 * k) |
EDMA_TPCC_IPR_RN_k (3) | R | 32 | 0x0000 2068 + (0x200 * k) | 0x01D1 2068 + (0x200 * k) |
EDMA_TPCC_IPRH_RN_k (3) | R | 32 | 0x0000 206C + (0x200 * k) | 0x01D1 206C + (0x200 * k) |
EDMA_TPCC_ICR_RN_k (3) | W | 32 | 0x0000 2070 + (0x200 * k) | 0x01D1 2070 + (0x200 * k) |
EDMA_TPCC_ICRH_RN_k (3) | W | 32 | 0x0000 2074 + (0x200 * k) | 0x01D1 2074 + (0x200 * k) |
EDMA_TPCC_IEVAL_RN_k (3) | W | 32 | 0x0000 2078 + (0x200 * k) | 0x01D1 2078 + (0x200 * k) |
EDMA_TPCC_QER_RN_k (3) | R | 32 | 0x0000 2080 + (0x200 * k) | 0x01D1 2080 + (0x200 * k) |
EDMA_TPCC_QEER_RN_k (3) | R | 32 | 0x0000 2084 + (0x200 * k) | 0x01D1 2084 + (0x200 * k) |
EDMA_TPCC_QEECR_RN_k (3) | W | 32 | 0x0000 2088 + (0x200 * k) | 0x01D1 2088 + (0x200 * k) |
EDMA_TPCC_QEESR_RN_k (3) | W | 32 | 0x0000 208C + (0x200 * k) | 0x01D1 208C + (0x200 * k) |
EDMA_TPCC_QSER_RN_k (3) | R | 32 | 0x0000 2090 + (0x200 * k) | 0x01D1 2090 + (0x200 * k) |
EDMA_TPCC_QSECR_RN_k (3) | W | 32 | 0x0000 2094 + (0x200 * k) | 0x01D1 2094 + (0x200 * k) |
EDMA_TPCC_OPT_n(6) | RW | 32 | 0x0000 4000 + (0x20 * n) | 0x01D1 4000 + (0x20 * n) |
EDMA_TPCC_SRC_n (6) | RW | 32 | 0x0000 4004 + (0x20 * n) | 0x01D1 4004 + (0x20 * n) |
EDMA_TPCC_ABCNT_n (6) | RW | 32 | 0x0000 4008 + (0x20 * n) | 0x01D1 4008 + (0x20 * n) |
EDMA_TPCC_DST_n (6) | RW | 32 | 0x0000 400C + (0x20 * n) | 0x01D1 400C + (0x20 * n) |
EDMA_TPCC_BIDX_n (6) | RW | 32 | 0x0000 4010 + (0x20 * n) | 0x01D1 4010 + (0x20 * n) |
EDMA_TPCC_LNK_n (6) | RW | 32 | 0x0000 4014 + (0x20 * n) | 0x01D1 4014 + (0x20 * n) |
EDMA_TPCC_CIDX_n (6) | RW | 32 | 0x0000 4018 + (0x20 * n) | 0x01D1 4018 + (0x20 * n) |
EDMA_TPCC_CCNT_n (6) | RW | 32 | 0x0000 401C + (0x20 * n) | 0x01D1 401C + (0x20 * n) |
Register Name | Type | Register Width (Bits) | Address Offset | EVE1_EDMA_TPCC Physical Address (L3_MAIN Access) | EVE2_EDMA_TPCC Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPCC_PID | R | 32 | 0x0000 0000 | 0x420A 0000 | 0x421A 0000 |
EDMA_TPCC_CCCFG | R | 32 | 0x0000 0004 | 0x420A 0004 | 0x421A 0004 |
EDMA_TPCC_CLKGDIS | RW | 32 | 0x0000 00FC | 0x420A 00FC | 0x421A 00FC |
EDMA_TPCC_DCHMAPN_m (5) | RW | 32 | 0x0000 0100 + (0x4 * m) | 0x420A 0100 + (0x4 * m) | 0x421A 0100 + (0x4 * m) |
EDMA_TPCC_QCHMAPN_j (2) | RW | 32 | 0x0000 0200 + (0x4 * j) | 0x420A 0200 + (0x4 * j) | 0x421A 0200 + (0x4 * j) |
EDMA_TPCC_DMAQNUMN_k (3) | RW | 32 | 0x0000 0240 + (0x4 * k) | 0x420A 0240 + (0x4 * k) | 0x421A 0240 + (0x4 * k) |
EDMA_TPCC_QDMAQNUM | RW | 32 | 0x0000 0260 | 0x420A 0260 | 0x421A 0260 |
EDMA_TPCC_QUETCMAP | RW | 32 | 0x0000 0280 | 0x420A 0280 | 0x421A 0280 |
EDMA_TPCC_QUEPRI | RW | 32 | 0x0000 0284 | 0x420A 0284 | 0x421A 0284 |
EDMA_TPCC_EMR | R | 32 | 0x0000 0300 | 0x420A 0300 | 0x421A 0300 |
EDMA_TPCC_EMRH | R | 32 | 0x0000 0304 | 0x420A 0304 | 0x421A 0304 |
EDMA_TPCC_EMCR | W | 32 | 0x0000 0308 | 0x420A 0308 | 0x421A 0308 |
EDMA_TPCC_EMCRH | W | 32 | 0x0000 030C | 0x420A 030C | 0x421A 030C |
EDMA_TPCC_QEMR | R | 32 | 0x0000 0310 | 0x420A 0310 | 0x421A 0310 |
EDMA_TPCC_QEMCR | W | 32 | 0x0000 0314 | 0x420A 0314 | 0x421A 0314 |
EDMA_TPCC_CCERR | R | 32 | 0x0000 0318 | 0x420A 0318 | 0x421A 0318 |
EDMA_TPCC_CCERRCLR | W | 32 | 0x0000 031C | 0x420A 031C | 0x421A 031C |
EDMA_TPCC_EEVAL | W | 32 | 0x0000 0320 | 0x420A 0320 | 0x421A 0320 |
EDMA_TPCC_DRAEM_k (3) | RW | 32 | 0x0000 0340 + (0x8 * k) | - | - |
EDMA_TPCC_DRAEHM_k (3) | RW | 32 | 0x0000 0344 + (0x8 * k) | - | - |
EDMA_TPCC_QRAEN_k (3) | RW | 32 | 0x0000 0380 + (0x4 * k) | 0x420A 0380 + (0x4 * k) | 0x421A 0380 + (0x4 * k) |
EDMA_TPCC_Q0E_p (4) | R | 32 | 0x0000 0400 + (0x4 * p) | - | - |
EDMA_TPCC_Q1E_p (4) | R | 32 | 0x0000 0440 + (0x4 *pl) | - | - |
EDMA_TPCC_QSTATN_i (1) | R | 32 | 0x0000 0600 + (0x4 * i) | 0x420A 0600 + (0x4 * i) | 0x421A 0600 + (0x4 * i) |
EDMA_TPCC_QWMTHRA | RW | 32 | 0x0000 0620 | 0x420A 0620 | 0x421A 0620 |
EDMA_TPCC_QWMTHRB | RW | 32 | 0x0000 0624 | 0x420A 0624 | 0x421A 0624 |
EDMA_TPCC_CCSTAT | R | 32 | 0x0000 0640 | 0x420A 0640 | 0x421A 0640 |
EDMA_TPCC_AETCTL | RW | 32 | 0x0000 0700 | 0x420A 0700 | 0x421A 0700 |
EDMA_TPCC_AETSTAT | R | 32 | 0x0000 0704 | 0x420A 0704 | 0x421A 0704 |
EDMA_TPCC_AETCMD | W | 32 | 0x0000 0708 | 0x420A 0708 | 0x421A 0708 |
EDMA_TPCC_MPFAR | R | 32 | 0x0000 0800 | 0x420A 0800 | 0x421A 0800 |
EDMA_TPCC_MPFSR | R | 32 | 0x0000 0804 | 0x420A 0804 | 0x421A 0804 |
EDMA_TPCC_MPFCR | W | 32 | 0x0000 0808 | 0x420A 0808 | 0x421A 0808 |
EDMA_TPCC_MPPAG | RW | 32 | 0x0000 080C | 0x420A 080C | 0x421A 080C |
EDMA_TPCC_MPPAN_k (3) | RW | 32 | 0x0000 0810 + (0x4 * k) | 0x420A 0810 + (0x4 * k) | 0x421A 0810 + (0x4 * k) |
EDMA_TPCC_ER | R | 32 | 0x0000 1000 | 0x420A 1000 | 0x421A 1000 |
EDMA_TPCC_ERH | R | 32 | 0x0000 1004 | 0x420A 1004 | 0x421A 1004 |
EDMA_TPCC_ECR | W | 32 | 0x0000 1008 | 0x420A 1008 | 0x421A 1008 |
EDMA_TPCC_ECRH | W | 32 | 0x0000 100C | 0x420A 100C | 0x421A 100C |
EDMA_TPCC_ESR | W | 32 | 0x0000 1010 | 0x420A 1010 | 0x421A 1010 |
EDMA_TPCC_ESRH | W | 32 | 0x0000 1014 | 0x420A 1014 | 0x421A 1014 |
EDMA_TPCC_CER | R | 32 | 0x0000 1018 | 0x420A 1018 | 0x421A 1018 |
EDMA_TPCC_CERH | R | 32 | 0x0000 101C | 0x420A 101C | 0x421A 101C |
EDMA_TPCC_EER | R | 32 | 0x0000 1020 | 0x420A 1020 | 0x421A 1020 |
EDMA_TPCC_EERH | R | 32 | 0x0000 1024 | 0x420A 1024 | 0x421A 1024 |
EDMA_TPCC_EECR | W | 32 | 0x0000 1028 | 0x420A 1028 | 0x421A 1028 |
EDMA_TPCC_EECRH | W | 32 | 0x0000 102C | 0x420A 102C | 0x421A 102C |
EDMA_TPCC_EESR | W | 32 | 0x0000 1030 | 0x420A 1030 | 0x421A 1030 |
EDMA_TPCC_EESRH | W | 32 | 0x0000 1034 | 0x420A 1034 | 0x421A 1034 |
EDMA_TPCC_SER | R | 32 | 0x0000 1038 | 0x420A 1038 | 0x421A 1038 |
EDMA_TPCC_SERH | R | 32 | 0x0000 103C | 0x420A 103C | 0x421A 103C |
EDMA_TPCC_SECR | W | 32 | 0x0000 1040 | 0x420A 1040 | 0x421A 1040 |
EDMA_TPCC_SECRH | W | 32 | 0x0000 1044 | 0x420A 1044 | 0x421A 1044 |
EDMA_TPCC_IER | R | 32 | 0x0000 1050 | 0x420A 1050 | 0x421A 1050 |
EDMA_TPCC_IERH | R | 32 | 0x0000 1054 | 0x420A 1054 | 0x421A 1054 |
EDMA_TPCC_IECR | W | 32 | 0x0000 1058 | 0x420A 1058 | 0x421A 1058 |
EDMA_TPCC_IECRH | W | 32 | 0x0000 105C | 0x420A 105C | 0x421A 105C |
EDMA_TPCC_IESR | W | 32 | 0x0000 1060 | 0x420A 1060 | 0x421A 1060 |
EDMA_TPCC_IESRH | W | 32 | 0x0000 1064 | 0x420A 1064 | 0x421A 1064 |
EDMA_TPCC_IPR | R | 32 | 0x0000 1068 | 0x420A 1068 | 0x421A 1068 |
EDMA_TPCC_IPRH | R | 32 | 0x0000 106C | 0x420A 106C | 0x421A 106C |
EDMA_TPCC_ICR | W | 32 | 0x0000 1070 | 0x420A 1070 | 0x421A 1070 |
EDMA_TPCC_ICRH | W | 32 | 0x0000 1074 | 0x420A 1074 | 0x421A 1074 |
EDMA_TPCC_IEVAL | W | 32 | 0x0000 1078 | 0x420A 1078 | 0x421A 1078 |
EDMA_TPCC_QER | R | 32 | 0x0000 1080 | 0x420A 1080 | 0x421A 1080 |
EDMA_TPCC_QEER | R | 32 | 0x0000 1084 | 0x420A 1084 | 0x421A 1084 |
EDMA_TPCC_QEECR | W | 32 | 0x0000 1088 | 0x420A 1088 | 0x421A 1088 |
EDMA_TPCC_QEESR | W | 32 | 0x0000 108C | 0x420A 108C | 0x421A 108C |
EDMA_TPCC_QSER | R | 32 | 0x0000 1090 | 0x420A 1090 | 0x421A 1090 |
EDMA_TPCC_QSECR | W | 32 | 0x0000 1094 | 0x420A 1094 | 0x421A 1094 |
EDMA_TPCC_ER_RN_k (3) | R | 32 | 0x0000 2000 + (0x200 * k) | 0x420A 2000 + (0x200 * k) | 0x421A 2000 + (0x200 * k) |
EDMA_TPCC_ERH_RN_k (3) | R | 32 | 0x0000 2004 + (0x200 * k) | 0x420A 2004 + (0x200 * k) | 0x421A 2004 + (0x200 * k) |
EDMA_TPCC_ECR_RN_k (3) | W | 32 | 0x0000 2008 + (0x200 * k) | 0x420A 2008 + (0x200 * k) | 0x421A 2008 + (0x200 * k) |
EDMA_TPCC_ECRH_RN_k (3) | W | 32 | 0x0000 200C + (0x200 * k) | 0x420A 200C + (0x200 * k) | 0x421A 200C + (0x200 * k) |
EDMA_TPCC_ESR_RN_k (3) | W | 32 | 0x0000 2010 + (0x200 * k) | 0x420A 2010 + (0x200 * k) | 0x421A 2010 + (0x200 * k) |
EDMA_TPCC_ESRH_RN_k (3) | W | 32 | 0x0000 2014 + (0x200 * k) | 0x420A 2014 + (0x200 * k) | 0x421A 2014 + (0x200 * k) |
EDMA_TPCC_CER_RN_k (3) | R | 32 | 0x0000 2018 + (0x200 * k) | 0x420A 2018 + (0x200 * k) | 0x421A 2018 + (0x200 * k) |
EDMA_TPCC_CERH_RN_k (3) | R | 32 | 0x0000 201C + (0x200 * k) | 0x420A 201C + (0x200 * k) | 0x421A 201C + (0x200 * k) |
EDMA_TPCC_EER_RN_k (3) | R | 32 | 0x0000 2020 + (0x200 * k) | 0x420A 2020 + (0x200 * k) | 0x421A 2020 + (0x200 * k) |
EDMA_TPCC_EERH_RN_k (3) | R | 32 | 0x0000 2024 + (0x200 * k) | 0x420A 2024 + (0x200 * k) | 0x421A 2024 + (0x200 * k) |
EDMA_TPCC_EECR_RN_k (3) | W | 32 | 0x0000 2028 + (0x200 * k) | 0x420A 2028 + (0x200 * k) | 0x421A 2028 + (0x200 * k) |
EDMA_TPCC_EECRH_RN_k (3) | W | 32 | 0x0000 202C + (0x200 * k) | 0x420A 202C + (0x200 * k) | 0x421A 202C + (0x200 * k) |
EDMA_TPCC_EESR_RN_k (3) | W | 32 | 0x0000 2030 + (0x200 * k) | 0x420A 2030 + (0x200 * k) | 0x421A 2030 + (0x200 * k) |
EDMA_TPCC_EESRH_RN_k (3) | W | 32 | 0x0000 2034 + (0x200 * k) | 0x420A 2034 + (0x200 * k) | 0x421A 2034 + (0x200 * k) |
EDMA_TPCC_SER_RN_k (3) | R | 32 | 0x0000 2038 + (0x200 * k) | 0x420A 2038 + (0x200 * k) | 0x421A 2038 + (0x200 * k) |
EDMA_TPCC_SERH_RN_k (3) | R | 32 | 0x0000 203C + (0x200 * k) | 0x420A 203C + (0x200 * k) | 0x421A 203C + (0x200 * k) |
EDMA_TPCC_SECR_RN_k (3) | W | 32 | 0x0000 2040 + (0x200 * k) | 0x420A 2040 + (0x200 * k) | 0x421A 2040 + (0x200 * k) |
EDMA_TPCC_SECRH_RN_k (3) | W | 32 | 0x0000 2044 + (0x200 * k) | 0x420A 2044 + (0x200 * k) | 0x421A 2044 + (0x200 * k) |
EDMA_TPCC_IER_RN_k (3) | R | 32 | 0x0000 2050 + (0x200 * k) | 0x420A 2050 + (0x200 * k) | 0x421A 2050 + (0x200 * k) |
EDMA_TPCC_IERH_RN_k (3) | R | 32 | 0x0000 2054 + (0x200 * k) | 0x420A 2054 + (0x200 * k) | 0x421A 2054 + (0x200 * k) |
EDMA_TPCC_IECR_RN_k (3) | W | 32 | 0x0000 2058 + (0x200 * k) | 0x420A 2058 + (0x200 * k) | 0x421A 2058 + (0x200 * k) |
EDMA_TPCC_IECRH_RN_k (3) | W | 32 | 0x0000 205C + (0x200 * k) | 0x420A 205C + (0x200 * k) | 0x421A 205C + (0x200 * k) |
EDMA_TPCC_IESR_RN_k (3) | W | 32 | 0x0000 2060 + (0x200 * k) | 0x420A 2060 + (0x200 * k) | 0x421A 2060 + (0x200 * k) |
EDMA_TPCC_IESRH_RN_k (3) | W | 32 | 0x0000 2064 + (0x200 * k) | 0x420A 2064 + (0x200 * k) | 0x421A 2064 + (0x200 * k) |
EDMA_TPCC_IPR_RN_k (3) | R | 32 | 0x0000 2068 + (0x200 * k) | 0x420A 2068 + (0x200 * k) | 0x421A 2068 + (0x200 * k) |
EDMA_TPCC_IPRH_RN_k (3) | R | 32 | 0x0000 206C + (0x200 * k) | 0x420A 206C + (0x200 * k) | 0x421A 206C + (0x200 * k) |
EDMA_TPCC_ICR_RN_k (3) | W | 32 | 0x0000 2070 + (0x200 * k) | 0x420A 2070 + (0x200 * k) | 0x421A 2070 + (0x200 * k) |
EDMA_TPCC_ICRH_RN_k (3) | W | 32 | 0x0000 2074 + (0x200 * k) | 0x420A 2074 + (0x200 * k) | 0x421A 2074 + (0x200 * k) |
EDMA_TPCC_IEVAL_RN_k (3) | W | 32 | 0x0000 2078 + (0x200 * k) | 0x420A 2078 + (0x200 * k) | 0x421A 2078 + (0x200 * k) |
EDMA_TPCC_QER_RN_k (3) | R | 32 | 0x0000 2080 + (0x200 * k) | 0x420A 2080 + (0x200 * k) | 0x421A 2080 + (0x200 * k) |
EDMA_TPCC_QEER_RN_k (3) | R | 32 | 0x0000 2084 + (0x200 * k) | 0x420A 2084 + (0x200 * k) | 0x421A 2084 + (0x200 * k) |
EDMA_TPCC_QEECR_RN_k (3) | W | 32 | 0x0000 2088 + (0x200 * k) | 0x420A 2088 + (0x200 * k) | 0x421A 2088 + (0x200 * k) |
EDMA_TPCC_QEESR_RN_k (3) | W | 32 | 0x0000 208C + (0x200 * k) | 0x420A 208C + (0x200 * k) | 0x421A 208C + (0x200 * k) |
EDMA_TPCC_QSER_RN_k (3) | R | 32 | 0x0000 2090 + (0x200 * k) | 0x420A 2090 + (0x200 * k) | 0x421A 2090 + (0x200 * k) |
EDMA_TPCC_QSECR_RN_k (3) | W | 32 | 0x0000 2094 + (0x200 * k) | 0x420A 2094 + (0x200 * k) | 0x421A 2094 + (0x200 * k) |
EDMA_TPCC_OPT_n(6) | RW | 32 | 0x0000 4000 + (0x20 * n) | 0x420A 4000 + (0x20 * n) | 0x421A 4000 + (0x20 * n) |
EDMA_TPCC_SRC_n (6) | RW | 32 | 0x0000 4004 + (0x20 * n) | 0x420A 4004 + (0x20 * n) | 0x421A 4004 + (0x20 * n) |
EDMA_TPCC_ABCNT_n (6) | RW | 32 | 0x0000 4008 + (0x20 * n) | 0x420A 4008 + (0x20 * n) | 0x421A 4008 + (0x20 * n) |
EDMA_TPCC_DST_n (6) | RW | 32 | 0x0000 400C + (0x20 * n) | 0x420A 400C + (0x20 * n) | 0x421A 400C + (0x20 * n) |
EDMA_TPCC_BIDX_n (6) | RW | 32 | 0x0000 4010 + (0x20 * n) | 0x420A 4010 + (0x20 * n) | 0x421A 4010 + (0x20 * n) |
EDMA_TPCC_LNK_n (6) | RW | 32 | 0x0000 4014 + (0x20 * n) | 0x420A 4014 + (0x20 * n) | 0x421A 4014 + (0x20 * n) |
EDMA_TPCC_CIDX_n (6) | RW | 32 | 0x0000 4018 + (0x20 * n) | 0x420A 4018 + (0x20 * n) | 0x421A 4018 + (0x20 * n) |
EDMA_TPCC_CCNT_n (6) | RW | 32 | 0x0000 401C + (0x20 * n) | 0x420A 401C + (0x20 * n) | 0x421A 401C + (0x20 * n) |
The value for "n" is from 0 to 1 in the Table 18-85. It corresponds of the Transfer Controller (EDMA_TPTC0 and EDMA_TPTC1) instances in the device.
Register Name | Type | Register Width (Bits) | Address Offset | SYS_EDMA_TPTC0 Physical Address (L3_MAIN Access) | SYS_EDMA_TPTC1 Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | 0x4340 0000 | 0x4350 0000 |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | 0x4340 0004 | 0x4350 0004 |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x4340 0100 | 0x4350 0100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x4340 0104 | 0x4350 0104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x4340 0108 | 0x4350 0108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x4340 010C | 0x4350 010C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x4340 0110 | 0x4350 0110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x4340 0120 | 0x4350 0120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x4340 0124 | 0x4350 0124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x4340 0128 | 0x4350 0128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x4340 012C | 0x4350 012C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x4340 0130 | 0x4350 0130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x4340 0140 | 0x4350 0140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x4340 0200 | 0x4350 0200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x4340 0204 | 0x4350 0204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x4340 0208 | 0x4350 0208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x4340 020C | 0x4350 020C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x4340 0210 | 0x4350 0210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x4340 0214 | 0x4350 0214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x4340 0240 | 0x4350 0240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x4340 0244 | 0x4350 0244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x4340 0248 | 0x4350 0248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | 0x4340 024C | 0x4350 024C |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x4340 0250 | 0x4350 0250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x4340 0254 | 0x4350 0254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x4340 0258 | 0x4350 0258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x4340 025C | 0x4350 025C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x4340 0260 | 0x4350 0260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x4340 0280 | 0x4350 0280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x4340 0284 | 0x4350 0284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | 0x4340 0288 | 0x4350 0288 |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x4340 0300 + (0x40 * i) | 0x4350 0300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x4340 0304 + (0x40 * i) | 0x4350 0304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x4340 0308 + (0x40 * i) | 0x4350 0308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x4340 030C + (0x40 * i) | 0x4350 030C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x4340 0310 + (0x40 * i) | 0x4350 0310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x4340 0314 + (0x40 * i) | 0x4350 0314 + (0x40 * i) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP1_EDMA_TPTC0 Physical Address (L3_MAIN Access) | DSP1_EDMA_TPTC1 Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | 0x40D0 5000 | 0x40D0 6000 |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | 0x40D0 5004 | 0x40D0 6004 |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x40D0 5100 | 0x40D0 6100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x40D0 5104 | 0x40D0 6104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x40D0 5108 | 0x40D0 6108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x40D0 510C | 0x40D0 610C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x40D0 5110 | 0x40D0 6110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x40D0 5120 | 0x40D0 6120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x40D0 5124 | 0x40D0 6124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x40D0 5128 | 0x40D0 6128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x40D0 512C | 0x40D0 612C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x40D0 5130 | 0x40D0 6130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x40D0 5140 | 0x40D0 6140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x40D0 5200 | 0x40D0 6200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x40D0 5204 | 0x40D0 6204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x40D0 5208 | 0x40D0 6208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x40D0 520C | 0x40D0 620C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x40D0 5210 | 0x40D0 6210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x40D0 5214 | 0x40D0 6214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x40D0 5240 | 0x40D0 6240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x40D0 5244 | 0x40D0 6244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x40D0 5248 | 0x40D0 6248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | 0x40D0 524C | 0x40D0 624C |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x40D0 5250 | 0x40D0 6250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x40D0 5254 | 0x40D0 6254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x40D0 5258 | 0x40D0 6258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x40D0 525C | 0x40D0 625C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x40D0 5260 | 0x40D0 6260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x40D0 5280 | 0x40D0 6280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x40D0 5284 | 0x40D0 6284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | 0x40D0 5288 | 0x40D0 6288 |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x40D0 5300 + (0x40 * i) | 0x40D0 6300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x40D0 5304 + (0x40 * i) | 0x40D0 6304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x40D0 5308 + (0x40 * i) | 0x40D0 6308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x40D0 530C + (0x40 * i) | 0x40D0 630C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x40D0 5310 + (0x40 * i) | 0x40D0 6310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x40D0 5314 + (0x40 * i) | 0x40D0 6314 + (0x40 * i) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP2_EDMA_TPTC0 Physical Address (L3_MAIN Access) | DSP2_EDMA_TPTC1 Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | 0x4150 5000 | 0x4150 6000 |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | 0x4150 5004 | 0x4150 6004 |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x4150 5100 | 0x4150 6100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x4150 5104 | 0x4150 6104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x4150 5108 | 0x4150 6108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x4150 510C | 0x4150 610C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x4150 5110 | 0x4150 6110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x4150 5120 | 0x4150 6120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x4150 5124 | 0x4150 6124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x4150 5128 | 0x4150 6128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x4150 512C | 0x4150 612C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x4150 5130 | 0x4150 6130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x4150 5140 | 0x4150 6140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x4150 5200 | 0x4150 6200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x4150 5204 | 0x4150 6204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x4150 5208 | 0x4150 6208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x4150 520C | 0x4150 620C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x4150 5210 | 0x4150 6210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x4150 5214 | 0x4150 6214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x4150 5240 | 0x4150 6240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x4150 5244 | 0x4150 6244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x4150 5248 | 0x4150 6248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | 0x4150 524C | 0x4150 624C |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x4150 5250 | 0x4150 6250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x4150 5254 | 0x4150 6254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x4150 5258 | 0x4150 6258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x4150 525C | 0x4150 625C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x4150 5260 | 0x4150 6260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x4150 5280 | 0x4150 6280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x4150 5284 | 0x4150 6284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | 0x4150 5288 | 0x4150 6288 |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x4150 5300 + (0x40 * i) | 0x4150 6300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x4150 5304 + (0x40 * i) | 0x4150 6304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x4150 5308 + (0x40 * i) | 0x4150 6308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x4150 530C + (0x40 * i) | 0x4150 630C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x4150 5310 + (0x40 * i) | 0x4150 6310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x4150 5314 + (0x40 * i) | 0x4150 6314 + (0x40 * i) |
Register Name | Type | Register Width (Bits) | Address Offset | DSP_EDMA_TPTC0 Physical Address (DSP Private Access) | DSP_EDMA_TPTC1 Physical Address (DSP Private Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | 0x01D0 5000 | 0x01D0 6000 |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | 0x01D0 5004 | 0x01D0 6004 |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x01D0 5100 | 0x01D0 6100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x01D0 5104 | 0x01D0 6104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x01D0 5108 | 0x01D0 6108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x01D0 510C | 0x01D0 610C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x01D0 5110 | 0x01D0 6110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x01D0 5120 | 0x01D0 6120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x01D0 5124 | 0x01D0 6124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x01D0 5128 | 0x01D0 6128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x01D0 512C | 0x01D0 612C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x01D0 5130 | 0x01D0 6130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x01D0 5140 | 0x01D0 6140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x01D0 5200 | 0x01D0 6200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x01D0 5204 | 0x01D0 6204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x01D0 5208 | 0x01D0 6208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x01D0 520C | 0x01D0 620C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x01D0 5210 | 0x01D0 6210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x01D0 5214 | 0x01D0 6214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x01D0 5240 | 0x01D0 6240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x01D0 5244 | 0x01D0 6244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x01D0 5248 | 0x01D0 6248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | 0x01D0 524C | 0x01D0 624C |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x01D0 5250 | 0x01D0 6250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x01D0 5254 | 0x01D0 6254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x01D0 5258 | 0x01D0 6258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x01D0 525C | 0x01D0 625C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x01D0 5260 | 0x01D0 6260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x01D0 5280 | 0x01D0 6280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x01D0 5284 | 0x01D0 6284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | 0x01D0 5288 | 0x01D0 6288 |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x01D0 5300 + (0x40 * i) | 0x01D0 6300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x01D0 5304 + (0x40 * i) | 0x01D0 6304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x01D0 5308 + (0x40 * i) | 0x01D0 6308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x01D0 530C + (0x40 * i) | 0x01D0 630C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x01D0 5310 + (0x40 * i) | 0x01D0 6310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x01D0 5314 + (0x40 * i) | 0x01D0 6314 + (0x40 * i) |
Register Name | Type | Register Width (Bits) | Address Offset | EVE1_EDMA_TPTC0 Physical Address (L3_MAIN Access) | EVE2_EDMA_TPTC0 Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | - | - |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | - | - |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x4208 6100 | 0x4218 6100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x4208 6104 | 0x4218 6104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x4208 6108 | 0x4218 6108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x4208 610C | 0x4218 610C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x4208 6110 | 0x4218 6110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x4208 6120 | 0x4218 6120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x4208 6124 | 0x4218 6124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x4208 6128 | 0x4218 6128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x4208 612C | 0x4218 612C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x4208 6130 | 0x4218 6130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x4208 6140 | 0x4218 6140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x4208 6200 | 0x4218 6200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x4208 6204 | 0x4218 6204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x4208 6208 | 0x4218 6208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x4208 620C | 0x4218 620C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x4208 6210 | 0x4218 6210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x4208 6214 | 0x4218 6214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x4208 6240 | 0x4218 6240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x4208 6244 | 0x4218 6244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x4208 6248 | 0x4218 6248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | - | - |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x4208 6250 | 0x4218 6250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x4208 6254 | 0x4218 6254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x4208 6258 | 0x4218 6258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x4208 625C | 0x4218 625C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x4208 6260 | 0x4218 6260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x4208 6280 | 0x4218 6280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x4208 6284 | 0x4218 6284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | - | - |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x4208 6300 + (0x40 * i) | 0x4218 6300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x4208 6304 + (0x40 * i) | 0x4218 6304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x4208 6308 + (0x40 * i) | 0x4218 6308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x4208 630C + (0x40 * i) | 0x4218 630C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x4208 6310 + (0x40 * i) | 0x4218 6310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x4208 6314 + (0x40 * i) | 0x4218 6314 + (0x40 * i) |
Register Name | Type | Register Width (Bits) | Address Offset | EVE1_EDMA_TPTC1 Physical Address (L3_MAIN Access) | EVE2_EDMA_TPTC1 Physical Address (L3_MAIN Access) |
---|---|---|---|---|---|
EDMA_TPTCn_PID | R | 32 | 0x0000 0000 | - | - |
EDMA_TPTCn_TCCFG | R | 32 | 0x0000 0004 | - | - |
EDMA_TPTCn_TCSTAT | R | 32 | 0x0000 0100 | 0x4208 7100 | 0x4218 7100 |
EDMA_TPTCn_INTSTAT | R | 32 | 0x0000 0104 | 0x4208 7104 | 0x4218 7104 |
EDMA_TPTCn_INTEN | RW | 32 | 0x0000 0108 | 0x4208 7108 | 0x4218 7108 |
EDMA_TPTCn_INTCLR | W | 32 | 0x0000 010C | 0x4208 710C | 0x4218 710C |
EDMA_TPTCn_INTCMD | W | 32 | 0x0000 0110 | 0x4208 7110 | 0x4218 7110 |
EDMA_TPTCn_ERRSTAT | R | 32 | 0x0000 0120 | 0x4208 7120 | 0x4218 7120 |
EDMA_TPTCn_ERREN | RW | 32 | 0x0000 0124 | 0x4208 7124 | 0x4218 7124 |
EDMA_TPTCn_ERRCLR | W | 32 | 0x0000 0128 | 0x4208 7128 | 0x4218 7128 |
EDMA_TPTCn_ERRDET | R | 32 | 0x0000 012C | 0x4208 712C | 0x4218 712C |
EDMA_TPTCn_ERRCMD | W | 32 | 0x0000 0130 | 0x4208 7130 | 0x4218 7130 |
EDMA_TPTCn_RDRATE | RW | 32 | 0x0000 0140 | 0x4208 7140 | 0x4218 7140 |
EDMA_TPTCn_POPT | RW | 32 | 0x0000 0200 | 0x4208 7200 | 0x4218 7200 |
EDMA_TPTCn_PSRC | RW | 32 | 0x0000 0204 | 0x4208 7204 | 0x4218 7204 |
EDMA_TPTCn_PCNT | RW | 32 | 0x0000 0208 | 0x4208 7208 | 0x4218 7208 |
EDMA_TPTCn_PDST | RW | 32 | 0x0000 020C | 0x4208 720C | 0x4218 720C |
EDMA_TPTCn_PBIDX | RW | 32 | 0x0000 0210 | 0x4208 7210 | 0x4218 7210 |
EDMA_TPTCn_PMPPRXY | R | 32 | 0x0000 0214 | 0x4208 7214 | 0x4218 7214 |
EDMA_TPTCn_SAOPT | R | 32 | 0x0000 0240 | 0x4208 7240 | 0x4218 7240 |
EDMA_TPTCn_SASRC | R | 32 | 0x0000 0244 | 0x4208 7244 | 0x4218 7244 |
EDMA_TPTCn_SACNT | R | 32 | 0x0000 0248 | 0x4208 7248 | 0x4218 7248 |
EDMA_TPTCn_SADST | R | 32 | 0x0000 024C | - | - |
EDMA_TPTCn_SABIDX | R | 32 | 0x0000 0250 | 0x4208 7250 | 0x4218 7250 |
EDMA_TPTCn_SAMPPRXY | R | 32 | 0x0000 0254 | 0x4208 7254 | 0x4218 7254 |
EDMA_TPTCn_SACNTRLD | R | 32 | 0x0000 0258 | 0x4208 7258 | 0x4218 7258 |
EDMA_TPTCn_SASRCBREF | R | 32 | 0x0000 025C | 0x4208 725C | 0x4218 725C |
EDMA_TPTCn_SADSTBREF | R | 32 | 0x0000 0260 | 0x4208 7260 | 0x4218 7260 |
EDMA_TPTCn_DFCNTRLD | R | 32 | 0x0000 0280 | 0x4208 7280 | 0x4218 7280 |
EDMA_TPTCn_DFSRCBREF | R | 32 | 0x0000 0284 | 0x4208 7284 | 0x4218 7284 |
EDMA_TPTCn_DFDSTBREF | R | 32 | 0x0000 0288 | - | - |
EDMA_TPTCn_DFOPTi(1) | R | 32 | 0x0000 0300 + (0x40 * i) | 0x4208 7300 + (0x40 * i) | 0x4218 7300 + (0x40 * i) |
EDMA_TPTCn_DFSRCi (1) | R | 32 | 0x0000 0304 + (0x40 * i) | 0x4208 7304 + (0x40 * i) | 0x4218 7304 + (0x40 * i) |
EDMA_TPTCn_DFCNTi (1) | R | 32 | 0x0000 0308 + (0x40 * i) | 0x4208 7308 + (0x40 * i) | 0x4218 7308 + (0x40 * i) |
EDMA_TPTCn_DFDSTi (1) | R | 32 | 0x0000 030C + (0x40 * i) | 0x4208 730C + (0x40 * i) | 0x4218 730C + (0x40 * i) |
EDMA_TPTCn_DFBIDXi (1) | R | 32 | 0x0000 0310 + (0x40 * i) | 0x4208 7310 + (0x40 * i) | 0x4218 7310 + (0x40 * i) |
EDMA_TPTCn_DFMPPRXYi (1) | R | 32 | 0x0000 0314 + (0x40 * i) | 0x4208 7314 + (0x40 * i) | 0x4218 7314 + (0x40 * i) |