SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
EVE image buffers are the primary location for the time-slot based data buffers. These buffers are built to facilitate ping-pong ownership and accesses by the EDMA and the VCOP. On a time-slot bases (as controlled by the ARP32 core), each of the respective image buffers can be assigned ownership to either the System (ARP32, EDMA, OCP target bus) or the VCOP.
IBUFLx and IBUFHx (x = A, B) are typically used as output buffers, and as such VCOP can concurrently access up to eight banks of memory in the VCOP-owned IBUFLA and IBUFLB banks and up to eight banks of memory in one of the VCOP owned IBUFHA and IBUFHB (see Figure 8-6). ARP32 accesses 32-bits per cycle in one of the system-owned IBUF banks.
EDMA (and other EVE system components) access up to 128 bits per cycle of contiguous banks of memory (in case there are no independent bank accesses) within a 128-bit window (a single access does not cross 128-bit boundary) for each system-owned corresponding IBUF bank. For example, if all banks are system owned, EDMA TC0 (or any other EVE system resource) accesses IBUFL at 128-bits per cycle in parallel with EDMA TC1 accessing IBUFH at 128-bits per cycle, giving a total throughput of 256-bits per cycle.
EDMA versus system versus ARP32 accesses are arbitrated dynamically on OCP burst boundaries. The arbitration is done with round-robin policy inside the EVE high-performance interconnect.
The ownership of each IBUF is pseudostatically controlled by the EVE_MSW_CTL [12]IBUFHB, EVE_MSW_CTL [8]IBUFLB, EVE_MSW_CTL [4]IBUFHA, EVE_MSW_CTL [0]IBUFLA bits. Ownership is also internally changed by ARP32 custom instruction or through writes to the memory-mapped address.
By setting EVE_MSW_CTL [12/8/4/0]IBUF = 0x1 the ownership of the IBUF memory is granted to VCOP, otherwise (EVE_MSW_CTL:IBUF = 0x0) the memory is owned by the EVE system resources. If IBUF is system owned, then the SM provides a connection from the EVE high-performance interconnect (for EDMA, ARP32, or external-to-EVE initiated access) to the corresponding IBUF memory, and VCOP accesses are not allowed. If IBUF is VCOP owned, the static mux provides a connection from VCOP to the IBUF memory, and system accesses are not allowed.
Ownership of each of the four IBUF regions (IBUFLA, IBUFLB, IBUFHA, and IBUFHB) is independently programmable with no restrictions. Aliased versus nonaliased mode is controlled by setting the EVE_MEMMAP register. In nonaliased mode it is possible for the VCOP core to own all four IBUFs, or for the system resources to own all four IBUFs or any combination. In aliased mode VCOP owns only one of the IBUFHx regions and one of the IBUFLx regions (x = A, B) because both A and B copies of the IBUFs are mapped to the same address.
In case VCOP or system initiators access the WBUF address location while IBUF is not owned, an error is captured in EVE memory switch error register (EVE_MSW_ERR) and EVE memory switch error address register (EVE_MSW_ERRADDR) and the corresponding flag in the EVE_MSW_ERR_IRQSTATUS_RAW register is set. Debug accesses do not cause the error registers or interrupt to be set, but result in OCP ERR response.
Figure 8-7 shows the typical ownership patterns that offer different amounts of memory/bandwidth to VCOP (V) versus system (S) accesses.