SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Register Name | Type | Register Width (Bits) | Address Offset | L3_MAIN Physical Address |
---|---|---|---|---|
DISPC_REVISION | R | 32 | 0x0000 0000 | 0x5800 1000 |
DISPC_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x5800 1010 |
DISPC_SYSSTATUS | R | 32 | 0x0000 0014 | 0x5800 1014 |
DISPC_IRQSTATUS | RW | 32 | 0x0000 0018 | 0x5800 1018 |
DISPC_IRQENABLE | RW | 32 | 0x0000 001C | 0x5800 101C |
DISPC_CONTROL1 | RW | 32 | 0x0000 0040 | 0x5800 1040 |
DISPC_CONFIG1 | RW | 32 | 0x0000 0044 | 0x5800 1044 |
RESERVED | R | 32 | 0x0000 0048 | 0x5800 1048 |
DISPC_DEFAULT_COLOR0 | RW | 32 | 0x0000 004C | 0x5800 104C |
DISPC_DEFAULT_COLOR1 | RW | 32 | 0x0000 0050 | 0x5800 1050 |
DISPC_TRANS_COLOR0 | RW | 32 | 0x0000 0054 | 0x5800 1054 |
DISPC_TRANS_COLOR1 | RW | 32 | 0x0000 0058 | 0x5800 1058 |
DISPC_LINE_STATUS | R | 32 | 0x0000 005C | 0x5800 105C |
DISPC_LINE_NUMBER | RW | 32 | 0x0000 0060 | 0x5800 1060 |
DISPC_TIMING_H1 | RW | 32 | 0x0000 0064 | 0x5800 1064 |
DISPC_TIMING_V1 | RW | 32 | 0x0000 0068 | 0x5800 1068 |
DISPC_POL_FREQ1 | RW | 32 | 0x0000 006C | 0x5800 106C |
DISPC_DIVISOR1 | RW | 32 | 0x0000 0070 | 0x5800 1070 |
DISPC_GLOBAL_ALPHA | RW | 32 | 0x0000 0074 | 0x5800 1074 |
DISPC_SIZE_TV | RW | 32 | 0x0000 0078 | 0x5800 1078 |
DISPC_SIZE_LCD1 | RW | 32 | 0x0000 007C | 0x5800 107C |
DISPC_GFX_BA_j (1) | RW | 32 | 0x0000 0080 + (0x4 * j) | 0x5800 1080 + (0x4 * j) |
DISPC_GFX_POSITION | RW | 32 | 0x0000 0088 | 0x5800 1088 |
DISPC_GFX_SIZE | RW | 32 | 0x0000 008C | 0x5800 108C |
DISPC_GFX_ATTRIBUTES | RW | 32 | 0x0000 00A0 | 0x5800 10A0 |
DISPC_GFX_BUF_THRESHOLD | RW | 32 | 0x0000 00A4 | 0x5800 10A4 |
DISPC_GFX_BUF_SIZE_STATUS | R | 32 | 0x0000 00A8 | 0x5800 10A8 |
DISPC_GFX_ROW_INC | RW | 32 | 0x0000 00AC | 0x5800 10AC |
DISPC_GFX_PIXEL_INC | RW | 32 | 0x0000 00B0 | 0x5800 10B0 |
RESERVED | R | 32 | 0x0000 00B4 | 0x5800 10B4 |
DISPC_GFX_TABLE_BA | RW | 32 | 0x0000 00B8 | 0x5800 10B8 |
DISPC_VID1_BA_j (1) | RW | 32 | 0x0000 00BC + (0x4 * j) | 0x5800 10BC + (0x4 * j) |
DISPC_VID1_POSITION | RW | 32 | 0x0000 00C4 | 0x5800 10C4 |
DISPC_VID1_SIZE | RW | 32 | 0x0000 00C8 | 0x5800 10C8 |
DISPC_VID1_ATTRIBUTES | RW | 32 | 0x0000 00CC | 0x5800 10CC |
DISPC_VID1_BUF_THRESHOLD | RW | 32 | 0x0000 00D0 | 0x5800 10D0 |
DISPC_VID1_BUF_SIZE_STATUS | R | 32 | 0x0000 00D4 | 0x5800 10D4 |
DISPC_VID1_ROW_INC | RW | 32 | 0x0000 00D8 | 0x5800 10D8 |
DISPC_VID1_PIXEL_INC | RW | 32 | 0x0000 00DC | 0x5800 10DC |
DISPC_VID1_FIR | RW | 32 | 0x0000 00E0 | 0x5800 10E0 |
DISPC_VID1_PICTURE_SIZE | RW | 32 | 0x0000 00E4 | 0x5800 10E4 |
DISPC_VID1_ACCU_j (1) | RW | 32 | 0x0000 00E8 + (0x4 * j) | 0x5800 10E8 + (0x4 * j) |
DISPC_VID1_FIR_COEF_H_i (2) | RW | 32 | 0x0000 00F0 + (0x8 * i) | 0x5800 10F0 + (0x8 * i) |
DISPC_VID1_FIR_COEF_HV_i (2) | RW | 32 | 0x0000 00F4 + (0x8 * i) | 0x5800 10F4 + (0x8 * i) |
DISPC_VID1_CONV_COEF0 | RW | 32 | 0x0000 0130 | 0x5800 1130 |
DISPC_VID1_CONV_COEF1 | RW | 32 | 0x0000 0134 | 0x5800 1134 |
DISPC_VID1_CONV_COEF2 | RW | 32 | 0x0000 0138 | 0x5800 1138 |
DISPC_VID1_CONV_COEF3 | RW | 32 | 0x0000 013C | 0x5800 113C |
DISPC_VID1_CONV_COEF4 | RW | 32 | 0x0000 0140 | 0x5800 1140 |
DISPC_VID2_BA_j (1) | RW | 32 | 0x0000 014C + (0x4 * j) | 0x5800 114C + (0x4 * j) |
DISPC_VID2_POSITION | RW | 32 | 0x0000 0154 | 0x5800 1154 |
DISPC_VID2_SIZE | RW | 32 | 0x0000 0158 | 0x5800 1158 |
DISPC_VID2_ATTRIBUTES | RW | 32 | 0x0000 015C | 0x5800 115C |
DISPC_VID2_BUF_THRESHOLD | RW | 32 | 0x0000 0160 | 0x5800 1160 |
DISPC_VID2_BUF_SIZE_STATUS | R | 32 | 0x0000 0164 | 0x5800 1164 |
DISPC_VID2_ROW_INC | RW | 32 | 0x0000 0168 | 0x5800 1168 |
DISPC_VID2_PIXEL_INC | RW | 32 | 0x0000 016C | 0x5800 116C |
DISPC_VID2_FIR | RW | 32 | 0x0000 0170 | 0x5800 1170 |
DISPC_VID2_PICTURE_SIZE | RW | 32 | 0x0000 0174 | 0x5800 1174 |
DISPC_VID2_ACCU_j (1) | RW | 32 | 0x0000 0178 + (0x4 * j) | 0x5800 1178 + (0x4 * j) |
DISPC_VID2_FIR_COEF_H_i (2) | RW | 32 | 0x0000 0180 + (0x8 * i) | 0x5800 1180 + (0x8 * i) |
DISPC_VID2_FIR_COEF_HV_i (2) | RW | 32 | 0x0000 0184 + (0x8 * i) | 0x5800 1184 + (0x8 * i) |
DISPC_VID2_CONV_COEF0 | RW | 32 | 0x0000 01C0 | 0x5800 11C0 |
DISPC_VID2_CONV_COEF1 | RW | 32 | 0x0000 01C4 | 0x5800 11C4 |
DISPC_VID2_CONV_COEF2 | RW | 32 | 0x0000 01C8 | 0x5800 11C8 |
DISPC_VID2_CONV_COEF3 | RW | 32 | 0x0000 01CC | 0x5800 11CC |
DISPC_VID2_CONV_COEF4 | RW | 32 | 0x0000 01D0 | 0x5800 11D0 |
DISPC_DATA1_CYCLE1 | RW | 32 | 0x0000 01D4 | 0x5800 11D4 |
DISPC_DATA1_CYCLE2 | RW | 32 | 0x0000 01D8 | 0x5800 11D8 |
DISPC_DATA1_CYCLE3 | RW | 32 | 0x0000 01DC | 0x5800 11DC |
DISPC_VID1_FIR_COEF_V_i (2) | RW | 32 | 0x0000 01E0 + (0x4 * i) | 0x5800 11E0 + (0x4 * i) |
DISPC_VID2_FIR_COEF_V_i (2) | RW | 32 | 0x0000 0200 + (0x4 * i) | 0x5800 1200 + (0x4 * i) |
DISPC_CPR1_COEF_R | RW | 32 | 0x0000 0220 | 0x5800 1220 |
DISPC_CPR1_COEF_G | RW | 32 | 0x0000 0224 | 0x5800 1224 |
DISPC_CPR1_COEF_B | RW | 32 | 0x0000 0228 | 0x5800 1228 |
DISPC_GFX_PRELOAD | RW | 32 | 0x0000 022C | 0x5800 122C |
DISPC_VID1_PRELOAD | RW | 32 | 0x0000 0230 | 0x5800 1230 |
DISPC_VID2_PRELOAD | RW | 32 | 0x0000 0234 | 0x5800 1234 |
DISPC_CONTROL2 | RW | 32 | 0x0000 0238 | 0x5800 1238 |
DISPC_GFX_POSITION2 | RW | 32 | 0x0000 0240 | 0x5800 1240 |
DISPC_VID1_POSITION2 | RW | 32 | 0x0000 0244 | 0x5800 1244 |
DISPC_VID2_POSITION2 | RW | 32 | 0x0000 0248 | 0x5800 1248 |
DISPC_VID3_POSITION2 | RW | 32 | 0x0000 024C | 0x5800 124C |
DISPC_VID3_ACCU_j (1) | RW | 32 | 0x0000 0300 + (0x4 * j) | 0x5800 1300 + (0x4 * j) |
DISPC_VID3_BA_j (1) | RW | 32 | 0x0000 0308 + (0x4 * j) | 0x5800 1308 + (0x4 * j) |
DISPC_VID3_FIR_COEF_H_i (2) | RW | 32 | 0x0000 0310 + (0x8 * i) | 0x5800 1310 + (0x8 * i) |
DISPC_VID3_FIR_COEF_HV_i (2) | RW | 32 | 0x0000 0314 + (0x8 * i) | 0x5800 1314 + (0x8 * i) |
DISPC_VID3_FIR_COEF_V_i (2) | RW | 32 | 0x0000 0350 + (0x4 * i) | 0x5800 1350 + (0x4 * i) |
DISPC_VID3_ATTRIBUTES | RW | 32 | 0x0000 0370 | 0x5800 1370 |
DISPC_VID3_CONV_COEF0 | RW | 32 | 0x0000 0374 | 0x5800 1374 |
DISPC_VID3_CONV_COEF1 | RW | 32 | 0x0000 0378 | 0x5800 1378 |
DISPC_VID3_CONV_COEF2 | RW | 32 | 0x0000 037C | 0x5800 137C |
DISPC_VID3_CONV_COEF3 | RW | 32 | 0x0000 0380 | 0x5800 1380 |
DISPC_VID3_CONV_COEF4 | RW | 32 | 0x0000 0384 | 0x5800 1384 |
DISPC_VID3_BUF_SIZE_STATUS | R | 32 | 0x0000 0388 | 0x5800 1388 |
DISPC_VID3_BUF_THRESHOLD | RW | 32 | 0x0000 038C | 0x5800 138C |
DISPC_VID3_FIR | RW | 32 | 0x0000 0390 | 0x5800 1390 |
DISPC_VID3_PICTURE_SIZE | RW | 32 | 0x0000 0394 | 0x5800 1394 |
DISPC_VID3_PIXEL_INC | RW | 32 | 0x0000 0398 | 0x5800 1398 |
DISPC_VID3_POSITION | RW | 32 | 0x0000 039C | 0x5800 139C |
DISPC_VID3_PRELOAD | RW | 32 | 0x0000 03A0 | 0x5800 13A0 |
DISPC_VID3_ROW_INC | RW | 32 | 0x0000 03A4 | 0x5800 13A4 |
DISPC_VID3_SIZE | RW | 32 | 0x0000 03A8 | 0x5800 13A8 |
DISPC_DEFAULT_COLOR2 | RW | 32 | 0x0000 03AC | 0x5800 13AC |
DISPC_TRANS_COLOR2 | RW | 32 | 0x0000 03B0 | 0x5800 13B0 |
DISPC_CPR2_COEF_B | RW | 32 | 0x0000 03B4 | 0x5800 13B4 |
DISPC_CPR2_COEF_G | RW | 32 | 0x0000 03B8 | 0x5800 13B8 |
DISPC_CPR2_COEF_R | RW | 32 | 0x0000 03BC | 0x5800 13BC |
DISPC_DATA2_CYCLE1 | RW | 32 | 0x0000 03C0 | 0x5800 13C0 |
DISPC_DATA2_CYCLE2 | RW | 32 | 0x0000 03C4 | 0x5800 13C4 |
DISPC_DATA2_CYCLE3 | RW | 32 | 0x0000 03C8 | 0x5800 13C8 |
DISPC_SIZE_LCD2 | RW | 32 | 0x0000 03CC | 0x5800 13CC |
DISPC_TIMING_H2 | RW | 32 | 0x0000 0400 | 0x5800 1400 |
DISPC_TIMING_V2 | RW | 32 | 0x0000 0404 | 0x5800 1404 |
DISPC_POL_FREQ2 | RW | 32 | 0x0000 0408 | 0x5800 1408 |
DISPC_DIVISOR2 | RW | 32 | 0x0000 040C | 0x5800 140C |
DISPC_WB_ACCU_j (1) | RW | 32 | 0x0000 0500 + (0x4 * j) | 0x5800 1500 + (0x4 * j) |
DISPC_WB_BA_j (1) | RW | 32 | 0x0000 0508 + (0x4 * j) | 0x5800 1508 + (0x4 * j) |
DISPC_WB_FIR_COEF_H_i (2) | RW | 32 | 0x0000 0510 + (0x8 * i) | 0x5800 1510 + (0x8 * i) |
DISPC_WB_FIR_COEF_HV_i (2) | RW | 32 | 0x0000 0514 + (0x8 * i) | 0x5800 1514 + (0x8 * i) |
DISPC_WB_FIR_COEF_V_i (2) | RW | 32 | 0x0000 0550 + (0x4 * i) | 0x5800 1550 + (0x4 * i) |
DISPC_WB_ATTRIBUTES | RW | 32 | 0x0000 0570 | 0x5800 1570 |
DISPC_WB_CONV_COEF0 | RW | 32 | 0x0000 0574 | 0x5800 1574 |
DISPC_WB_CONV_COEF1 | RW | 32 | 0x0000 0578 | 0x5800 1578 |
DISPC_WB_CONV_COEF2 | RW | 32 | 0x0000 057C | 0x5800 157C |
DISPC_WB_CONV_COEF3 | RW | 32 | 0x0000 0580 | 0x5800 1580 |
DISPC_WB_CONV_COEF4 | RW | 32 | 0x0000 0584 | 0x5800 1584 |
DISPC_WB_BUF_SIZE_STATUS | R | 32 | 0x0000 0588 | 0x5800 1588 |
DISPC_WB_BUF_THRESHOLD | RW | 32 | 0x0000 058C | 0x5800 158C |
DISPC_WB_FIR | RW | 32 | 0x0000 0590 | 0x5800 1590 |
DISPC_WB_PICTURE_SIZE | RW | 32 | 0x0000 0594 | 0x5800 1594 |
DISPC_WB_PIXEL_INC | RW | 32 | 0x0000 0598 | 0x5800 1598 |
DISPC_WB_ROW_INC | RW | 32 | 0x0000 05A4 | 0x5800 15A4 |
DISPC_WB_SIZE | RW | 32 | 0x0000 05A8 | 0x5800 15A8 |
DISPC_VID1_BA_UV_j (1) | RW | 32 | 0x0000 0600 + (0x4 * j) | 0x5800 1600 + (0x4 * j) |
DISPC_VID2_BA_UV_j (1) | RW | 32 | 0x0000 0608 + (0x4 * j) | 0x5800 1608 + (0x4 * j) |
DISPC_VID3_BA_UV_j (1) | RW | 32 | 0x0000 0610 + (0x4 * j) | 0x5800 1610 + (0x4 * j) |
DISPC_WB_BA_UV_j (1) | RW | 32 | 0x0000 0618 + (0x4 * j) | 0x5800 1618 + (0x4 * j) |
DISPC_CONFIG2 | RW | 32 | 0x0000 0620 | 0x5800 1620 |
DISPC_VID1_ATTRIBUTES2 | RW | 32 | 0x0000 0624 | 0x5800 1624 |
DISPC_VID2_ATTRIBUTES2 | RW | 32 | 0x0000 0628 | 0x5800 1628 |
DISPC_VID3_ATTRIBUTES2 | RW | 32 | 0x0000 062C | 0x5800 162C |
DISPC_GAMMA_TABLE0 | W | 32 | 0x0000 0630 | 0x5800 1630 |
DISPC_GAMMA_TABLE1 | W | 32 | 0x0000 0634 | 0x5800 1634 |
DISPC_GAMMA_TABLE2 | W | 32 | 0x0000 0638 | 0x5800 1638 |
DISPC_VID1_FIR2 | RW | 32 | 0x0000 063C | 0x5800 163C |
DISPC_VID1_ACCU2_j (1) | RW | 32 | 0x0000 0640 + (0x4 * j) | 0x5800 1640 + (0x4 * j) |
DISPC_VID1_FIR_COEF_H2_i (2) | RW | 32 | 0x0000 0648 + (0x8 * i) | 0x5800 1648 + (0x8 * i) |
DISPC_VID1_FIR_COEF_HV2_i (2) | RW | 32 | 0x0000 064C + (0x8 * i) | 0x5800 164C + (0x8 * i) |
DISPC_VID1_FIR_COEF_V2_i (2) | RW | 32 | 0x0000 0688 + (0x4 * i) | 0x5800 1688 + (0x4 * i) |
DISPC_VID2_FIR2 | RW | 32 | 0x0000 06A8 | 0x5800 16A8 |
DISPC_VID2_ACCU2_j (1) | RW | 32 | 0x0000 06AC + (0x4 * j) | 0x5800 16AC + (0x4 * j) |
DISPC_VID2_FIR_COEF_H2_i (2) | RW | 32 | 0x0000 06B4 + (0x8 * i) | 0x5800 16B4 + (0x8 * i) |
DISPC_VID2_FIR_COEF_HV2_i (2) | RW | 32 | 0x0000 06B8 + (0x8 * i) | 0x5800 16B8 + (0x8 * i) |
DISPC_VID2_FIR_COEF_V2_i (2) | RW | 32 | 0x0000 06F4 + (0x4 * i) | 0x5800 16F4 + (0x4 * i) |
DISPC_VID3_FIR2 | RW | 32 | 0x0000 0724 | 0x5800 1724 |
DISPC_VID3_ACCU2_j (1) | RW | 32 | 0x0000 0728 + (0x4 * j) | 0x5800 1728 + (0x4 * j) |
DISPC_VID3_FIR_COEF_H2_i (2) | RW | 32 | 0x0000 0730 + (0x8 * i) | 0x5800 1730 + (0x8 * i) |
DISPC_VID3_FIR_COEF_HV2_i (2) | RW | 32 | 0x0000 0734 + (0x8 * i) | 0x5800 1734 + (0x8 * i) |
DISPC_VID3_FIR_COEF_V2_i (2) | RW | 32 | 0x0000 0770 + (0x4 * i) | 0x5800 1770 + (0x4 * i) |
DISPC_WB_FIR2 | RW | 32 | 0x0000 0790 | 0x5800 1790 |
DISPC_WB_ACCU2_j (1) | RW | 32 | 0x0000 0794 + (0x4 * j) | 0x5800 1794 + (0x4 * j) |
DISPC_WB_FIR_COEF_H2_i (2) | RW | 32 | 0x0000 07A0 + (0x8 * i) | 0x5800 17A0 + (0x8 * i) |
DISPC_WB_FIR_COEF_HV2_i (2) | RW | 32 | 0x0000 07A4 + (0x8 * i) | 0x5800 17A4 + (0x8 * i) |
DISPC_WB_FIR_COEF_V2_i (2) | RW | 32 | 0x0000 07E0 + (0x4 * i) | 0x5800 17E0 + (0x4 * i) |
DISPC_GLOBAL_BUFFER | RW | 32 | 0x0000 0800 | 0x5800 1800 |
DISPC_DIVISOR | RW | 32 | 0x0000 0804 | 0x5800 1804 |
DISPC_WB_ATTRIBUTES2 | RW | 32 | 0x0000 0810 | 0x5800 1810 |
DISPC_DEFAULT_COLOR3 | RW | 32 | 0x0000 0814 | 0x5800 1814 |
DISPC_TRANS_COLOR3 | RW | 32 | 0x0000 0818 | 0x5800 1818 |
DISPC_CPR3_COEF_B | RW | 32 | 0x0000 081C | 0x5800 181C |
DISPC_CPR3_COEF_G | RW | 32 | 0x0000 0820 | 0x5800 1820 |
DISPC_CPR3_COEF_R | RW | 32 | 0x0000 0824 | 0x5800 1824 |
DISPC_DATA3_CYCLE1 | RW | 32 | 0x0000 0828 | 0x5800 1828 |
DISPC_DATA3_CYCLE2 | RW | 32 | 0x0000 082C | 0x5800 182C |
DISPC_DATA3_CYCLE3 | RW | 32 | 0x0000 0830 | 0x5800 1830 |
DISPC_SIZE_LCD3 | RW | 32 | 0x0000 0834 | 0x5800 1834 |
DISPC_DIVISOR3 | RW | 32 | 0x0000 0838 | 0x5800 1838 |
DISPC_POL_FREQ3 | RW | 32 | 0x0000 083C | 0x5800 183C |
DISPC_TIMING_H3 | RW | 32 | 0x0000 0840 | 0x5800 1840 |
DISPC_TIMING_V3 | RW | 32 | 0x0000 0844 | 0x5800 1844 |
DISPC_CONTROL3 | RW | 32 | 0x0000 0848 | 0x5800 1848 |
DISPC_CONFIG3 | RW | 32 | 0x0000 084C | 0x5800 184C |
DISPC_GAMMA_TABLE3 | W | 32 | 0x0000 0850 | 0x5800 1850 |
DISPC_BA0_FLIPIMMEDIATE_EN | RW | 32 | 0x0000 0854 | 0x5800 1854 |
DISABLE_MSTANDBY_ENHANCEMENT | RW | 32 | 0x0000 0858 | 0x5800 1858 |
DISPC_GLOBAL_MFLAG_ATTRIBUTE | RW | 32 | 0x0000 085C | 0x5800 185C |
DISPC_GFX_MFLAG_THRESHOLD | RW | 32 | 0x0000 0860 | 0x5800 1860 |
DISPC_VID1_MFLAG_THRESHOLD | RW | 32 | 0x0000 0864 | 0x5800 1864 |
DISPC_VID2_MFLAG_THRESHOLD | RW | 32 | 0x0000 0868 | 0x5800 1868 |
DISPC_VID3_MFLAG_THRESHOLD | RW | 32 | 0x0000 086C | 0x5800 186C |
DISPC_WB_MFLAG_THRESHOLD | RW | 32 | 0x0000 0870 | 0x5800 1870 |