SPRUIE9D May   2017  – May 2024 DRA74P , DRA75P , DRA76P , DRA77P

 

  1.   1
  2.   Read This First
    1.     Support Resources
    2.     About This Manual
    3.     Information About Cautions and Warnings
    4.     Register, Field, and Bit Calls
    5.     Coding Rules
    6.     Flow Chart Rules
    7.     Glossary
    8.     Export Control Notice
    9.     DRA75xP, DRA74xP, DRA77xP, DRA76xP MIPI® Disclaimer
    10.     Trademarks
  3. 1 Introduction
    1. 1.1 DRA75xP, DRA74xP, DRA77xP, DRA76xP Overview
    2. 1.2 DRA75xP, DRA74xP, DRA77xP, DRA76xP Environment
    3. 1.3 DRA75xP, DRA74xP, DRA77xP, DRA76xP Description
      1. 1.3.1  MPU Subsystem
      2. 1.3.2  DSP Subsystems
      3. 1.3.3  EVE Subsystems
      4. 1.3.4  Imaging Subsystem
      5. 1.3.5  Camera Interface Subsystem
      6. 1.3.6  IPU Subsystems
      7. 1.3.7  IVA-HD Subsystem
      8. 1.3.8  Display Subsystem
      9. 1.3.9  Video Processing Subsystem
      10. 1.3.10 Video Capture
      11. 1.3.11 3D GPU Subsystem
      12. 1.3.12 BB2D Subsystem
      13. 1.3.13 On-Chip Debug Support
      14. 1.3.14 Power, Reset, and Clock Management
      15. 1.3.15 On-Chip Memory
      16. 1.3.16 Memory Management
      17. 1.3.17 External Memory Interfaces
      18. 1.3.18 System and Connectivity Peripherals
        1. 1.3.18.1 System Peripherals
        2. 1.3.18.2 Media Connectivity Peripherals
        3. 1.3.18.3 Car Connectivity Peripherals
        4. 1.3.18.4 Audio Connectivity Peripherals
        5. 1.3.18.5 Serial Control Peripherals
        6. 1.3.18.6 Radio Accelerators
    4. 1.4 DRA75xP, DRA74xP, DRA77xP, DRA76xP Family
    5. 1.5 DRA75xP, DRA74xP, DRA77xP, DRA76xP Device Identification
    6. 1.6 DRA75xP, DRA74xP, DRA77xP, DRA76xP Package Characteristics Overview
  4. 2 Memory Mapping
    1. 2.1 Introduction
    2. 2.2 L3_MAIN Memory Map
      1. 2.2.1 L3_INSTR Memory Map
    3. 2.3 L4 Memory Map
      1. 2.3.1 L4_CFG Memory Map
      2. 2.3.2 L4_WKUP Memory Map
    4. 2.4 L4_PER Memory Map
      1. 2.4.1 L4_PER1 Memory Space Mapping
      2. 2.4.2 L4_PER2 Memory Map
      3. 2.4.3 L4_PER3 Memory Map
    5. 2.5 MPU Memory Map
    6. 2.6 IPU Memory Map
    7. 2.7 DSP Memory Map
    8. 2.8 EVE Memory Map
    9. 2.9 TILER View Memory Map
  5. 3 Power, Reset, and Clock Management
    1. 3.1  Device Power Management Introduction
      1. 3.1.1 Device Power-Management Architecture Building Blocks
        1. 3.1.1.1 Clock Management
          1. 3.1.1.1.1 Module Interface and Functional Clocks
          2. 3.1.1.1.2 65
          3. 3.1.1.1.3 Module-Level Clock Management
          4. 3.1.1.1.4 Clock Domain
          5. 3.1.1.1.5 Clock Domain-Level Clock Management
          6. 3.1.1.1.6 Clock Domain HW_AUTO Mode Sequences
          7. 3.1.1.1.7 Clock Domain Sleep/Wake-up
          8. 3.1.1.1.8 Clock Domain Dependency
            1. 3.1.1.1.8.1 Static Dependency
            2. 3.1.1.1.8.2 Dynamic Dependency
            3. 3.1.1.1.8.3 Wake-Up Dependency
        2. 3.1.1.2 Power Management
          1. 3.1.1.2.1 Power Domain
          2. 3.1.1.2.2 Module Logic and Memory Context
          3. 3.1.1.2.3 Power Domain Management
        3. 3.1.1.3 Voltage Management
          1. 3.1.1.3.1 Voltage Domain
          2. 3.1.1.3.2 Voltage Domain Management
          3. 3.1.1.3.3 AVS Overview
            1. 3.1.1.3.3.1 AVS Class 0 (SmartReflex™) Voltage Control
      2. 3.1.2 Power-Management Techniques
        1. 3.1.2.1 Standby Leakage Management
        2. 3.1.2.2 Dynamic Voltage and Frequency Scaling
        3. 3.1.2.3 Dynamic Power Switching
        4. 3.1.2.4 Adaptive Voltage Scaling
        5. 3.1.2.5 Adaptive Body Bias
        6. 3.1.2.6 SR3-APG (Automatic Power Gating)
        7. 3.1.2.7 Combining Power-Management Techniques
          1. 3.1.2.7.1 DPS Versus SLM
    2. 3.2  PRCM Subsystem Overview
      1. 3.2.1 Introduction
      2. 3.2.2 Power-Management Framework Features
    3. 3.3  PRCM Subsystem Environment
      1. 3.3.1 External Clock Signals
      2. 3.3.2 External Boot Signals
      3. 3.3.3 External Reset Signals
      4. 3.3.4 External Voltage Inputs
    4. 3.4  PRCM Subsystem Integration
      1. 3.4.1 Device Power-Management Layout
      2. 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests
        1. 3.4.2.1 Power Domain
        2. 3.4.2.2 Resets
        3. 3.4.2.3 PRCM Interrupt Requests
        4. 3.4.2.4 107
    5. 3.5  Reset Management Functional Description
      1. 3.5.1 Overview
        1. 3.5.1.1 PRCM Reset Management Functional Description
          1. 3.5.1.1.1 Power-On Reset
          2. 3.5.1.1.2 Warm Reset
        2. 3.5.1.2 PRM Reset Management Functional Description
      2. 3.5.2 General Characteristics of Reset Signals
        1. 3.5.2.1 Scope
        2. 3.5.2.2 Occurrence
        3. 3.5.2.3 Source Type
        4. 3.5.2.4 Retention Type
      3. 3.5.3 Reset Sources
        1. 3.5.3.1 Global Reset Sources
        2. 3.5.3.2 Local Reset Sources
      4. 3.5.4 Reset Logging
      5. 3.5.5 Reset Domains
      6. 3.5.6 Reset Sequences
        1. 3.5.6.1  MPU Subsystem Power-On Reset Sequence
        2. 3.5.6.2  MPU Subsystem Warm Reset Sequence
        3. 3.5.6.3  MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
        4. 3.5.6.4  IVA Subsystem Power-On Reset Sequence
        5. 3.5.6.5  IVA Subsystem Software Warm Reset Sequence
        6. 3.5.6.6  DSP1 Subsystem Power-On Reset Sequence
        7. 3.5.6.7  DSP1 Subsystem Software Warm Reset Sequence
        8. 3.5.6.8  DSP2 Subsystem Power-On Reset Sequence
        9. 3.5.6.9  DSP2 Subsystem Software Warm Reset Sequence
        10. 3.5.6.10 IPU1 Subsystem Power-On Reset Sequence
        11. 3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence
        12. 3.5.6.12 IPU2 Subsystem Power-On Reset Sequence
        13. 3.5.6.13 IPU2 Subsystem Software Warm Reset Sequence
        14. 3.5.6.14 EVE1 Subsystem Power-On Reset Sequence
        15. 3.5.6.15 EVE1 Subsystem Software Warm Reset Sequence
        16. 3.5.6.16 EVE2 Subsystem Power-On Reset Sequence
        17. 3.5.6.17 EVE2 Subsystem Software Warm Reset Sequence
        18. 3.5.6.18 Global Warm Reset Sequence
    6. 3.6  Clock Management Functional Description
      1. 3.6.1 Overview
      2. 3.6.2 External Clock Inputs
        1. 3.6.2.1 FUNC_32K_CLK Clock
        2. 3.6.2.2 High-Frequency System Clock Input
        3. 3.6.2.3 External Reference Clock Input
      3. 3.6.3 Internal Clock Sources and Generators
        1. 3.6.3.1  PRM Clock Source
        2. 3.6.3.2  CM Clock Source
          1. 3.6.3.2.1 CM_CORE_AON Clock Generator
          2. 3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview
          3. 3.6.3.2.3 CM_CORE_AON_TIMER Overview
          4. 3.6.3.2.4 CM_CORE_AON_MCASP Overview
        3. 3.6.3.3  Generic DPLL Overview
          1. 3.6.3.3.1 Generic APLL Overview
          2. 3.6.3.3.2 DPLLs Output Clocks Parameters
          3. 3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode
          4. 3.6.3.3.4 DPLL Power Modes
          5. 3.6.3.3.5 DPLL Recalibration
          6. 3.6.3.3.6 DPLL Output Power Down
        4. 3.6.3.4  DPLL_PER Description
          1. 3.6.3.4.1 DPLL_PER Overview
          2. 3.6.3.4.2 DPLL_PER Synthesized Clock Parameters
          3. 3.6.3.4.3 DPLL_PER Power Modes
          4. 3.6.3.4.4 DPLL_PER Recalibration
        5. 3.6.3.5  DPLL_CORE Description
          1. 3.6.3.5.1 DPLL_CORE Overview
          2. 3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters
          3. 3.6.3.5.3 DPLL_CORE Power Modes
          4. 3.6.3.5.4 DPLL_CORE Recalibration
        6. 3.6.3.6  DPLL_ABE Description
          1. 3.6.3.6.1 DPLL_ABE Overview
          2. 3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters
          3. 3.6.3.6.3 DPLL_ABE Power Modes
          4. 3.6.3.6.4 DPLL_ABE Recalibration
          5. 3.6.3.6.5 Fractional M-factor
        7. 3.6.3.7  DPLL_MPU Description
          1. 3.6.3.7.1 DPLL_MPU Overview
          2. 3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment
          3. 3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters
          4. 3.6.3.7.4 DPLL_MPU Power Modes
          5. 3.6.3.7.5 DPLL_MPU Recalibration
        8. 3.6.3.8  DPLL_IVA Description
          1. 3.6.3.8.1 DPLL_IVA Overview
          2. 3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters
          3. 3.6.3.8.3 DPLL_IVA Power Modes
          4. 3.6.3.8.4 DPLL_IVA Recalibration
        9. 3.6.3.9  DPLL_USB Description
          1. 3.6.3.9.1 DPLL_USB Overview
          2. 3.6.3.9.2 DPLL_USB Synthesized Clock Parameters
          3. 3.6.3.9.3 DPLL_USB Power Modes
          4. 3.6.3.9.4 DPLL_USB Recalibration
        10. 3.6.3.10 DPLL_EVE Description
          1. 3.6.3.10.1 DPLL_EVE Overview
          2. 3.6.3.10.2 DPLL_EVE Synthesized Clock Parameters
          3. 3.6.3.10.3 DPLL_EVE Power Modes
          4. 3.6.3.10.4 DPLL_EVE Recalibration
        11. 3.6.3.11 DPLL_DSP Description
          1. 3.6.3.11.1 DPLL_DSP Overview
          2. 3.6.3.11.2 DPLL_DSP Synthesized Clock Parameters
          3. 3.6.3.11.3 DPLL_DSP Power Modes
          4. 3.6.3.11.4 DPLL_DSP Recalibration
        12. 3.6.3.12 DPLL_GMAC Description
          1. 3.6.3.12.1 DPLL_GMAC Overview
          2. 3.6.3.12.2 DPLL_GMAC Synthesized Clock Parameters
          3. 3.6.3.12.3 DPLL_GMAC Power Modes
          4. 3.6.3.12.4 DPLL_GMAC Recalibration
        13. 3.6.3.13 DPLL_GPU Description
          1. 3.6.3.13.1 DPLL_GPU Overview
          2. 3.6.3.13.2 DPLL_GPU Synthesized Clock Parameters
          3. 3.6.3.13.3 DPLL_GPU Power Modes
          4. 3.6.3.13.4 DPLL_GPU Recalibration
        14. 3.6.3.14 DPLL_DDR Description
          1. 3.6.3.14.1 DPLL_DDR Overview
          2. 3.6.3.14.2 DPLL_DDR Synthesized Clock Parameters
          3. 3.6.3.14.3 DPLL_DDR Power Modes
          4. 3.6.3.14.4 DPLL_DDR Recalibration
        15. 3.6.3.15 DPLL_PCIE_REF Description
          1. 3.6.3.15.1 DPLL_PCIE_REF Overview
          2. 3.6.3.15.2 DPLL_PCIE_REF Synthesized Clock Parameters
          3. 3.6.3.15.3 DPLL_PCIE_REF Power Modes
        16. 3.6.3.16 APLL_PCIE Description
          1. 3.6.3.16.1 APLL_PCIE Overview
          2. 3.6.3.16.2 APLL_PCIE Synthesized Clock Parameters
          3. 3.6.3.16.3 APLL_PCIE Power Modes
      4. 3.6.4 Clock Domains
        1. 3.6.4.1  CD_WKUPAON Clock Domain
          1. 3.6.4.1.1 Overview
          2. 3.6.4.1.2 Clock Domain Modes
          3. 3.6.4.1.3 Clock Domain Dependency
            1. 3.6.4.1.3.1 Wake-Up Dependency
          4. 3.6.4.1.4 Clock Domain Module Attributes
        2. 3.6.4.2  CD_DSP1 Clock Domain
          1. 3.6.4.2.1 Overview
          2. 3.6.4.2.2 Clock Domain Modes
          3. 3.6.4.2.3 Clock Domain Dependency
            1. 3.6.4.2.3.1 Static Dependency
            2. 3.6.4.2.3.2 Dynamic Dependency
          4. 3.6.4.2.4 Clock Domain Module Attributes
        3. 3.6.4.3  CD_DSP2 Clock Domain
          1. 3.6.4.3.1 Overview
          2. 3.6.4.3.2 Clock Domain Modes
          3. 3.6.4.3.3 Clock Domain Dependency
            1. 3.6.4.3.3.1 Static Dependency
            2. 3.6.4.3.3.2 Dynamic Dependency
          4. 3.6.4.3.4 Clock Domain Module Attributes
        4. 3.6.4.4  CD_CUSTEFUSE Clock Domain
          1. 3.6.4.4.1 Overview
          2. 3.6.4.4.2 Clock Domain Modes
          3. 3.6.4.4.3 Clock Domain Dependency
          4. 3.6.4.4.4 Clock Domain Module Attributes
        5. 3.6.4.5  CD_MPU Clock Domain
          1. 3.6.4.5.1 Overview
          2. 3.6.4.5.2 Clock Domain Modes
          3. 3.6.4.5.3 Clock Domain Dependency
            1. 3.6.4.5.3.1 Static Dependency
            2. 3.6.4.5.3.2 Dynamic Dependency
          4. 3.6.4.5.4 Clock Domain Module Attributes
        6. 3.6.4.6  CD_L4PER1 Clock Domain
          1. 3.6.4.6.1 Overview
          2. 3.6.4.6.2 Clock Domain Modes
          3. 3.6.4.6.3 Clock Domain Dependency
            1. 3.6.4.6.3.1 Dynamic Dependency
            2. 3.6.4.6.3.2 Wake-Up Dependency
          4. 3.6.4.6.4 Clock Domain Module Attributes
        7. 3.6.4.7  CD_L4PER2 Clock Domain
          1. 3.6.4.7.1 Overview
          2. 3.6.4.7.2 Clock Domain Modes
          3. 3.6.4.7.3 Clock Domain Dependency
            1. 3.6.4.7.3.1 Dynamic Dependency
            2. 3.6.4.7.3.2 Wake-Up Dependency
          4. 3.6.4.7.4 Clock Domain Module Attributes
        8. 3.6.4.8  CD_L4PER3 Clock Domain
          1. 3.6.4.8.1 Overview
          2. 3.6.4.8.2 Clock Domain Modes
          3. 3.6.4.8.3 Clock Domain Dependency
            1. 3.6.4.8.3.1 Dynamic Dependency
            2. 3.6.4.8.3.2 Wake-Up Dependency
          4. 3.6.4.8.4 Clock Domain Module Attributes
        9. 3.6.4.9  CD_L4SEC Clock Domain
          1. 3.6.4.9.1 Overview
          2. 3.6.4.9.2 Clock Domain Modes
          3. 3.6.4.9.3 Clock Domain Dependency
            1. 3.6.4.9.3.1 Static Dependency
            2. 3.6.4.9.3.2 Dynamic Dependency
          4. 3.6.4.9.4 Clock Domain Module Attributes
          5. 3.6.4.9.5 289
        10. 3.6.4.10 CD_L3INIT Clock Domain
          1. 3.6.4.10.1 Overview
          2. 3.6.4.10.2 Clock Domain Modes
          3. 3.6.4.10.3 Clock Domain Dependency
            1. 3.6.4.10.3.1 Static Dependency
            2. 3.6.4.10.3.2 Dynamic Dependency
            3. 3.6.4.10.3.3 Wake-Up Dependency
          4. 3.6.4.10.4 Clock Domain Module Attributes
        11. 3.6.4.11 CD_IVA Clock Domain
          1. 3.6.4.11.1 Overview
          2. 3.6.4.11.2 Clock Domain Modes
          3. 3.6.4.11.3 Clock Domain Dependency
            1. 3.6.4.11.3.1 Static Dependency
            2. 3.6.4.11.3.2 Dynamic Dependency
          4. 3.6.4.11.4 Clock Domain Module Attributes
        12. 3.6.4.12 CD_GPU Description
          1. 3.6.4.12.1 Overview
          2. 3.6.4.12.2 Clock Domain Modes
          3. 3.6.4.12.3 Clock Domain Dependency
            1. 3.6.4.12.3.1 Static Dependency
            2. 3.6.4.12.3.2 Dynamic Dependency
          4. 3.6.4.12.4 Clock Domain Module Attributes
        13. 3.6.4.13 CD_EMU Clock Domain
          1. 3.6.4.13.1 Overview
          2. 3.6.4.13.2 Clock Domain Modes
          3. 3.6.4.13.3 Clock Domain Dependency
            1. 3.6.4.13.3.1 Dynamic Dependency
          4. 3.6.4.13.4 Clock Domain Module Attributes
        14. 3.6.4.14 CD_DSS Clock Domain
          1. 3.6.4.14.1 Overview
          2. 3.6.4.14.2 Clock Domain Modes
          3. 3.6.4.14.3 Clock Domain Dependency
            1. 3.6.4.14.3.1 Static Dependency
            2. 3.6.4.14.3.2 Dynamic Dependency
            3. 3.6.4.14.3.3 Wake-Up Dependency
          4. 3.6.4.14.4 Clock Domain Module Attributes
        15. 3.6.4.15 CD_L4_CFG Clock Domain
          1. 3.6.4.15.1 Overview
          2. 3.6.4.15.2 Clock Domain Modes
          3. 3.6.4.15.3 Clock Domain Dependency
            1. 3.6.4.15.3.1 Dynamic Dependency
          4. 3.6.4.15.4 Clock Domain Module Attributes
        16. 3.6.4.16 CD_L3_INSTR Clock Domain
          1. 3.6.4.16.1 Overview
          2. 3.6.4.16.2 Clock Domain Modes
          3. 3.6.4.16.3 Clock Domain Dependency
          4. 3.6.4.16.4 Clock Domain Module Attributes
        17. 3.6.4.17 CD_L3_MAIN1 Clock Domain
          1. 3.6.4.17.1 Overview
          2. 3.6.4.17.2 Clock Domain Modes
          3. 3.6.4.17.3 Clock Domain Dependency
            1. 3.6.4.17.3.1 Dynamic Dependency
          4. 3.6.4.17.4 Clock Domain Module Attributes
        18. 3.6.4.18 CD_EMIF Clock Domain
          1. 3.6.4.18.1 Overview
          2. 3.6.4.18.2 Clock Domain Modes
          3. 3.6.4.18.3 Clock Domain Dependency
          4. 3.6.4.18.4 Clock Domain Module Attributes
        19. 3.6.4.19 CD_IPU Clock Domain
          1. 3.6.4.19.1 Overview
          2. 3.6.4.19.2 Clock Domain Modes
          3. 3.6.4.19.3 Clock Domain Dependency
            1. 3.6.4.19.3.1 Static Dependency
            2. 3.6.4.19.3.2 Dynamic Dependency
          4. 3.6.4.19.4 Clock Domain Module Attributes
        20. 3.6.4.20 CD_IPU1 Clock Domain
          1. 3.6.4.20.1 Overview
          2. 3.6.4.20.2 Clock Domain Modes
          3. 3.6.4.20.3 Clock Domain Dependency
            1. 3.6.4.20.3.1 Static Dependency
            2. 3.6.4.20.3.2 Dynamic Dependency
          4. 3.6.4.20.4 Clock Domain Module Attributes
        21. 3.6.4.21 CD_IPU2 Clock Domain
          1. 3.6.4.21.1 Overview
          2. 3.6.4.21.2 Clock Domain Modes
          3. 3.6.4.21.3 Clock Domain Dependency
            1. 3.6.4.21.3.1 Static Dependency
            2. 3.6.4.21.3.2 Dynamic Dependency
          4. 3.6.4.21.4 Clock Domain Module Attributes
        22. 3.6.4.22 CD_DMA Clock Domain
          1. 3.6.4.22.1 Overview
          2. 3.6.4.22.2 Clock Domain Modes
          3. 3.6.4.22.3 Clock Domain Dependency
            1. 3.6.4.22.3.1 Static Dependency
            2. 3.6.4.22.3.2 Dynamic Dependency
          4. 3.6.4.22.4 Clock Domain Module Attributes
        23. 3.6.4.23 CD_ATL Clock Domain
          1. 3.6.4.23.1 Overview
          2. 3.6.4.23.2 Clock Domain Modes
          3. 3.6.4.23.3 Clock Domain Module Attributes
        24. 3.6.4.24 CD_CAM Clock Domain
          1. 3.6.4.24.1 Overview
          2. 3.6.4.24.2 Clock Domain Modes
          3. 3.6.4.24.3 Clock Domain Dependency
            1. 3.6.4.24.3.1 Static Dependency
            2. 3.6.4.24.3.2 Dynamic Dependency
          4. 3.6.4.24.4 Clock Domain Module Attributes
          5. 3.6.4.24.5 387
        25. 3.6.4.25 CD_GMAC Clock Domain
          1. 3.6.4.25.1 Overview
          2. 3.6.4.25.2 Clock Domain Modes
          3. 3.6.4.25.3 Clock Domain Dependency
            1. 3.6.4.25.3.1 Static Dependency
            2. 3.6.4.25.3.2 Dynamic Dependency
          4. 3.6.4.25.4 Clock Domain Module Attributes
        26. 3.6.4.26 CD_VPE Clock Domain
          1. 3.6.4.26.1 CD_VPE Overview
          2. 3.6.4.26.2 Clock Domain Modes
          3. 3.6.4.26.3 Clock Domain Dependency
            1. 3.6.4.26.3.1 Wake-Up Dependency
          4. 3.6.4.26.4 Clock Domain Module Attributes
        27. 3.6.4.27 CD_EVE1 Clock Domain
          1. 3.6.4.27.1 CD_EVE1 Overview
          2. 3.6.4.27.2 Clock Domain Modes
          3. 3.6.4.27.3 Clock Domain Dependency
            1. 3.6.4.27.3.1 Wake-Up Dependency
          4. 3.6.4.27.4 Clock Domain Module Attributes
        28. 3.6.4.28 CD_EVE2 Clock Domain
          1. 3.6.4.28.1 CD_EVE2 Overview
          2. 3.6.4.28.2 Clock Domain Modes
          3. 3.6.4.28.3 Clock Domain Dependency
            1. 3.6.4.28.3.1 Wake-Up Dependency
          4. 3.6.4.28.4 Clock Domain Module Attributes
        29. 3.6.4.29 CD_EVE3 Clock Domain
          1. 3.6.4.29.1 CD_EVE3 Overview
          2. 3.6.4.29.2 415
          3. 3.6.4.29.3 Clock Domain Modes
          4. 3.6.4.29.4 Clock Domain Dependency
            1. 3.6.4.29.4.1 Wake-Up Dependency
          5. 3.6.4.29.5 Clock Domain Module Attributes
        30. 3.6.4.30 CD_RTC Clock Domain
          1. 3.6.4.30.1 CD_RTC Overview
          2. 3.6.4.30.2 Clock Domain Modes
          3. 3.6.4.30.3 Clock Domain Dependency
            1. 3.6.4.30.3.1 Wake-Up Dependency
          4. 3.6.4.30.4 Clock Domain Module Attributes
        31. 3.6.4.31 CD_PCIE Clock Domain
          1. 3.6.4.31.1 CD_PCIE Overview
          2. 3.6.4.31.2 Clock Domain Modes
          3. 3.6.4.31.3 Clock Domain Dependency
            1. 3.6.4.31.3.1 Wake-Up Dependency
          4. 3.6.4.31.4 Clock Domain Module Attributes
    7. 3.7  Power Management Functional Description
      1. 3.7.1  PD_WKUPAON Description
        1. 3.7.1.1 Power Domain Modes
          1. 3.7.1.1.1 Logic and Memory Area Power Modes
      2. 3.7.2  PD_DSP1 Description
        1. 3.7.2.1 Power Domain Modes
          1. 3.7.2.1.1 Logic and Memory Area Power Modes
          2. 3.7.2.1.2 Logic and Memory Area Power Modes Control and Status
      3. 3.7.3  PD_DSP2 Description
        1. 3.7.3.1 Power Domain Modes
          1. 3.7.3.1.1 Logic and Memory Area Power Modes
          2. 3.7.3.1.2 Logic and Memory Area Power Modes Control and Status
      4. 3.7.4  PD_CUSTEFUSE Description
        1. 3.7.4.1 Power Domain Modes
          1. 3.7.4.1.1 Logic and Memory Area Power Modes
          2. 3.7.4.1.2 Logic and Memory Area Power Modes Control and Status
      5. 3.7.5  PD_MPU Description
        1. 3.7.5.1 Power Domain Modes
          1. 3.7.5.1.1 Logic and Memory Area Power Modes
          2. 3.7.5.1.2 Logic and Memory Area Power Modes Control and Status
          3. 3.7.5.1.3 Power State Override
      6. 3.7.6  PD_IPU Description
        1. 3.7.6.1 Power Domain Modes
          1. 3.7.6.1.1 Logic and Memory Area Power Modes
          2. 3.7.6.1.2 Logic and Memory Area Power Modes Control and Status
      7. 3.7.7  PD_L3INIT Description
        1. 3.7.7.1 Power Domain Modes
          1. 3.7.7.1.1 Logic and Memory Area Power Modes
          2. 3.7.7.1.2 Logic and Memory Area Power Modes Control and Status
      8. 3.7.8  PD_L4PER Description
        1. 3.7.8.1 Power Domain Modes
          1. 3.7.8.1.1 Logic and Memory Area Power Modes
          2. 3.7.8.1.2 Logic and Memory Area Power Modes Control and Status
      9. 3.7.9  PD_IVA Description
        1. 3.7.9.1 Power Domain Modes
          1. 3.7.9.1.1 Logic and Memory Area Power Modes
          2. 3.7.9.1.2 Logic and Memory Area Power Modes Control and Status
      10. 3.7.10 PD_GPU Description
        1. 3.7.10.1 Power Domain Modes
          1. 3.7.10.1.1 Logic and Memory Area Power Modes
          2. 3.7.10.1.2 Logic and Memory Area Power Modes Control and Status
      11. 3.7.11 PD_EMU Description
        1. 3.7.11.1 Power Domain Modes
          1. 3.7.11.1.1 Logic and Memory Area Power Modes
          2. 3.7.11.1.2 Logic and Memory Area Power Modes Control and Status
      12. 3.7.12 PD_DSS Description
        1. 3.7.12.1 Power Domain Modes
          1. 3.7.12.1.1 Logic and Memory Area Power Modes
          2. 3.7.12.1.2 Logic and Memory Area Power Mode Control and Status
      13. 3.7.13 PD_CORE Description
        1. 3.7.13.1 Power Domain Modes
          1. 3.7.13.1.1 Logic and Memory Area Power Modes
          2. 3.7.13.1.2 Logic and Memory Area Power Mode Control and Status
      14. 3.7.14 PD_CAM (Physical PD_COREAON) Description
        1. 3.7.14.1 Power Domain Modes
          1. 3.7.14.1.1 Logic and Memory Area Power Modes
          2. 3.7.14.1.2 Logic and Memory Area Power Mode Control and Status
      15. 3.7.15 PD_MPUAON Description
        1. 3.7.15.1 Power Domain Modes
      16. 3.7.16 PD_MMAON Description
        1. 3.7.16.1 Power Domain Modes
      17. 3.7.17 PD_COREAON Description
        1. 3.7.17.1 Power Domain Modes
      18. 3.7.18 PD_VPE Description
        1. 3.7.18.1 Power Domain Modes
          1. 3.7.18.1.1 Logic and Memory Area Power Modes
          2. 3.7.18.1.2 Logic and Memory Area Power Modes Control and Status
      19. 3.7.19 PD_EVE1 Description
        1. 3.7.19.1 Power Domain Modes
          1. 3.7.19.1.1 Logic and Memory Area Power Modes
          2. 3.7.19.1.2 Logic and Memory Area Power Modes Control and Status
      20. 3.7.20 PD_EVE2 Description
        1. 3.7.20.1 Power Domain Modes
          1. 3.7.20.1.1 Logic and Memory Area Power Modes
          2. 3.7.20.1.2 Logic and Memory Area Power Modes Control and Status
      21. 3.7.21 PD_EVE3 Description
        1. 3.7.21.1 Power Domain Modes
          1. 3.7.21.1.1 Logic and Memory Area Power Modes
          2. 3.7.21.1.2 Logic and Memory Area Power Modes Control and Status
      22. 3.7.22 PD_RTC Description
        1. 3.7.22.1 Power Domain Modes
          1. 3.7.22.1.1 Logic and Memory Area Power Modes
    8. 3.8  Voltage-Management Functional Description
      1. 3.8.1 Overview
      2. 3.8.2 Voltage-Control Architecture
      3. 3.8.3 Internal LDOs Control
        1. 3.8.3.1 VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
          1. 3.8.3.1.1 Adaptive Voltage Scaling
            1. 3.8.3.1.1.1 SmartReflex in the Device
        2. 3.8.3.2 Memory LDOs
        3. 3.8.3.3 ABB LDOs Control
        4. 3.8.3.4 ABB LDO Programming Sequence
          1. 3.8.3.4.1 ABB LDO Enable Sequence
          2. 3.8.3.4.2 ABB LDO Disable Sequence (Entering in Bypass Mode)
        5. 3.8.3.5 BANDGAPs Control
      4. 3.8.4 DVFS
    9. 3.9  Device Low-Power States
      1. 3.9.1 Device Wake-Up Source Summary
      2. 3.9.2 Wakeup Upon Global Warm Reset
      3. 3.9.3 Global Warm Reset During a Device Wake-Up Sequence
      4. 3.9.4 I/O Management
        1. 3.9.4.1 Isolation / Wakeup Sequence
          1. 3.9.4.1.1 Software-Controlled I/O Isolation
    10. 3.10 PRCM Module Programming Guide
      1. 3.10.1 DPLLs Low-Level Programming Models
        1. 3.10.1.1 Global Initialization
          1. 3.10.1.1.1 Surrounding Module Global Initialization
          2. 3.10.1.1.2 DPLL Global Initialization
            1. 3.10.1.1.2.1 Main Sequence – DPLL Global Initialization
            2. 3.10.1.1.2.2 Subsequence – Recalibration Parameter Configuration
            3. 3.10.1.1.2.3 Subsequence – Synthesized Clock Parameter Configuration
            4. 3.10.1.1.2.4 Subsequence – Output Clock Parameter Configuration
        2. 3.10.1.2 DPLL Output Frequency Change
      2. 3.10.2 Clock Management Low-Level Programming Models
        1. 3.10.2.1 Global Initialization
          1. 3.10.2.1.1 Surrounding Module Global Initialization
          2. 3.10.2.1.2 Clock Management Global Initialization
            1. 3.10.2.1.2.1 Main Sequence – Clock Domain Global Initialization
            2. 3.10.2.1.2.2 Subsequence – Slave Module Clock-Management Parameters Configuration
        2. 3.10.2.2 Clock Domain Sleep Transition and Troubleshooting
        3. 3.10.2.3 Enable/Disable Software-Programmable Static Dependency
      3. 3.10.3 Power Management Low-Level Programming Models
        1. 3.10.3.1 Global Initialization
          1. 3.10.3.1.1 Surrounding Module Global Initialization
          2. 3.10.3.1.2 Power Management Global Initialization
            1. 3.10.3.1.2.1 Main Sequence – Power Domain Global Initialization and Setting
        2. 3.10.3.2 Forced Memory Area State Change With Power Domain ON
        3. 3.10.3.3 Forced Power Domain Low-Power State Transition
    11. 3.11 560
    12. 3.12 PRCM Software Configuration for OPP_PLUS
    13. 3.13 PRCM Register Manual
      1. 3.13.1  PRCM Instance Summary
      2. 3.13.2  CM_CORE_AON__CKGEN Registers
        1. 3.13.2.1 CM_CORE_AON__CKGEN Register Summary
        2. 3.13.2.2 CM_CORE_AON__CKGEN Register Description
      3. 3.13.3  CM_CORE_AON__DSP1 Registers
        1. 3.13.3.1 CM_CORE_AON__DSP1 Register Summary
        2. 3.13.3.2 CM_CORE_AON__DSP1 Register Description
      4. 3.13.4  CM_CORE_AON__DSP2 Registers
        1. 3.13.4.1 CM_CORE_AON__DSP2 Register Summary
        2. 3.13.4.2 CM_CORE_AON__DSP2 Register Description
      5. 3.13.5  CM_CORE_AON__EVE1 Registers
        1. 3.13.5.1 CM_CORE_AON__EVE1 Register Summary
        2. 3.13.5.2 CM_CORE_AON__EVE1 Register Description
      6. 3.13.6  CM_CORE_AON__EVE2 Registers
        1. 3.13.6.1 CM_CORE_AON__EVE2 Register Summary
        2. 3.13.6.2 CM_CORE_AON__EVE2 Register Description
      7. 3.13.7  CORE_AON__EVE3 Registers
        1. 3.13.7.1 CM_CORE_AON__EVE3 Register Summary
        2. 3.13.7.2 CM_CORE_AON__EVE3 Register Description
      8. 3.13.8  CM_CORE_AON__INSTR Registers
        1. 3.13.8.1 CM_CORE_AON__INSTR Register Summary
        2. 3.13.8.2 CM_CORE_AON__INSTR Register Description
      9. 3.13.9  CM_CORE_AON__IPU Registers
        1. 3.13.9.1 CM_CORE_AON__IPU Register Summary
        2. 3.13.9.2 CM_CORE_AON__IPU Register Description
      10. 3.13.10 CM_CORE_AON__MPU Registers
        1. 3.13.10.1 CM_CORE_AON__MPU Register Summary
        2. 3.13.10.2 CM_CORE_AON__MPU Register Description
      11. 3.13.11 CM_CORE_AON__OCP_SOCKET Registers
        1. 3.13.11.1 CM_CORE_AON__OCP_SOCKET Register Summary
        2. 3.13.11.2 CM_CORE_AON__OCP_SOCKET Register Description
      12. 3.13.12 CM_CORE_AON__RESTORE Registers
        1. 3.13.12.1 CM_CORE_AON__RESTORE Register Summary
        2. 3.13.12.2 CM_CORE_AON__RESTORE Register Description
      13. 3.13.13 CM_CORE_AON__RTC Registers
        1. 3.13.13.1 CM_CORE_AON__RTC Register Summary
        2. 3.13.13.2 CM_CORE_AON__RTC Register Description
      14. 3.13.14 CM_CORE_AON__VPE Registers
        1. 3.13.14.1 CM_CORE_AON__VPE Register Summary
        2. 3.13.14.2 CM_CORE_AON__VPE Register Description
      15. 3.13.15 CM_CORE__CAM Registers
        1. 3.13.15.1 CM_CORE__CAM Register Summary
        2. 3.13.15.2 CM_CORE__CAM Register Description
      16. 3.13.16 CM_CORE__CKGEN Registers
        1. 3.13.16.1 CM_CORE__CKGEN Register Summary
        2. 3.13.16.2 CM_CORE__CKGEN Register Description
      17. 3.13.17 CM_CORE__COREAON Registers
        1. 3.13.17.1 CM_CORE__COREAON Register Summary
        2. 3.13.17.2 CM_CORE__COREAON Register Description
      18. 3.13.18 CM_CORE__CORE Registers
        1. 3.13.18.1 CM_CORE__CORE Register Summary
        2. 3.13.18.2 CM_CORE__CORE Register Description
      19. 3.13.19 CM_CORE__CUSTEFUSE Registers
        1. 3.13.19.1 CM_CORE__CUSTEFUSE Register Summary
        2. 3.13.19.2 CM_CORE__CUSTEFUSE Register Description
      20. 3.13.20 CM_CORE__DSS Registers
        1. 3.13.20.1 CM_CORE__DSS Register Summary
        2. 3.13.20.2 CM_CORE__DSS Register Description
      21. 3.13.21 CM_CORE__GPU Registers
        1. 3.13.21.1 CM_CORE__GPU Register Summary
        2. 3.13.21.2 CM_CORE__GPU Register Description
      22. 3.13.22 CM_CORE__IVA Registers
        1. 3.13.22.1 CM_CORE__IVA Register Summary
        2. 3.13.22.2 CM_CORE__IVA Register Description
      23. 3.13.23 CM_CORE__L3INIT Registers
        1. 3.13.23.1 CM_CORE__L3INIT Register Summary
        2. 3.13.23.2 CM_CORE__L3INIT Register Description
      24. 3.13.24 CM_CORE__L4PER Registers
        1. 3.13.24.1 CM_CORE__L4PER Register Summary
        2. 3.13.24.2 CM_CORE__L4PER Register Description
      25. 3.13.25 CM_CORE__OCP_SOCKET Registers
        1. 3.13.25.1 CM_CORE__OCP_SOCKET Register Summary
        2. 3.13.25.2 CM_CORE__OCP_SOCKET Register Description
      26. 3.13.26 CM_CORE__RESTORE Registers
        1. 3.13.26.1 CM_CORE__RESTORE Register Summary
        2. 3.13.26.2 CM_CORE__RESTORE Register Description
      27. 3.13.27 CAM_PRM Registers
        1. 3.13.27.1 CAM_PRM Register Summary
        2. 3.13.27.2 CAM_PRM Register Description
      28. 3.13.28 CKGEN_PRM Registers
        1. 3.13.28.1 CKGEN_PRM Register Summary
        2. 3.13.28.2 CKGEN_PRM Register Description
      29. 3.13.29 CORE_PRM Registers
        1. 3.13.29.1 CORE_PRM Register Summary
        2. 3.13.29.2 CORE_PRM Register Description
      30. 3.13.30 CUSTEFUSE_PRM Registers
        1. 3.13.30.1 CUSTEFUSE_PRM Register Summary
        2. 3.13.30.2 CUSTEFUSE_PRM Register Description
      31. 3.13.31 DEVICE_PRM Registers
        1. 3.13.31.1 DEVICE_PRM Register Summary
        2. 3.13.31.2 DEVICE_PRM Register Description
      32. 3.13.32 DSP1_PRM Registers
        1. 3.13.32.1 DSP1_PRM Register Summary
        2. 3.13.32.2 DSP1_PRM Register Description
      33. 3.13.33 DSP2_PRM Registers
        1. 3.13.33.1 DSP2_PRM Register Summary
        2. 3.13.33.2 DSP2_PRM Register Description
      34. 3.13.34 DSS_PRM Registers
        1. 3.13.34.1 DSS_PRM Register Summary
        2. 3.13.34.2 DSS_PRM Register Description
      35. 3.13.35 EMU_CM Registers
        1. 3.13.35.1 EMU_CM Register Summary
        2. 3.13.35.2 EMU_CM Register Description
      36. 3.13.36 EMU_PRM Registers
        1. 3.13.36.1 EMU_PRM Register Summary
        2. 3.13.36.2 EMU_PRM Register Description
      37. 3.13.37 EVE1_PRM Registers
        1. 3.13.37.1 EVE1_PRM Register Summary
        2. 3.13.37.2 EVE1_PRM Register Description
      38. 3.13.38 EVE2_PRM Registers
        1. 3.13.38.1 EVE2_PRM Register Summary
        2. 3.13.38.2 EVE2_PRM Register Description
      39. 3.13.39 EVE3_PRM Registers
        1. 3.13.39.1 EVE3_PRM Register Summary
        2. 3.13.39.2 EVE3_PRM Register Description
      40. 3.13.40 GPU_PRM Registers
        1. 3.13.40.1 GPU_PRM Register Summary
        2. 3.13.40.2 GPU_PRM Register Description
      41. 3.13.41 INSTR_PRM Registers
        1. 3.13.41.1 INSTR_PRM Register Summary
        2. 3.13.41.2 INSTR_PRM Register Description
      42. 3.13.42 IPU_PRM Registers
        1. 3.13.42.1 IPU_PRM Register Summary
        2. 3.13.42.2 IPU_PRM Register Description
      43. 3.13.43 IVA_PRM Registers
        1. 3.13.43.1 IVA_PRM Register Summary
        2. 3.13.43.2 IVA_PRM Register Description
      44. 3.13.44 L3INIT_PRM Registers
        1. 3.13.44.1 L3INIT_PRM Register Summary
        2. 3.13.44.2 L3INIT_PRM Register Description
      45. 3.13.45 L4PER_PRM Registers
        1. 3.13.45.1 L4PER_PRM Register Summary
        2. 3.13.45.2 L4PER_PRM Register Description
      46. 3.13.46 MPU_PRM Registers
        1. 3.13.46.1 MPU_PRM Register Summary
        2. 3.13.46.2 MPU_PRM Register Description
      47. 3.13.47 OCP_SOCKET_PRM Registers
        1. 3.13.47.1 OCP_SOCKET_PRM Register Summary
        2. 3.13.47.2 OCP_SOCKET_PRM Register Description
      48. 3.13.48 RTC_PRM Registers
        1. 3.13.48.1 RTC_PRM Register Summary
        2. 3.13.48.2 RTC_PRM Register Description
      49. 3.13.49 VPE_PRM Registers
        1. 3.13.49.1 VPE_PRM Register Summary
        2. 3.13.49.2 VPE_PRM Register Description
      50. 3.13.50 WKUPAON_CM Registers
        1. 3.13.50.1 WKUPAON_CM Register Summary
        2. 3.13.50.2 WKUPAON_CM Register Description
      51. 3.13.51 WKUPAON_PRM Registers
        1. 3.13.51.1 WKUPAON_PRM Register Summary
        2. 3.13.51.2 WKUPAON_PRM Register Description
  6. 4 Dual Cortex-A15 MPU Subsystem
    1. 4.1 Dual Cortex-A15 MPU Subsystem Overview
      1. 4.1.1 Introduction
      2. 4.1.2 Features
    2. 4.2 Dual Cortex-A15 MPU Subsystem Integration
      1. 4.2.1 Clock Distribution
      2. 4.2.2 Reset Distribution
    3. 4.3 Dual Cortex-A15 MPU Subsystem Functional Description
      1. 4.3.1 MPU Subsystem Block Diagram
      2. 4.3.2 Cortex-A15 MPCore (MPU_CLUSTER)
        1. 4.3.2.1 MPU L2 Cache Memory System
          1. 4.3.2.1.1 MPU L2 Cache Architecture
          2. 4.3.2.1.2 MPU L2 Cache Controller
          3. 4.3.2.1.3 727
      3. 4.3.3 MPU_AXI2OCP
      4. 4.3.4 Memory Adapter
        1. 4.3.4.1 MPU_MA Overview
        2. 4.3.4.2 AXI Input Interface
        3. 4.3.4.3 Interleaving
          1. 4.3.4.3.1 High-Order Fixed Interleaving Model
          2. 4.3.4.3.2 Lower 2-GiB Programmable Interleaving Model
          3. 4.3.4.3.3 Local Interconnect and Synchronization Agent (LISA) Section Manager
          4. 4.3.4.3.4 MA_LSM Registers
          5. 4.3.4.3.5 Posted and Nonposted Writes
          6. 4.3.4.3.6 Errors
        4. 4.3.4.4 Statistics Collector Probe Ports
        5. 4.3.4.5 MPU_MA Firewall
        6. 4.3.4.6 MPU_MA Power and Reset Management
        7. 4.3.4.7 MPU_MA Watchpoint
          1. 4.3.4.7.1 Watchpoint Types
          2. 4.3.4.7.2 Transaction Filtering Options
          3. 4.3.4.7.3 Transaction Match Effects
          4. 4.3.4.7.4 Trigger Generation
          5. 4.3.4.7.5 Programming Options Summary
      5. 4.3.5 Realtime Counter (Master Counter)
        1. 4.3.5.1 Counter Operation
        2. 4.3.5.2 Frequency Change Procedure
      6. 4.3.6 MPU Watchdog Timer
      7. 4.3.7 MPU Subsystem Power Management
        1. 4.3.7.1 Power Domains
        2. 4.3.7.2 Power States of MPU_Cx
        3. 4.3.7.3 Power States of MPU Subsystem
        4. 4.3.7.4 MPU_WUGEN
        5. 4.3.7.5 Power Transition Sequence
        6. 4.3.7.6 SR3-APG Technology Fail-Safe Mode
      8. 4.3.8 MPU Subsystem AMBA Interface Configuration
    4. 4.4 Dual Cortex-A15 MPU Subsystem Register Manual
      1. 4.4.1  Dual Cortex-A15 MPU Subsystem Instance Summary
      2. 4.4.2  MPU_CS_STM Registers
      3. 4.4.3  MPU_INTC Registers
      4. 4.4.4  MPU_PRCM_OCP_SOCKET Registers
        1. 4.4.4.1 MPU_PRCM_OCP_SOCKET Register Summary
        2. 4.4.4.2 MPU_PRCM_OCP_SOCKET Register Description
      5. 4.4.5  MPU_PRCM_DEVICE Registers
        1. 4.4.5.1 MPU_PRCM_DEVICE Register Summary
        2. 4.4.5.2 MPU_PRCM_DEVICE Register Description
      6. 4.4.6  MPU_PRCM_PRM_C0 Registers
        1. 4.4.6.1 MPU_PRCM_PRM_C0 Register Summary
        2. 4.4.6.2 MPU_PRCM_PRM_C0 Register Description
      7. 4.4.7  MPU_PRCM_CM_C0 Registers
        1. 4.4.7.1 MPU_PRCM_CM_C0 Register Summary
        2. 4.4.7.2 MPU_PRCM_CM_C0 Register Description
      8. 4.4.8  MPU_PRCM_PRM_C1 Registers
        1. 4.4.8.1 MPU_PRCM_PRM_C1 Register Summary
        2. 4.4.8.2 MPU_PRCM_PRM_C1 Register Description
      9. 4.4.9  MPU_PRCM_CM_C1 Registers
        1. 4.4.9.1 MPU_PRCM_CM_C1 Register Summary
        2. 4.4.9.2 MPU_PRCM_CM_C1 Register Description
      10. 4.4.10 MPU_WUGEN Registers
        1. 4.4.10.1 MPU_WUGEN Register Summary
        2. 4.4.10.2 MPU_WUGEN Register Description
      11. 4.4.11 MPU_WD_TIMER Registers
        1. 4.4.11.1 MPU_WD_TIMER Register Summary
        2. 4.4.11.2 MPU_WD_TIMER Register Description
      12. 4.4.12 MPU_AXI2OCP_MISC Registers
        1. 4.4.12.1 MPU_AXI2OCP_MISC Register Summary
        2. 4.4.12.2 MPU_AXI2OCP_MISC Register Description
      13. 4.4.13 MPU_MA_LSM Registers
        1. 4.4.13.1 MPU_MA_LSM Register Summary
        2. 4.4.13.2 MPU_MA_LSM Register Description
      14. 4.4.14 MPU_MA_WP Registers
        1. 4.4.14.1 MPU_MA_WP Register Summary
        2. 4.4.14.2 MPU_MA_WP Register Description
  7. 5 DSP Subsystems
    1. 5.1 DSP Subsystems Overview
      1. 5.1.1 DSP Subsystems Key Features
    2. 5.2 DSP Subsystem Integration
    3. 5.3 DSP Subsystems Functional Description
      1. 5.3.1  DSP Subsystems Block Diagram
      2. 5.3.2  DSP Subsystem Components
        1. 5.3.2.1 C66x DSP Subsystem Introduction
        2. 5.3.2.2 DSP TMS320C66x CorePac
          1. 5.3.2.2.1 DSP TMS320C66x CorePac CPU
          2. 5.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories
            1. 5.3.2.2.2.1 Level 1 Memories
            2. 5.3.2.2.2.2 Level 2 Memory
          3. 5.3.2.2.3 DSP C66x CorePac Internal Peripherals
            1. 5.3.2.2.3.1 DSP C66x CorePac Interrupt Controller (DSP INTC)
            2. 5.3.2.2.3.2 DSP C66x CorePac Power-Down Controller (DSP PDC)
            3. 5.3.2.2.3.3 DSP C66x CorePac Bandwidth Manager (BWM)
            4. 5.3.2.2.3.4 DSP C66x CorePac Memory Protection Hardware
            5. 5.3.2.2.3.5 DSP C66x CorePac Internal DMA (IDMA) Controller
            6. 5.3.2.2.3.6 DSP C66x CorePac External Memory Controller
            7. 5.3.2.2.3.7 DSP C66x CorePac Extended Memory Controller
              1. 5.3.2.2.3.7.1 XMC MDMA Accesses at DSP System Level
                1. 5.3.2.2.3.7.1.1 DSP System MPAX Logic
                2. 5.3.2.2.3.7.1.2 MDMA Non-Post Override Control
            8. 5.3.2.2.3.8 L1P Memory Error Detection Logic
            9. 5.3.2.2.3.9 L2 Memory Error Detection and Correction Logic
        3. 5.3.2.3 DSP Debug and Trace Support
          1. 5.3.2.3.1 DSP Advanced Event Triggering (AET)
          2. 5.3.2.3.2 DSP Trace Support
          3. 5.3.2.3.3 826
      3. 5.3.3  DSP System Control Logic
        1. 5.3.3.1 DSP System Clocks
        2. 5.3.3.2 DSP Hardware Resets
        3. 5.3.3.3 DSP Software Resets
        4. 5.3.3.4 DSP Power Management
          1. 5.3.3.4.1 DSP System Powerdown Protocols
          2. 5.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview
          3. 5.3.3.4.3 DSP IDLE Wakeup
          4. 5.3.3.4.4 DSP SYSTEM IRQWAKEEN registers
          5. 5.3.3.4.5 DSP Automatic Power Transition
      4. 5.3.4  DSP Interrupt Requests
        1. 5.3.4.1 DSP Input Interrupts
          1. 5.3.4.1.1 DSP Non-maskable Interrupt Input
        2. 5.3.4.2 DSP Event and Interrupt Generation Outputs
          1. 5.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs
          2. 5.3.4.2.2 DSP Aggregated Error Interrupt Output
          3. 5.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
      5. 5.3.5  DSP DMA Requests
        1. 5.3.5.1 DSP EDMA Wakeup Interrupt
      6. 5.3.6  DSP Intergated Memory Management Units
        1. 5.3.6.1 DSP MMUs Overview
        2. 5.3.6.2 Routing MDMA Traffic through DSP MMU0
        3. 5.3.6.3 Routing EDMA Traffic thorugh DSP MMU1
      7. 5.3.7  DSP Integrated EDMA Subsystem
        1. 5.3.7.1 DSP EDMA Overview
        2. 5.3.7.2 DSP System and Device Level Settings of DSP EDMA
      8. 5.3.8  DSP L2 interconnect Network
        1. 5.3.8.1 DSP Public Firewall Settings
        2. 5.3.8.2 DSP NoC Flag Mux and Error Log Registers
        3. 5.3.8.3 DSP NoC Arbitration
      9. 5.3.9  DSP Boot Configuration
      10. 5.3.10 DSP Internal and External Memory Views
        1. 5.3.10.1 C66x CPU View of the Address Space
        2. 5.3.10.2 DSP_EDMA View of the Address Space
        3. 5.3.10.3 L3_MAIN View of the DSP Address Space
    4. 5.4 DSP Subsystem Register Manual
      1. 5.4.1 DSP Subsystem Instance Summary
      2. 5.4.2 DSP_ICFG Registers
        1. 5.4.2.1 DSP_ICFG Register Summary
        2. 5.4.2.2 DSP_ICFG Register Description
      3. 5.4.3 DSP_SYSTEM Registers
        1. 5.4.3.1 DSP_SYSTEM Register Summary
        2. 5.4.3.2 DSP_SYSTEM Register Description
      4. 5.4.4 DSP_FW_L2_NOC_CFG Registers
        1. 5.4.4.1 DSP_FW_L2_NOC_CFG Register Summary
        2. 5.4.4.2 DSP_FW_L2_NOC_CFG Register Description
  8. 6 IVA Subsystem
  9. 7 Dual Cortex-M4 IPU Subsystem
    1. 7.1 Dual Cortex-M4 IPU Subsystem Overview
      1. 7.1.1 Introduction
      2. 7.1.2 Features
    2. 7.2 Dual Cortex-M4 IPU Subsystem Integration
      1. 7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
        1. 7.2.1.1 Clock Distribution
        2. 7.2.1.2 Reset Distribution
    3. 7.3 Dual Cortex-M4 IPU Subsystem Functional Description
      1. 7.3.1 IPUx Subsystem Block Diagram
      2. 7.3.2 Power Management
        1. 7.3.2.1 Local Power Management
        2. 7.3.2.2 Power Domains
        3. 7.3.2.3 887
        4. 7.3.2.4 Voltage Domain
        5. 7.3.2.5 Power States and Modes
        6. 7.3.2.6 Wake-Up Generator (IPUx_WUGEN)
          1. 7.3.2.6.1 IPUx_WUGEN Main Features
      3. 7.3.3 IPUx_UNICACHE
      4. 7.3.4 IPUx_UNICACHE_MMU
      5. 7.3.5 IPUx_UNICACHE_SCTM
        1. 7.3.5.1 Counter Functions
          1. 7.3.5.1.1 Input Events
          2. 7.3.5.1.2 Counters
            1. 7.3.5.1.2.1 Counting Modes
            2. 7.3.5.1.2.2 Counter Overflow
            3. 7.3.5.1.2.3 Counters and Processor State
            4. 7.3.5.1.2.4 Chaining Counters
            5. 7.3.5.1.2.5 Enabling and Disabling Counters
            6. 7.3.5.1.2.6 Resetting Counters
        2. 7.3.5.2 Timer Functions
          1. 7.3.5.2.1 Periodic Intervals
          2. 7.3.5.2.2 Event Generation
      6. 7.3.6 IPUx_MMU
        1. 7.3.6.1 IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
      7. 7.3.7 Interprocessor Communication (IPC)
        1. 7.3.7.1 Use of WFE and SEV
        2. 7.3.7.2 Use of Interrupt for IPC
        3. 7.3.7.3 Use of the Bit-Band Feature for Semaphore Operations
        4. 7.3.7.4 Private Memory Space
      8. 7.3.8 IPU Boot Options
    4. 7.4 Dual Cortex-M4 IPU Subsystem Register Manual
      1. 7.4.1 IPUx Subsystem Instance Summary
      2. 7.4.2 IPUx_UNICACHE_CFG Registers
        1. 7.4.2.1 IPUx_UNICACHE_CFG Register Summary
        2. 7.4.2.2 IPUx_UNICACHE_CFG Register Description
      3. 7.4.3 IPUx_UNICACHE_SCTM Registers
        1. 7.4.3.1 IPUx_UNICACHE_SCTM Register Summary
        2. 7.4.3.2 IPUx_UNICACHE_SCTM Register Description
      4. 7.4.4 IPUx_UNICACHE_MMU (AMMU) Registers
        1. 7.4.4.1 IPUx_UNICACHE_MMU (AMMU) Register Summary
        2. 7.4.4.2 IPUx_UNICACHE_MMU (AMMU) Register Description
      5. 7.4.5 IPUx_MMU Registers
      6. 7.4.6 IPUx_Cx_INTC Registers
      7. 7.4.7 IPUx_WUGEN Registers
        1. 7.4.7.1 IPUx_WUGEN Register Summary
        2. 7.4.7.2 IPUx_WUGEN Register Description
      8. 7.4.8 IPUx_Cx_RW_TABLE Registers
        1. 7.4.8.1 IPUx_Cx_RW_TABLE Register Summary
        2. 7.4.8.2 IPUx_Cx_RW_TABLE Register Description
  10. 8 Embedded Vision Engine
    1. 8.1 Embedded Vision Engine (EVE) Subsystem
      1. 8.1.1 EVE Overview
        1. 8.1.1.1 EVE Memories
      2. 8.1.2 EVE Integration
        1. 8.1.2.1 Multi-EVE Recommended Connections
      3. 8.1.3 EVE Functional Description
        1. 8.1.3.1  EVE Connection ID (ConnID) Mapping
        2. 8.1.3.2  EVE Processors Overview
          1. 8.1.3.2.1 Scalar Core (ARP32)
          2. 8.1.3.2.2 VCOP
          3. 8.1.3.2.3 Scalar-Vector Interaction
        3. 8.1.3.3  Internal Memory Overview
          1. 8.1.3.3.1 Program Cache/Memory
          2. 8.1.3.3.2 ARP32 Data Memory (DMEM)
          3. 8.1.3.3.3 WBUF
          4. 8.1.3.3.4 Image Buffers–IBUFLA, IBUFLB, IBUFHA, and IBUFHB
          5. 8.1.3.3.5 Memory Switch Error Registers
          6. 8.1.3.3.6 Memory Error Detection
            1. 8.1.3.3.6.1 Captured Address – EDADDR and EDADDR_BO
            2. 8.1.3.3.6.2 Modes of Operation
            3. 8.1.3.3.6.3 Parity Error Testability
            4. 8.1.3.3.6.4 Parity Error Recovery
          7. 8.1.3.3.7 VCOP System Error Halt Conditions
        4. 8.1.3.4  Program Cache Architecture
          1. 8.1.3.4.1 Basic Operation
          2. 8.1.3.4.2 Line Buffer
          3. 8.1.3.4.3 Software Direct Preload
          4. 8.1.3.4.4 User Coherence Operation
            1. 8.1.3.4.4.1 Global Invalidate
            2. 8.1.3.4.4.2 Range-Based Invalidate
            3. 8.1.3.4.4.3 Single-Address Invalidate – For Breakpoint Operation
          5. 8.1.3.4.5 Demand-Based Prefetch
          6. 8.1.3.4.6 Debug Support
            1. 8.1.3.4.6.1 Read/Write Accessibility through OCP Debug Target Port
            2. 8.1.3.4.6.2 Breakpoint Support
            3. 8.1.3.4.6.3 Cache Profiling
          7. 8.1.3.4.7 Error Detection
        5. 8.1.3.5  EDMA
          1. 8.1.3.5.1 DMA Channel Events
          2. 8.1.3.5.2 DMA Parameter Set
          3. 8.1.3.5.3 Channel Controller
          4. 8.1.3.5.4 EVE-Level Bus Width and Throughput
            1. 8.1.3.5.4.1 Concurrent Transfer Requirements
        6. 8.1.3.6  General-Purpose Inputs/Outputs
        7. 8.1.3.7  CME Signaling
        8. 8.1.3.8  Multi-EVE and VIP Usage Models
          1. 8.1.3.8.1 Data Partitioning
          2. 8.1.3.8.2 Task Partitioning
          3. 8.1.3.8.3 983
        9. 8.1.3.9  Memory Management Unit
        10. 8.1.3.10 Interrupt Control
          1. 8.1.3.10.1 EVE Interrupt Sources – Memory Switch and Parity Error Interrupts
          2. 8.1.3.10.2 ARP32 INTC
          3. 8.1.3.10.3 Output Interrupt Reduction
          4. 8.1.3.10.4 End of Interrupt Mapping
        11. 8.1.3.11 Interprocessor Communication
          1. 8.1.3.11.1 Mailbox Configuration
            1. 8.1.3.11.1.1 Mailbox 0 – EVE to DSP1, DSP2 and MPU
            2. 8.1.3.11.1.2 Mailbox 1 – EVE to Other Hosts
            3. 8.1.3.11.1.3 Mailbox 2 – EVE to EVE in a 2x EVE System
        12. 8.1.3.12 Powerdown
          1. 8.1.3.12.1 Extended Duration Sleep
            1. 8.1.3.12.1.1 Sequence Overview
            2. 8.1.3.12.1.2 Idle Protocol Overview
            3. 8.1.3.12.1.3 Mstandby Protocol Overview
            4. 8.1.3.12.1.4 IDLE Wakeup
        13. 8.1.3.13 Hardware-Assisted Software Self-Test – MISRs
          1. 8.1.3.13.1 Mapping of MISRs to Different Width Buses
          2. 8.1.3.13.2 Detection of Valid Address and Data Cycles
          3. 8.1.3.13.3 Creating a Unique Signature – Software Self-Test Implications
          4. 8.1.3.13.4 Multipass Tests Using WBUF MISR
        14. 8.1.3.14 Error Recovery – ARP32 and OCP Disconnect
          1. 8.1.3.14.1 ARP32 Disconnect
          2. 8.1.3.14.2 OCP Initiator Disconnect
        15. 8.1.3.15 Lock and Unlock Feature
        16. 8.1.3.16 EVE Memory Map
          1. 8.1.3.16.1 VCOP and Local EDMA: IBUF Memory Map Aliasing
          2. 8.1.3.16.2 ARP32 Write Model – Avoiding Race Conditions
        17. 8.1.3.17 Debug Support
          1. 8.1.3.17.1 ARP32 Debug Support
          2. 8.1.3.17.2 SCTM
            1. 8.1.3.17.2.1 SCTM Configuration
            2. 8.1.3.17.2.2 SCTM Resources Reserved for BIOS
            3. 8.1.3.17.2.3 SCTM Event Mapping
            4. 8.1.3.17.2.4 SCTM Halt and Idle Modes
          3. 8.1.3.17.3 SMSET
            1. 8.1.3.17.3.1 SMSET Configuration
            2. 8.1.3.17.3.2 SMSET Event Mapping
        18. 8.1.3.18 EVE L2_FNOC Interconnect
          1. 8.1.3.18.1 EVE L2_FNOC Flag Mux and Error Log Registers
      4. 8.1.4 EVE Programming Model
        1. 8.1.4.1 Boot
        2. 8.1.4.2 Task Change and Program Cache Prefetch
          1. 8.1.4.2.1 Simple or Unoptimized Branch to New Task
          2. 8.1.4.2.2 Prefetch, Wait, then Branch to New Task
          3. 8.1.4.2.3 Hidden Prefetch
        3. 8.1.4.3 Interrupts
        4. 8.1.4.4 Safety Considerations
          1. 8.1.4.4.1 Memory Error Detection
          2. 8.1.4.4.2 MMU
          3. 8.1.4.4.3 Firewall
          4. 8.1.4.4.4 Interconnect
          5. 8.1.4.4.5 Application Stability/Sequencing
          6. 8.1.4.4.6 Interrupt Servicing
      5. 8.1.5 EVE Subsystem Register Manual
        1. 8.1.5.1 EVE Instance Summary
        2. 8.1.5.2 EVE Register Summary and Description
          1. 8.1.5.2.1 EVE Register Summary
          2. 8.1.5.2.2 EVE Register Description
        3. 8.1.5.3 EVE L2_FNOC Register Summary and Description
          1. 8.1.5.3.1 EVE L2_FNOC Register Summary
          2. 8.1.5.3.2 EVE L2_FNOC Register Description
      6. 8.1.6 Subsystem Counter Timer Module
        1. 8.1.6.1 Introduction
          1. 8.1.6.1.1 Overview
          2. 8.1.6.1.2 Top-Level Requirements
          3. 8.1.6.1.3 Configuration
          4. 8.1.6.1.4 Block Diagram
        2. 8.1.6.2 Functional Description
          1. 8.1.6.2.1 Configuration Interface
          2. 8.1.6.2.2 Counter Function
            1. 8.1.6.2.2.1 Input Events
            2. 8.1.6.2.2.2 Counters
            3. 8.1.6.2.2.3 Counting Mode
            4. 8.1.6.2.2.4 Counter Overflow
            5. 8.1.6.2.2.5 Counters and Processor State
            6. 8.1.6.2.2.6 Chaining Counters
              1. 8.1.6.2.2.6.1 Reading Chained Counters
            7. 8.1.6.2.2.7 Enabling and Disabling Counters
            8. 8.1.6.2.2.8 Resetting Counters
          3. 8.1.6.2.3 Timer Function
            1. 8.1.6.2.3.1 Periodic Intervals
            2. 8.1.6.2.3.2 Event Generation
            3. 8.1.6.2.3.3 Watchdog Timer Function
          4. 8.1.6.2.4 System Trace Integration
            1. 8.1.6.2.4.1 Overview
            2. 8.1.6.2.4.2 STM Configuration
              1. 8.1.6.2.4.2.1 Periodic Counter State Export
              2. 8.1.6.2.4.2.2 Application Control of Counter State Export
              3. 8.1.6.2.4.2.3 Application Control of the Counter Configuration Export
        3. 8.1.6.3 Use Case Examples
          1. 8.1.6.3.1 Counter Enable
            1. 8.1.6.3.1.1 Enabling a Single Counter
            2. 8.1.6.3.1.2 Reading a Single Counter
            3. 8.1.6.3.1.3 Enabling a Group of Counters Simultaneously
            4. 8.1.6.3.1.4 Reading a Group of Counters Simultaneously
            5. 8.1.6.3.1.5 Configuring a Chained Counter
          2. 8.1.6.3.2 Timer Enable
          3. 8.1.6.3.3 Periodic STM Export Enable
          4. 8.1.6.3.4 Disabling the SCTM
        4. 8.1.6.4 SCTM Register Manual
          1. 8.1.6.4.1 SCTM Instance Summary
          2. 8.1.6.4.2 SCTM Registers
            1. 8.1.6.4.2.1 SCTM Register Summary
            2. 8.1.6.4.2.2 SCTM Register Description
      7. 8.1.7 Software Message and System Event Trace
        1. 8.1.7.1 Introduction
          1. 8.1.7.1.1 Overview
          2. 8.1.7.1.2 Configuration
          3. 8.1.7.1.3 Block Diagram
        2. 8.1.7.2 Functional Description
          1. 8.1.7.2.1 Connectivity
          2. 8.1.7.2.2 SMSET Event Mapping
          3. 8.1.7.2.3 Software Messages
          4. 8.1.7.2.4 SMSET Master Port
            1. 8.1.7.2.4.1 OCP Disconnect
          5. 8.1.7.2.5 SMSET Debug Features
          6. 8.1.7.2.6 Component Ownership
            1. 8.1.7.2.6.1 Ownership State
              1. 8.1.7.2.6.1.1 Available State
              2. 8.1.7.2.6.1.2 Claimed State
              3. 8.1.7.2.6.1.3 Enabled State
            2. 8.1.7.2.6.2 Ownership Commands
            3. 8.1.7.2.6.3 Claim Reset
        3. 8.1.7.3 Use Case Examples
          1. 8.1.7.3.1 Procedure to Enable System Event Capture
          2. 8.1.7.3.2 Procedure to Start and Stop System Event Capture from External Trigger Detection
          3. 8.1.7.3.3 Procedure to Disable System Event Capture
        4. 8.1.7.4 SMSET Register Manual
          1. 8.1.7.4.1 SMSET Instance Summary
          2. 8.1.7.4.2 SMSET Register Summary
          3. 8.1.7.4.3 SMSET Register Description
    2. 8.2 ARP32 CPU and Instruction Set
      1. 8.2.1 Overview
      2. 8.2.2 Features
      3. 8.2.3 Block Diagram
      4. 8.2.4 Architecture
        1. 8.2.4.1  Interface Description
          1. 8.2.4.1.1 Data Memory Interface
          2. 8.2.4.1.2 Instruction Memory Interface
        2. 8.2.4.2  Pipeline
          1. 8.2.4.2.1 Overview
          2. 8.2.4.2.2 Pipeline Operation
            1. 8.2.4.2.2.1 ARP32 CPU Pipeline Operation
            2. 8.2.4.2.2.2 1129
          3. 8.2.4.2.3 Pipeline Interlocks
        3. 8.2.4.3  Data Format
        4. 8.2.4.4  Endian Support
        5. 8.2.4.5  Architectural Register File
        6. 8.2.4.6  CPU Control Registers
          1. 8.2.4.6.1  Control Status Register (CSR)
          2. 8.2.4.6.2  Interrupt Enable Register (IER)
          3. 8.2.4.6.3  Interrupt Flag Register (IFR)
          4. 8.2.4.6.4  Interrupt Set Register (ISR)
          5. 8.2.4.6.5  Interrupt Clear Register (ICR)
          6. 8.2.4.6.6  Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
          7. 8.2.4.6.7  Interrupt Return Pointer Register (IRP)
          8. 8.2.4.6.8  Stack Pointer Register (SP)
          9. 8.2.4.6.9  Global Data Pointer Register (GDP)
          10. 8.2.4.6.10 Link Register (LR)
          11. 8.2.4.6.11 Loop 0 Start Address Register (LSA0)
          12. 8.2.4.6.12 Loop 0 End Address Register (LEA0)
          13. 8.2.4.6.13 Loop 0 Iteration Count Register (LCNT0)
          14. 8.2.4.6.14 Loop 1 Start Address Register (LSA1)
          15. 8.2.4.6.15 Loop 1 End Address Register (LEA1)
          16. 8.2.4.6.16 Loop 1 Iteration Count Register (LCNT1)
          17. 8.2.4.6.17 Loop 0 Iteration Count Reload Value Register (LCNT0RLD)
          18. 8.2.4.6.18 Shadow Control Status Register (SCSR)
          19. 8.2.4.6.19 NMI Shadow Control Status Register (NMISCSR)
          20. 8.2.4.6.20 CPU Identification Register (CPUID)
          21. 8.2.4.6.21 Decode Program Counter Register (DPC)
          22. 8.2.4.6.22 Time Stamp Counter Registers (TSCL and TSCH)
            1. 8.2.4.6.22.1 Initialization
            2. 8.2.4.6.22.2 Enabling Counting
            3. 8.2.4.6.22.3 Disabling Counting
            4. 8.2.4.6.22.4 Reading the Counter
        7. 8.2.4.7  CPU Shadow Registers
        8. 8.2.4.8  Functional Units
        9. 8.2.4.9  Instruction Fetch
        10. 8.2.4.10 Alignment of 32-bit Instructions
        11. 8.2.4.11 Instruction Execution in Branch Delay Slot
        12. 8.2.4.12 Address Space
        13. 8.2.4.13 Program Counter Convention
        14. 8.2.4.14 Stack Pointer Convention
        15. 8.2.4.15 Global Data Pointer Convention
        16. 8.2.4.16 Conditional Execution
        17. 8.2.4.17 Hardware Loop Acceleration
          1. 8.2.4.17.1  Overview
          2. 8.2.4.17.2  Loop Registers
          3. 8.2.4.17.3  Loop Setup Instructions
          4. 8.2.4.17.4  Loop Operation
          5. 8.2.4.17.5  Call and Branch within Loop Context
          6. 8.2.4.17.6  Dynamic Changes to Loop Iteration Count
          7. 8.2.4.17.7  Interrupt Processing During HLA
          8. 8.2.4.17.8  HLA Usage in Interrupt Context
          9. 8.2.4.17.9  HLA Usage Restrictions
          10. 8.2.4.17.10 HLA Mapping Examples
            1. 8.2.4.17.10.1 Loops With Single Level of Nesting
              1. 8.2.4.17.10.1.1 C memset-like Loop, Single Level, Minimum Instructions
              2. 8.2.4.17.10.1.2 1184
              3. 8.2.4.17.10.1.3 C memcpy-like Loop, Single Level, Minimum Instructions
              4. 8.2.4.17.10.1.4 1186
            2. 8.2.4.17.10.2 Loops With Two Levels of Nesting
              1. 8.2.4.17.10.2.1 Two-level Nesting, Both Loops Ending at Same Instruction
              2. 8.2.4.17.10.2.2 1189
              3. 8.2.4.17.10.2.3 Two-level Nesting, Different Ending Instructions for Two Levels
              4. 8.2.4.17.10.2.4 1191
        18. 8.2.4.18 Interrupts
          1. 8.2.4.18.1  Overview
          2. 8.2.4.18.2  Interrupt Processing
          3. 8.2.4.18.3  Interrupt Acknowledgment
          4. 8.2.4.18.4  Interrupt Priorities
          5. 8.2.4.18.5  Interrupt Service Table (IST)
          6. 8.2.4.18.6  Interrupt Flags
            1. 8.2.4.18.6.1 Setting Interrupt Flag
            2. 8.2.4.18.6.2 Setting Interrupt Flag
            3. 8.2.4.18.6.3 1201
          7. 8.2.4.18.7  Interrupt Behavior
            1. 8.2.4.18.7.1 Reset Interrupt
            2. 8.2.4.18.7.2 Non-maskable Interrupt (NMI)
            3. 8.2.4.18.7.3 SWI Interrupt
            4. 8.2.4.18.7.4 Maskable Interrupts
            5. 8.2.4.18.7.5 UNDEF Interrupt
          8. 8.2.4.18.8  Interrupt Context Save and Restore
          9. 8.2.4.18.9  Nested Interrupts
            1. 8.2.4.18.9.1 Non-nested Interrupt Model
            2. 8.2.4.18.9.2 Nested Interrupt Model
          10. 8.2.4.18.10 Non-nested Interrupt Latency
            1. 8.2.4.18.10.1 Best Case Interrupt Latency
            2. 8.2.4.18.10.2 Worst Case Interrupt Latency
      5.      8.2.A Instruction Set
        1.       8.2.A.1 Instruction Operation and Execution Notations
        2.       8.2.A.2 Instruction Syntax and Opcode Notations
        3.       8.2.A.3 Instruction Scheduling Restrictions
          1.        8.2.A.3.1 Restrictions Applicable to a Branch Delay Slot
          2.        8.2.A.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA)
          3.        8.2.A.3.3 Restrictions on Other Types of Control Flow Instructions
          4.        8.2.A.3.4 Restrictions for Write Data Bypass to Control Register Reads
          5.        8.2.A.3.5 Restrictions for Write Data Bypass to Shadow Register Reads
          6.        8.2.A.3.6 Restrictions for Link Register Update
        4.       8.2.A.4 Instruction Set Encoding
        5.       8.2.A.5 Instruction Descriptions
          1.        ABS
          2.        ADD
          3.        ADD
          4.        ADD
          5.        ADD
          6.        ADD
          7.        AND
          8.        AND
          9.        B(cc)
          10.        B(cc)
          11.        B(cc)
          12.        BIRP
          13.        BKPT
          14.        BNRP
          15.        CALL
          16.        CALL
          17.        CLR
          18.        CLR
          19.        CMP
          20.        CMP
          21.        CMP
          22.        CMPU
          23.        CMPU
          24.        CMPU
          25.        DIV
          26.        DIVU
          27.        EXT
          28.        EXT
          29.        EXTU
          30.        EXTU
          31.        IDLE
          32.        LDB(U)
          33.        LDB(U)
          34.        LDB(U)
          35.        LDB(U)
          36.        LDB(U)
          37.        LDB(U)
          38.        LDB(U)
          39.        LDB(U)
          40.        LDH(U)
          41.        LDH(U)
          42.        LDH(U)
          43.        LDH(U)
          44.        LDH(U)
          45.        LDH(U)
          46.        LDH(U)
          47.        LDH(U)
          48.        LDW
          49.        LDW
          50.        LDW
          51.        LDW
          52.        LDW
          53.        LDW
          54.        LDW
          55.        LDW
          56.        LDRF
          57.        LMBD
          58.        MAX
          59.        MAXU
          60.        MIN
          61.        MINU
          62.        MOD
          63.        MODU
          64.        MPY
          65.        MPYU
          66.        MV
          67.        MVC
          68.        MVC
          69.        MVC
          70.        MVCH
          71.        MVK
          72.        MVKH
          73.        MVKLS
          74.        MVKS
          75.        MVS
          76.        MVS
          77.        NEG
          78.        NOP
          79.        NOT
          80.        OR
          81.        OR
          82.        RET
          83.        REV
          84.        ROT
          85.        ROTC
          86.        SADD
          87.        SATN
          88.        SET
          89.        SET
          90.        SHL
          91.        SHL
          92.        SHRA
          93.        SHRA
          94.        SHRU
          95.        SHRU
          96.        SLA
          97.        SSUB
          98.        STB
          99.        STB
          100.        STB
          101.        STB
          102.        STB
          103.        STB
          104.        STB
          105.        STB
          106.        STH
          107.        STH
          108.        STH
          109.        STH
          110.        STH
          111.        STH
          112.        STH
          113.        STH
          114.        STW
          115.        STW
          116.        STW
          117.        STW
          118.        STW
          119.        STW
          120.        STW
          121.        STW
          122.        STHI
          123.        STRF
          124.        SUB
          125.        SUB
          126.        SUB
          127.        SUB
          128.        SUB
          129.        SWI
          130.        XOR
          131.        XOR
      6.      8.2.B Clock, Reset, and Dynamic Power Management
        1.       8.2.B.1 Introduction
        2.       8.2.B.2 CPU Reset Modes
        3.       8.2.B.3 Dynamic Power Management
      7.      8.2.C Notes on Programming Model
        1.       8.2.C.1 Booting
        2.       8.2.C.2 Enabling and Disabling Interrupts
          1.        8.2.C.2.1 Globally Enabling or Disabling Maskable Interrupts
          2.        8.2.C.2.2 Enabling or Disabling Individual Interrupts
        3.       8.2.C.3 Stack Usage in Interrupt Service Routine
        4.       8.2.C.4 General Restrictions
    3. 8.3 VCOP CPU and Instruction Set
      1. 8.3.1 Module Overview
      2. 8.3.2 Features
      3. 8.3.3 Block Diagram
      4. 8.3.4 System Interfaces
        1. 8.3.4.1 Interrupts
        2. 8.3.4.2 Configuration Bus Slave Port
        3. 8.3.4.3 Performance Counter Interface
        4. 8.3.4.4 Data Memory Map
      5. 8.3.5 Functional Description
        1. 8.3.5.1 Scalar-Vector Architecture
          1. 8.3.5.1.1 Scalar Core
          2. 8.3.5.1.2 Scalar-Vector Interaction
        2. 8.3.5.2 Vector Core Overview
          1. 8.3.5.2.1 Nested for Loop Model
            1. 8.3.5.2.1.1 Nested Loop Model Skeleton
            2. 8.3.5.2.1.2 1385
          2. 8.3.5.2.2 Instruction Organization
        3. 8.3.5.3 Vector Control
          1. 8.3.5.3.1 Repeat End Count
          2. 8.3.5.3.2 Parameter Pointer
          3. 8.3.5.3.3 Switch Buffers
        4. 8.3.5.4 Vector-Scalar Synchronization
          1. 8.3.5.4.1 Wait for Vector Core Done
          2. 8.3.5.4.2 Wait for Vector Core Ready
        5. 8.3.5.5 Vector Computation
          1. 8.3.5.5.1  Vector Loop
            1. 8.3.5.5.1.1 Retention of State Between VLOOPs
          2. 8.3.5.5.2  Vector Register Initialization
          3. 8.3.5.5.3  Address Generator (agen)
          4. 8.3.5.5.4  Vector Load
          5. 8.3.5.5.5  Vector Arithmetic/Logic Operations
          6. 8.3.5.5.6  Vector Store
          7. 8.3.5.5.7  Table Lookup Operation
          8. 8.3.5.5.8  Histogram Operation
          9. 8.3.5.5.9  Circular Buffer Addressing Support
          10. 8.3.5.5.10 Load/Store Address Alignment Constraints
        6. 8.3.5.6 Load/Store Buffer and Scheduling
          1. 8.3.5.6.1 3-Tap Horizontal Filtering, Byte Type
          2. 8.3.5.6.2 1408
          3. 8.3.5.6.3 Horizontal Filtering, Short Type
          4. 8.3.5.6.4 1410
        7. 8.3.5.7 VCOP Per-Loop Overhead
        8. 8.3.5.8 VCOP Error Handling
        9. 8.3.5.9 Vector Operation Details
          1. 8.3.5.9.1  VABS
          2. 8.3.5.9.2  VABSDIF
          3. 8.3.5.9.3  VADD
          4. 8.3.5.9.4  VADDH
          5. 8.3.5.9.5  VADDSUB
          6. 8.3.5.9.6  VADD3
          7. 8.3.5.9.7  VADIF3
          8. 8.3.5.9.8  VAND
          9. 8.3.5.9.9  VANDN
          10. 8.3.5.9.10 VAND3
          11. 8.3.5.9.11 VBINLOG
          12. 8.3.5.9.12 VBITC
          13. 8.3.5.9.13 VBITDI
          14. 8.3.5.9.14 VBITI
          15. 8.3.5.9.15 VBITPK
          16. 8.3.5.9.16 VBITR
          17. 8.3.5.9.17 VBITTR
          18. 8.3.5.9.18 VBITUNPK
          19. 8.3.5.9.19 VCMOV
          20. 8.3.5.9.20 VCMPEQ
          21. 8.3.5.9.21 VCMPGE
          22. 8.3.5.9.22 VCMPGT
          23. 8.3.5.9.23 VDINTRLV
          24. 8.3.5.9.24 VDINTRLV2
          25. 8.3.5.9.25 VEXITNZ
          26. 8.3.5.9.26 VINTRLV
          27. 8.3.5.9.27 VINTRLV2
          28. 8.3.5.9.28 VINTRLV4
          29. 8.3.5.9.29 VLMBD
          30. 8.3.5.9.30 VMADD
          31. 8.3.5.9.31 VMAX
          32. 8.3.5.9.32 VMAXSETF
          33. 8.3.5.9.33 VMIN
          34. 8.3.5.9.34 VMINSETF
          35. 8.3.5.9.35 VMPY
          36. 8.3.5.9.36 VMSUB
          37. 8.3.5.9.37 VNOP
          38. 8.3.5.9.38 VNOT
          39. 8.3.5.9.39 VOR
          40. 8.3.5.9.40 VOR3
          41. 8.3.5.9.41 VRND
          42. 8.3.5.9.42 VSAD
          43. 8.3.5.9.43 VSEL
          44. 8.3.5.9.44 VSHF
          45. 8.3.5.9.45 VSHFOR
          46. 8.3.5.9.46 VSHF16
          47. 8.3.5.9.47 VSIGN
          48. 8.3.5.9.48 VSORT2
          49. 8.3.5.9.49 VSUB
          50. 8.3.5.9.50 VSWAP
          51. 8.3.5.9.51 VXOR
      6. 8.3.6 Debug Support
      7. 8.3.7 VCOP Register Manual
        1. 8.3.7.1 VCOP Instance Summary
        2. 8.3.7.2 VCOP Registers
          1. 8.3.7.2.1 VCOP Registers Mapping Summary
          2. 8.3.7.2.2 VCOP Register Description
  11. 9 Imaging Subsystem
    1. 9.1 ISS Overview
      1. 9.1.1 ISS Integration
        1. 9.1.1.1 ISS PRCM Interface Integration
          1. 9.1.1.1.1 ISS Clock Domains
      2. 9.1.2 ISS Functional Description
        1. 9.1.2.1 ISS Interrupts
          1. 9.1.2.1.1 ISS Interrupt Merger
          2. 9.1.2.1.2 ISS Submodule Interrupts
            1. 9.1.2.1.2.1 ISS ISP Interrupts
            2. 9.1.2.1.2.2 ISS CAL_B Interrupts
            3. 9.1.2.1.2.3 ISS SIMCOP Interrupts
        2. 9.1.2.2 ISS Interconnect
        3. 9.1.2.3 ISS Video Mux
        4. 9.1.2.4 ISS Clocks
        5. 9.1.2.5 ISS Reset
        6. 9.1.2.6 ISS Power Management
          1. 9.1.2.6.1 ISS Power-Management Infrastructure Overview
          2. 9.1.2.6.2 ISS STANDBY Mechanism
          3. 9.1.2.6.3 ISS IDLE Mechanism
        7. 9.1.2.7 ISS CAL Usage Considerations
          1. 9.1.2.7.1 CAL Usage as Memory to Memory Pixel DMA
          2. 9.1.2.7.2 CAL Usage with GLBCE
      3. 9.1.3 ISS Register Manual
        1. 9.1.3.1 ISS Instance Summary
        2. 9.1.3.2 ISS Registers
          1. 9.1.3.2.1 ISS TOP Register Summary
          2. 9.1.3.2.2 ISS TOP Register Description
    2. 9.2 ISS Camera Adapter Layer (CAL)
      1. 9.2.1 ISS CAL Features
      2. 9.2.2 ISS CAL Integration
        1. 9.2.2.1 CAL Main Integration Attributes
        2. 9.2.2.2 CAL Integration - Video Port
        3. 9.2.2.3 CAL Integration - BYS Ports
      3. 9.2.3 ISS CAL Functional Description
        1. 9.2.3.1  CAL Block Diagram
        2. 9.2.3.2  CAL Hardware and Software Reset
        3. 9.2.3.3  CAL Clock Configuration
        4. 9.2.3.4  CAL Power Management
        5. 9.2.3.5  CAL Interrupt Events
        6. 9.2.3.6  CAL Data Stream
        7. 9.2.3.7  CAL Pixel Extraction
        8. 9.2.3.8  CAL DPCM Decoding and Encoding
          1. 9.2.3.8.1 CAL Partial DPCM Decompression
        9. 9.2.3.9  CAL Pixel Packing
        10. 9.2.3.10 CAL Write DMA
          1. 9.2.3.10.1 CAL Write DMA Overview
          2. 9.2.3.10.2 CAL Write DMA Data Cropping
          3. 9.2.3.10.3 CAL Write DMA Buffer Management
          4. 9.2.3.10.4 CAL Write DMA OCP Address Generation
            1. 9.2.3.10.4.1 Write DMA Buffer Base Address
            2. 9.2.3.10.4.2 Write DMA Line Start Address
            3. 9.2.3.10.4.3 Write DMA Data Address
          5. 9.2.3.10.5 CAL Write DMA OCP Transaction Generation
          6. 9.2.3.10.6 CAL Write DMA Real Time Traffic
        11. 9.2.3.11 CAL Read DMA
          1. 9.2.3.11.1 CAL Read DMA Overview
          2. 9.2.3.11.2 CAL Read DMA Data Provided to Processing Pipeline
          3. 9.2.3.11.3 CAL Read DMA Skipping Modes
          4. 9.2.3.11.4 CAL Read DMA YUV420 Support
          5. 9.2.3.11.5 CAL Read DMA OCP Request Generation
        12. 9.2.3.12 CAL Video Port
          1. 9.2.3.12.1 CAL Video Port Overview
          2. 9.2.3.12.2 CAL Video Port Pixel Clock Generation
          3. 9.2.3.12.3 CAL Video Port Video Timing Generator
        13. 9.2.3.13 CAL BYS Ports
          1. 9.2.3.13.1 CAL BYS Ports Overview
          2. 9.2.3.13.2 CAL BYS Output Port
          3. 9.2.3.13.3 BYS Input Port
        14. 9.2.3.14 CAL Registers Shadowing
      4. 9.2.4 ISS CAL Register Manual
        1. 9.2.4.1 CAL Instance Summary
        2. 9.2.4.2 CAL Registers
          1. 9.2.4.2.1 CAL Register Summary
          2. 9.2.4.2.2 CAL Register Description
    3. 9.3 ISS Image Signal Processor (ISP)
      1. 9.3.1 ISS ISP Overview
        1. 9.3.1.1 ISS ISP Features
        2. 9.3.1.2 ISS ISP Block Diagram
      2. 9.3.2 ISS ISP Integration
        1. 9.3.2.1 ISS ISP PRCM Interface
          1. 9.3.2.1.1 ISS ISP Clocks
          2. 9.3.2.1.2 ISS ISP Reset
        2. 9.3.2.2 ISS ISP Interrupt Tree
        3. 9.3.2.3 ISS ISP IPIPEIF Integration
          1. 9.3.2.3.1 ISS ISP IPIPEIF Interrupts
        4. 9.3.2.4 ISS ISP IPIPE Integration
          1. 9.3.2.4.1 ISS ISP IPIPE Interrupts
        5. 9.3.2.5 ISS ISP RSZ Integration
          1. 9.3.2.5.1 ISS ISP RSZ PRCM Interface
            1. 9.3.2.5.1.1 ISS ISP RSZ Reset
          2. 9.3.2.5.2 ISS ISP RSZ Interrupts
        6. 9.3.2.6 ISS ISP H3A Integration
          1. 9.3.2.6.1 ISS ISP H3A Interrupts
        7. 9.3.2.7 ISS ISP ISIF Integration
          1. 9.3.2.7.1 ISS ISP ISIF Interrupts
        8. 9.3.2.8 ISS ISP BL Integration
      3. 9.3.3 ISS ISP Functional Description
        1. 9.3.3.1  ISS ISP VP Functional Description
          1. 9.3.3.1.1 ISS ISP VP Overview
          2. 9.3.3.1.2 ISS ISP VP Data Formats
          3. 9.3.3.1.3 ISS ISP VP Top-Level Communication With CAL_B
          4. 9.3.3.1.4 ISS ISP VP Pixel Clock Inversion
        2. 9.3.3.2  ISS ISP GLBCE Functional Description
          1. 9.3.3.2.1 ISS ISP GLBCE Overview
          2. 9.3.3.2.2 ISS ISP GLBCE Interface
          3. 9.3.3.2.3 ISS ISP GLBCE Core
            1. 9.3.3.2.3.1 ISS ISP GLBCE Core Key Parameters
            2. 9.3.3.2.3.2 ISS ISP GLBCE Iridix Strength Calculation
            3. 9.3.3.2.3.3 ISS ISP GLBCE Iridix Configuration Registers
              1. 9.3.3.2.3.3.1  ISS ISP GLBCE Iridix Frame Width
              2. 9.3.3.2.3.3.2  ISS ISP GLBCE Iridix Frame Height
              3. 9.3.3.2.3.3.3  ISS ISP GLBCE Iridix Control
              4. 9.3.3.2.3.3.4  ISS ISP GLBCE Iridix Control
              5. 9.3.3.2.3.3.5  ISS ISP GLBCE Iridix Strength
              6. 9.3.3.2.3.3.6  ISS ISP GLBCE Iridix Variance
              7. 9.3.3.2.3.3.7  ISS ISP GLBCE Iridix Dither
              8. 9.3.3.2.3.3.8  ISS ISP GLBCE Iridix Amplification Limit
              9. 9.3.3.2.3.3.9  ISS ISP GLBCE Iridix Slope Min and Max
              10. 9.3.3.2.3.3.10 ISS ISP GLBCE Iridix Black Level
              11. 9.3.3.2.3.3.11 ISS ISP GLBCE Iridix White Level
              12. 9.3.3.2.3.3.12 ISS ISP GLBCE Iridix Asymmetry Function Look-up-table
              13. 9.3.3.2.3.3.13 ISS ISP GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
              14. 9.3.3.2.3.3.14 ISS ISP GLBCE Iridix Tile Position and Size
              15. 9.3.3.2.3.3.15 ISS ISP GLBCE Iridix WDR Look-up-table
          4. 9.3.3.2.4 ISS ISP GLBCE Embedded Memory
          5. 9.3.3.2.5 ISS ISP GLBCE Programming Model
            1. 9.3.3.2.5.1 ISS ISP GLBCE Restriction
              1. 9.3.3.2.5.1.1 ISS ISP GLBCE Recovery from Reset
              2. 9.3.3.2.5.1.2 General description of GLBCE processing
              3. 9.3.3.2.5.1.3 Continuous Frame Processing
              4. 9.3.3.2.5.1.4 Single Image Processing
        3. 9.3.3.3  ISS ISP NSF3V Functional Description
          1. 9.3.3.3.1 ISS ISP NSF3V Overview
          2. 9.3.3.3.2 ISS ISP NSF3V Register Shadowing
          3. 9.3.3.3.3 ISS ISP NSF3V Programming Model
            1. 9.3.3.3.3.1 ISS ISP NSF3V Initialization
        4. 9.3.3.4  ISS ISP IPIPEIF Functional Description
          1. 9.3.3.4.1  ISS ISP IPIPEIF Overview
          2. 9.3.3.4.2  ISS ISP IPIPEIF Top-Level Block Diagram
          3. 9.3.3.4.3  ISS ISP IPIPEIF Input Interface
            1. 9.3.3.4.3.1 ISS ISP IPIPEIF Input From VP
            2. 9.3.3.4.3.2 ISS ISP IPIPEIF Input From BL
              1. 9.3.3.4.3.2.1 ISS ISP IPIPEIF Double-Buffer Input Function When Reading From BL
          4. 9.3.3.4.4  ISS ISP IPIPEIF Data Path Selection
            1. 9.3.3.4.4.1 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0
            2. 9.3.3.4.4.2 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1
            3. 9.3.3.4.4.3 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2
            4. 9.3.3.4.4.4 ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3
            5. 9.3.3.4.4.5 ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0
            6. 9.3.3.4.4.6 ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0
            7. 9.3.3.4.4.7 ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0
          5. 9.3.3.4.5  ISS ISP IPIPEIF Timing Generation
            1. 9.3.3.4.5.1 ISS ISP IPIPEIF Fractional Clock Divider
          6. 9.3.3.4.6  ISS ISP IPIPEIF Decompression (DPCM) Subblock: Unpack and Decompression Function
          7. 9.3.3.4.7  ISS ISP IPIPEIF Dark-Frame Subtraction Functionality
            1. 9.3.3.4.7.1 ISS ISP IPIPEIF Defect Pixel Correction
            2. 9.3.3.4.7.2 ISS ISP IPIPEIF DFS Subtraction Direction
          8. 9.3.3.4.8  ISS ISP IPIPEIF Wide Dynamic Range WDR Merging Functionality
            1. 9.3.3.4.8.1 ISS ISP IPIPEIF merging general description
          9. 9.3.3.4.9  ISS ISP IPIPEIF (1, 2, 1) Averaging Filter for IPIPE Data Path
          10. 9.3.3.4.10 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for IPIPE Data Path
          11. 9.3.3.4.11 ISS ISP IPIPEIF RAW Data Gain for IPIPE Data Path
          12. 9.3.3.4.12 ISS ISP IPIPEIF (1, 2 ,1) Averaging Filter for H3A Data Path
          13. 9.3.3.4.13 ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for H3A Data Path
          14. 9.3.3.4.14 ISS ISP IPIPEIF YUV4:2:2 8-bit Packed Data Input Coming From ISIF Module
          15. 9.3.3.4.15 ISS ISP IPIPEIF YUV4:2:0 Data Input for Memory-to-Memory Resize Operations
          16. 9.3.3.4.16 ISS ISP IPIPEIF Module Events and Status Checking
        5. 9.3.3.5  ISS ISP IPIPE Functional Description
          1. 9.3.3.5.1  ISS ISP IPIPE Overview
          2. 9.3.3.5.2  ISS ISP IPIPE Top-Level Block Diagram
          3. 9.3.3.5.3  ISS ISP IPIPE Input Interface
          4. 9.3.3.5.4  ISS ISP IPIPE Defect Pixel Correction
            1. 9.3.3.5.4.1 ISS ISP IPIPE LUT Defect Pixel Correction (LUT DPC)
          5. 9.3.3.5.5  ISS ISP IPIPE DPC Interface
          6. 9.3.3.5.6  ISS ISP IPIPE White Balance
          7. 9.3.3.5.7  ISS ISP IPIPE YUV422to444
          8. 9.3.3.5.8  ISS ISP IPIPE RGB2RGB Blending Module
          9. 9.3.3.5.9  ISS ISP IPIPE Gamma Correction Module
          10. 9.3.3.5.10 ISS ISP IPIPE Second RGB2RGB Conversion Matrix
          11. 9.3.3.5.11 ISS ISP IPIPE RGB2YCbCr Conversion Matrix
          12. 9.3.3.5.12 ISS ISP IPIPE 4:2:2 Conversion Module
          13. 9.3.3.5.13 ISS ISP IPIPE 2D Edge-Enhancer
          14. 9.3.3.5.14 ISS ISP IPIPE Histogram
          15. 9.3.3.5.15 ISS ISP IPIPE Boxcar
        6. 9.3.3.6  ISS ISP RSZ Functional Description
          1. 9.3.3.6.1 ISS ISP RSZ Overview
          2. 9.3.3.6.2 ISS ISP RSZ Top-Level Block Diagram
          3. 9.3.3.6.3 ISS ISP RSZ Interfaces
            1. 9.3.3.6.3.1 ISS ISP RSZ VBUSP Interface
            2. 9.3.3.6.3.2 ISS ISP RSZ Video Port Interfaces
            3. 9.3.3.6.3.3 ISS ISP RSZ MTC Interfaces
            4. 9.3.3.6.3.4 ISS ISP RSZ CNF Interface
          4. 9.3.3.6.4 ISS ISP RSZ ICM Handshake Signals
          5. 9.3.3.6.5 ISS ISP RSZ Integration
          6. 9.3.3.6.6 ISS ISP RSZ Functional Description
            1. 9.3.3.6.6.1 ISS ISP RSZ Operating Modes
              1. 9.3.3.6.6.1.1 ISS ISP RSZ Operating Modes and Maximum Input Clock
            2. 9.3.3.6.6.2 ISS ISP RSZ Input Data Cropper
            3. 9.3.3.6.6.3 ISS ISP RSZ Averager
              1. 9.3.3.6.6.3.1 ISS ISP RSZ Use Cases
              2. 9.3.3.6.6.3.2 ISS ISP RSZ Memory Use
              3. 9.3.3.6.6.3.3 ISS ISP RSZ Border Conditions
            4. 9.3.3.6.6.4 ISS ISP RSZ Interpolation
              1. 9.3.3.6.6.4.1 ISS ISP RSZ Liner Interpolation Input Data
                1. 9.3.3.6.6.4.1.1 ISS ISP RSZ Cubic Convolution Mode
                2. 9.3.3.6.6.4.1.2 ISS ISP RSZ Phase Settings
            5. 9.3.3.6.6.5 ISS ISP RSZ Data Saturator
            6. 9.3.3.6.6.6 ISS ISP RSZ Color Converter
            7. 9.3.3.6.6.7 ISS ISP RSZ Output Interface
              1. 9.3.3.6.6.7.1 ISS ISP RSZ Circular Buffer
        7. 9.3.3.7  ISS ISP CNF Functional Description
          1. 9.3.3.7.1 ISS ISP CNF Overview
          2. 9.3.3.7.2 ISS ISP CNF Top Level Block Diagram
          3. 9.3.3.7.3 ISS ISP CNF Noise Filter Algorithm
          4. 9.3.3.7.4 ISS ISP CNF Chroma Downsampling and Upsampling
          5. 9.3.3.7.5 ISS ISP CNF Vertical and Horizontal Blanking
          6. 9.3.3.7.6 ISS ISP CNF configuring ranges/restrictions
        8. 9.3.3.8  ISS ISP H3A Functional Description
          1. 9.3.3.8.1 ISS ISP H3A Overview
          2. 9.3.3.8.2 ISS ISP H3A Top-Level Block Diagram
          3. 9.3.3.8.3 ISS ISP H3A Line Framing Logic
          4. 9.3.3.8.4 ISS ISP H3A Optional Preprocessing
          5. 9.3.3.8.5 ISS ISP H3A Autofocus Engine
            1. 9.3.3.8.5.1 ISS ISP H3A Paxel Extraction
            2. 9.3.3.8.5.2 ISS ISP H3A Horizontal FV Calculator
            3. 9.3.3.8.5.3 ISS ISP H3A HFV Accumulator
            4. 9.3.3.8.5.4 ISS ISP H3A VFV Calculator
            5. 9.3.3.8.5.5 ISS ISP H3A VFV Accumulator
          6. 9.3.3.8.6 ISS ISP H3A AE/AWB Engine
            1. 9.3.3.8.6.1 ISS ISP H3A Subsampler
            2. 9.3.3.8.6.2 ISS ISP H3A Additional Black Row of AE/AWB Windows
            3. 9.3.3.8.6.3 ISS ISP H3A Saturation Check
            4. 9.3.3.8.6.4 ISS ISP H3A AE/AWB Accumulators
          7. 9.3.3.8.7 ISS ISP H3A DMA Interface
          8. 9.3.3.8.8 ISS ISP H3A Events and Status Checking
        9. 9.3.3.9  ISS ISP ISIF Functional Description
          1. 9.3.3.9.1  ISS ISP ISIF Overview
          2. 9.3.3.9.2  ISS ISP ISIF Top-Level Block Diagram
          3. 9.3.3.9.3  ISS ISP ISIF Input Interface
          4. 9.3.3.9.4  ISS ISP ISIF Interface
          5. 9.3.3.9.5  ISS ISP ISIF Sensor Linearization
          6. 9.3.3.9.6  ISS ISP ISIF Input Data Formatter
            1. 9.3.3.9.6.1 1714
            2. 9.3.3.9.6.2 ISS ISP ISIF Formatter Area Settings
            3. 9.3.3.9.6.3 ISS ISP ISIF Formatter Programming
            4. 9.3.3.9.6.4 ISS ISP ISIF Combine the Divided Input Lines
          7. 9.3.3.9.7  ISS ISP ISIF Color Space Converter
          8. 9.3.3.9.8  ISS ISP ISIF Black Clamp
            1. 9.3.3.9.8.1 ISS ISP ISIF Clamp Value for Horizontal Direction
            2. 9.3.3.9.8.2 ISS ISP ISIF Clamp Value for Vertical Direction
          9. 9.3.3.9.9  ISS ISP ISIF Vertical Line Defect Correction (VDFC)
            1. 9.3.3.9.9.1 ISS ISP ISIF Vertical Line Defect Table Update Procedure
          10. 9.3.3.9.10 ISS ISP ISIF Lens Shading Correction Module (2D-LSC)
            1. 9.3.3.9.10.1 ISS ISP ISIF 2D-LSC Active Region Settings
              1. 9.3.3.9.10.1.1 ISS ISP ISIF 2D-LSC Gain and Offset Tables
              2. 9.3.3.9.10.1.2 ISS ISP ISIF 2D-LSC Gain and Offset Table Upsampling
              3. 9.3.3.9.10.1.3 ISS ISP ISIF Application of Gain and Offset to Image Pixels
              4. 9.3.3.9.10.1.4 ISS ISP ISIF Enabling and Disabling the 2D-LSC Module
              5. 9.3.3.9.10.1.5 ISS ISP ISIF 2D-LSC Events and Status Checking
              6. 9.3.3.9.10.1.6 ISS ISP ISIF Supported On-the-Fly 2D-LSC Configurations
              7. 9.3.3.9.10.1.7 ISS ISP ISIF Bandwidth Requirements on BL Read Port
          11. 9.3.3.9.11 ISS ISP ISIF White Balance
          12. 9.3.3.9.12 ISS ISP ISIF Low-Pass Filter
          13. 9.3.3.9.13 ISS ISP ISIF A-Law Compression
          14. 9.3.3.9.14 ISS ISP ISIF Culling
          15. 9.3.3.9.15 ISS ISP ISIF 12-to-8-Bit DPCM Compression Block
          16. 9.3.3.9.16 ISP ISIF Storage Formatter
          17. 9.3.3.9.17 ISS ISP ISIF Circular Buffer
          18. 9.3.3.9.18 ISS ISP ISIF YCbCr Signal Processing
          19. 9.3.3.9.19 ISS ISP ISIF Expected Bandwidth on BL Ports
            1. 9.3.3.9.19.1 ISS ISP ISIF Write Port
            2. 9.3.3.9.19.2 ISS ISP ISIF Read Port
          20. 9.3.3.9.20 ISS ISP ISIF Events and Status Checking
            1. 9.3.3.9.20.1 ISS ISP ISIF VDINT0, VDINT1, and VDINT2 Interrupts
            2. 9.3.3.9.20.2 ISS ISP ISIF 2DLSCINT Interrupt
            3. 9.3.3.9.20.3 ISS ISP ISIF Status Checking
        10. 9.3.3.10 ISS ISP BL Functional Description
          1. 9.3.3.10.1 ISS ISP BL Overview
          2. 9.3.3.10.2 ISS ISP BL Functional Description
          3. 9.3.3.10.3 ISS ISP BL Address Alignment
          4. 9.3.3.10.4 ISS ISP BL Out-of-Order Responses
          5. 9.3.3.10.5 ISS ISP BL Stalling
            1. 9.3.3.10.5.1 ISS ISP BL Stalling Write Requests
            2. 9.3.3.10.5.2 ISS ISP BL Stalling Read Requests
          6. 9.3.3.10.6 ISS ISP BL Dynamic and Static MFlag Generation
          7. 9.3.3.10.7 ISS ISP BL VBUSM2OCP Last Beat Command Delay
          8. 9.3.3.10.8 ISS ISP BL Peak Memory Bandwidth Reduction
        11. 9.3.3.11 ISS ISP Memory Mapping
      4. 9.3.4 ISS ISP Register Manual
        1. 9.3.4.1  ISS ISP Instance Summary
        2. 9.3.4.2  ISS ISP6P5_SYS1 Registers
          1. 9.3.4.2.1 ISS ISP6P5_SYS1 Register Summary
          2. 9.3.4.2.2 ISS ISP6P5_SYS1 Register Description
        3. 9.3.4.3  ISS ISP6P5_SYS2 Registers
          1. 9.3.4.3.1 ISS ISP6P5_SYS2 Register Summary
          2. 9.3.4.3.2 ISS ISP6P5_SYS2 Register Description
        4. 9.3.4.4  ISS ISP6P5_RESIZER Registers
          1. 9.3.4.4.1 ISS ISP6P5_RESIZER Register Summary
          2. 9.3.4.4.2 ISS ISP6P5_RESIZER Register Description
        5. 9.3.4.5  ISS ISP6P5_IPIPE Registers
          1. 9.3.4.5.1 ISS ISP6P5_IPIPE Register Summary
          2. 9.3.4.5.2 ISS ISP6P5_IPIPE Register Description
        6. 9.3.4.6  ISS ISP6P5_ISIF Registers
          1. 9.3.4.6.1 ISS ISP6P5_ISIF Register Summary
          2. 9.3.4.6.2 ISS ISP6P5_ISIF Register Description
        7. 9.3.4.7  ISS ISP6P5_IPIPEIF Registers
          1. 9.3.4.7.1 ISS ISP6P5_IPIPEIF Register Summary
          2. 9.3.4.7.2 ISS ISP6P5_IPIPEIF Register Description
        8. 9.3.4.8  ISS ISP6P5_H3A Registers
          1. 9.3.4.8.1 ISS ISP6P5_H3A Register Summary
          2. 9.3.4.8.2 ISS ISP6P5_H3A Register Description
        9. 9.3.4.9  ISS ISP6P5_SYS3 Registers
          1. 9.3.4.9.1 ISS ISP6P5_SYS3 Register Summary
          2. 9.3.4.9.2 ISS ISP6P5_SYS3 Register Description
        10. 9.3.4.10 ISS ISP6P5 CNF1 and NSF3V Registers
          1. 9.3.4.10.1 ISS ISP6P5 CNF1 and NSF3V Register Summary
          2. 9.3.4.10.2 ISS ISP6P5 CNF1 and NSF3V Register Description
        11. 9.3.4.11 ISS ISP6P5_GLBCE Registers
          1. 9.3.4.11.1 ISS ISP6P5_GLBCE Register Summary
          2. 9.3.4.11.2 ISS ISP6P5_GLBCE Register Description
    4. 9.4 ISS Still Image Coprocessor (SIMCOP)
      1. 9.4.1 ISS SIMCOP Overview
        1. 9.4.1.1 ISS SIMCOP Integration
        2. 9.4.1.2 ISS SIMCOP Functional Description
          1. 9.4.1.2.1 ISS SIMCOP Local Power and Clock Management
            1. 9.4.1.2.1.1 ISS SIMCOP Local Clock Management
            2. 9.4.1.2.1.2 Local Clock Autogating
            3. 9.4.1.2.1.3 ISS SIMCOP Power Management
          2. 9.4.1.2.2 ISS SIMCOP Reset
          3. 9.4.1.2.3 ISS SIMCOP Interrupt Merger
          4. 9.4.1.2.4 ISS SIMCOP Modules Description
        3. 9.4.1.3 ISS SIMCOP Programming Models
          1. 9.4.1.3.1 Global Initialization
            1. 9.4.1.3.1.1 Surrounding Modules Global Initialization
            2. 9.4.1.3.1.2 ISS SIMCOP Module Global Initialization
          2. 9.4.1.3.2 ISS SIMCOP Operational Modes Configuration
            1. 9.4.1.3.2.1 Interrupts
        4. 9.4.1.4 ISS SIMCOP Registers Manual
          1. 9.4.1.4.1 SIMCOP Instance Summary
          2. 9.4.1.4.2 SIMCOP Registers
            1. 9.4.1.4.2.1 SIMCOP Register Summary
            2. 9.4.1.4.2.2 SIMCOP Register Description
      2. 9.4.2 ISS SIMCOP Hardware Sequencer and Buffers Module
        1. 9.4.2.1 ISS SIMCOP Hardware Sequencer and Buffers Overview
        2. 9.4.2.2 ISS SIMCOP Hardware Sequencer and Buffer Integration
        3. 9.4.2.3 ISS SIMCOP Hardware Sequencer and Buffers Functional Description
          1. 9.4.2.3.1 ISS SIMCOP Hardware Sequencer and Buffers Software Reset
          2. 9.4.2.3.2 ISS SIMCOP Hardware Sequencer and Buffers Power Management
          3. 9.4.2.3.3 ISS SIMCOP Hardware Sequencer and Buffer Interrupt Requests
            1. 9.4.2.3.3.1 Static Crossbar
            2. 9.4.2.3.3.2 Image Buffers
          4. 9.4.2.3.4 ISS SIMCOP Hardware Sequencer
            1. 9.4.2.3.4.1 Automatic Operation
            2. 9.4.2.3.4.2 Hardware Sequencer Override
        4. 9.4.2.4 ISS SIMCOP Hardware Sequencer and Buffers Basic Programming Model
          1. 9.4.2.4.1 ISS SIMCOP Hardware Sequencer and Buffers Application Programming Principle
          2. 9.4.2.4.2 External CPU Use for Data Processing
        5. 9.4.2.5 ISS SIMCOP Hardware Sequencer and Buffer Registers Manual
          1. 9.4.2.5.1 Hardware Sequencer Instance Summary
          2. 9.4.2.5.2 Hardware Sequencer Registers
            1. 9.4.2.5.2.1 Hardware Sequencer Register Summary
            2. 9.4.2.5.2.2 Hardware Sequencer Register Description
      3. 9.4.3 ISS SIMCOP DMA Module
        1. 9.4.3.1 ISS SIMCOP DMA Overview
        2. 9.4.3.2 ISS SIMCOP DMA Integration
        3. 9.4.3.3 ISS SIMCOP DMA Functional Description
          1. 9.4.3.3.1 ISS SIMCOP DMA Block Diagram
          2. 9.4.3.3.2 ISS SIMCOP DMA Power Management
          3. 9.4.3.3.3 ISS SIMCOP DMA Interrupt Requests
          4. 9.4.3.3.4 ISS SIMCOP DMA Logical Channels
            1. 9.4.3.3.4.1 Logical Channel States
            2. 9.4.3.3.4.2 Logical Channel Chaining, Trigger, and Hardware Synchronization
            3. 9.4.3.3.4.3 Logical Channel Data Transfer
          5. 9.4.3.3.5 Transaction Generation
            1. 9.4.3.3.5.1 Incrementing Bursts for Regular Transfers
        4. 9.4.3.4 ISS SIMCOP DMA Basic Programming Model
          1. 9.4.3.4.1 Initialization of Surrounding Modules
          2. 9.4.3.4.2 ISS SIMCOP DMA Channel Configuration and Hardware Synchronization
          3. 9.4.3.4.3 Software Synchronization
        5. 9.4.3.5 ISS SIMCOP DMA Register Manual
          1. 9.4.3.5.1 ISS SIMCOP DMA Instance Summary
          2. 9.4.3.5.2 ISS SIMCOP DMA Registers
            1. 9.4.3.5.2.1 ISS SIMCOP DMA Register Summary
            2. 9.4.3.5.2.2 ISS SIMCOP DMA Register Description
      4. 9.4.4 ISS SIMCOP VTNF Module
        1. 9.4.4.1 ISS SIMCOP VTNF Overview
        2. 9.4.4.2 ISS SIMCOP VTNF Environment
          1. 9.4.4.2.1 ISS SIMCOP VTNF Protocols and Data Formats
        3. 9.4.4.3 ISS SIMCOP VTNF Integration
        4. 9.4.4.4 ISS SIMCOP VTNF Functional Description
          1. 9.4.4.4.1 ISS SIMCOP VTNF Block Diagram
          2. 9.4.4.4.2 ISS SIMCOP VTNF Clocks Management
          3. 9.4.4.4.3 ISS SIMCOP VTNF Interrupt Requests
          4. 9.4.4.4.4 ISS SIMCOP VTNF Configuration
            1. 9.4.4.4.4.1 ISS SIMCOP VTNF Initialization
            2. 9.4.4.4.4.2 ISS SIMCOP VTNF Programming Ranges and Restrictions
            3. 9.4.4.4.4.3 ISS SIMCOP VTNF Resets
            4. 9.4.4.4.4.4 ISS SIMCOP VTNF Programming Parameters Tuning
        5. 9.4.4.5 ISS SIMCOP VTNF Register Manual
          1. 9.4.4.5.1 ISS SIMCOP VTNF Instance Summary
          2. 9.4.4.5.2 ISS SIMCOP VTNF registers
            1. 9.4.4.5.2.1 ISS SIMCOP VTNF Register Summary
            2. 9.4.4.5.2.2 ISS SIMCOP VTNF Register Description
      5. 9.4.5 ISS SIMCOP LDC Module
        1. 9.4.5.1 ISS SIMCOP LDC Overview
        2. 9.4.5.2 ISS SIMCOP LDC Integration
        3. 9.4.5.3 ISS SIMCOP LDC Functional Description
          1. 9.4.5.3.1  ISS SIMCOP LDC Block Diagram
          2. 9.4.5.3.2  ISS SIMCOP LDC Interrupt Requests
          3. 9.4.5.3.3  ISS SIMCOP LDC Input/Output Format Data
            1. 9.4.5.3.3.1 ISS SIMCOP LDC YCbCr Format
            2. 9.4.5.3.3.2 ISS SIMCOP LDC Bayer Format
          4. 9.4.5.3.4  ISS SIMCOP Lens Distortion Back-Mapping
          5. 9.4.5.3.5  ISS SIMCOP LCD Bayer Chromatic Aberration Correction Implementation
          6. 9.4.5.3.6  ISS SIMCOP LDC Affine Transform
          7. 9.4.5.3.7  ISS SIMCOP LDC Perspective Transformation
          8. 9.4.5.3.8  ISS SIMCOP LDC Pixel Interpolation
          9. 9.4.5.3.9  ISS SIMCOP LDC Buffer Management
          10. 9.4.5.3.10 ISS SIMCOP LDC Input Circular Buffer
          11. 9.4.5.3.11 ISS SIMCOP LDC and Hardware Sequencer
            1. 9.4.5.3.11.1 ISS SIMCOP LDC and Hardware Sequencer and Buffers Overview
            2. 9.4.5.3.11.2 ISS SIMCOP LDC and Hardware Sequencer and Buffer Integration
            3. 9.4.5.3.11.3 ISS SIMCOP LDC and Hardware Sequencer and Buffers Functional Description
              1. 9.4.5.3.11.3.1 ISS SIMCOP Hardware Sequencer Buffer Description
                1. 9.4.5.3.11.3.1.1 ISS SIMCOP LDC Static Crossbar
                2. 9.4.5.3.11.3.1.2 ISS SIMCOP LDC Private Input Memory
              2. 9.4.5.3.11.3.2 ISS SIMCOP Hardware Sequencer
                1. 9.4.5.3.11.3.2.1 Hardware Sequencer Override
        4. 9.4.5.4 ISS SIMCOP LDC Basic Programming Model
          1. 9.4.5.4.1 ISS SIMCOP LDC Initialization of Surrounding Modules
          2. 9.4.5.4.2 ISS SIMCOP LDC Geometric Distortion Mode
          3. 9.4.5.4.3 ISS SIMCOP LDC Bayer Chromatic Aberration Mode
          4. 9.4.5.4.4 ISS SIMCOP LDC Programming Affine Transformation
          5. 9.4.5.4.5 ISS SIMCOP LDC Programming Perspective Transformation
        5. 9.4.5.5 ISS SIMCOP LDC Register Manual
          1. 9.4.5.5.1 ISS SIMCOP LDC Instance Summary
          2. 9.4.5.5.2 ISS SIMCOP LDC Registers
            1. 9.4.5.5.2.1 ISS SIMCOP LDC Register Summary
            2. 9.4.5.5.2.2 ISS SIMCOP LDC Register Description
  12. 10Camera Interface Subsystem
    1. 10.1 CAMSS Overview
      1. 10.1.1 CAMSS Block Diagram
      2. 10.1.2 1914
      3. 10.1.3 CAMSS Features
    2. 10.2 CAMSS Environment
      1. 10.2.1 CAMSS Interfaces Signal Descriptions
    3. 10.3 CAMSS Integration
      1. 10.3.1 CAMSS Main Integration Attributes
      2. 10.3.2 CAL Integration - Video Port
      3. 10.3.3 CAL Integration - PPI Interface
    4. 10.4 CAMSS Functional Description
      1. 10.4.1 CAMSS Hardware and Software Reset
      2. 10.4.2 CAMSS Clock Configuration
      3. 10.4.3 CAMSS Power Management
      4. 10.4.4 CAMSS Interrupt Events
      5. 10.4.5 CSI2 PHY Functional Description
        1. 10.4.5.1 CSI2 PHY Overview
        2. 10.4.5.2 CSI2 PHY Configuration
        3. 10.4.5.3 CSI2 PHY Link Initialization Sequence
        4. 10.4.5.4 CSI2 PHY Error Signals
      6. 10.4.6 CAL Functional Description
        1. 10.4.6.1  CAL Block Diagram
        2. 10.4.6.2  CSI2 Low Level Protocol
          1. 10.4.6.2.1 CSI2 Physical Layer
          2. 10.4.6.2.2 CSI2 Multi-lane Layer and Lane Merger
          3. 10.4.6.2.3 CSI2 Protocol Layer
            1. 10.4.6.2.3.1  CSI2 Short Packet
            2. 10.4.6.2.3.2  CSI2 Long Packet
            3. 10.4.6.2.3.3  CSI2 ECC and Checksum Generation
              1. 10.4.6.2.3.3.1 CSI2 ECC
              2. 10.4.6.2.3.3.2 CSI2 Checksum
            4. 10.4.6.2.3.4  CSI2 Alignment Constraints
            5. 10.4.6.2.3.5  CSI2 Data Identifier
            6. 10.4.6.2.3.6  CSI2 Virtual Channel ID
            7. 10.4.6.2.3.7  CSI2 Synchronization Codes
            8. 10.4.6.2.3.8  CSI2 Generic Short Packet Codes
            9. 10.4.6.2.3.9  CSI2 Frame Structure and Data
            10. 10.4.6.2.3.10 CSI2 Virtual Channel and Context
          4. 10.4.6.2.4 CSI2 TAG Generation FSM
        3. 10.4.6.3  CAL Data Stream Merger
        4. 10.4.6.4  CAL Pixel Extraction
        5. 10.4.6.5  CAL DPCM Decoding and Encoding
        6. 10.4.6.6  CAL Stream Interleaving
        7. 10.4.6.7  CAL Pixel Packing
        8. 10.4.6.8  CAL Write DMA
          1. 10.4.6.8.1 CAL Write DMA Overview
          2. 10.4.6.8.2 CAL Write DMA Data Cropping
          3. 10.4.6.8.3 CAL Write DMA YUV422 to YUV422BP Conversion
          4. 10.4.6.8.4 CAL Write DMA Buffer Management
          5. 10.4.6.8.5 CAL Write DMA OCP Address Generation
            1. 10.4.6.8.5.1 Write DMA Buffer Base Address
            2. 10.4.6.8.5.2 Write DMA Line Start Address
            3. 10.4.6.8.5.3 Write DMA Data Address
          6. 10.4.6.8.6 CAL Write DMA OCP Transaction Generation
          7. 10.4.6.8.7 CAL Write DMA Real Time Traffic
        9. 10.4.6.9  CAL Video Port
          1. 10.4.6.9.1 CAL Video Port Overview
          2. 10.4.6.9.2 CAL Video Port Pixel Clock Generation
          3. 10.4.6.9.3 CAL Video Port Video Timing Generator
        10. 10.4.6.10 CAL Registers Shadowing
    5. 10.5 CAMSS Register Manual
      1. 10.5.1 CAMSS Instance Summary
      2. 10.5.2 CAL Registers
        1. 10.5.2.1 CAL Register Summary
        2. 10.5.2.2 CAL Register Description
      3. 10.5.3 CSI2 PHY Registers
        1. 10.5.3.1 CSI2 PHY Register Summary
        2. 10.5.3.2 CSI2 PHY Register Description
  13. 11Video Input Port
    1. 11.1 VIP Overview
    2. 11.2 VIP Environment
    3. 11.3 VIP Integration
    4. 11.4 VIP Functional Description
      1. 11.4.1 VIP Block Diagram
      2. 11.4.2 VIP Software Reset
      3. 11.4.3 VIP Power and Clocks Management
        1. 11.4.3.1 VIP Clocks
        2. 11.4.3.2 VIP Idle Mode
        3. 11.4.3.3 VIP StandBy Mode
      4. 11.4.4 VIP Slice
        1. 11.4.4.1 VIP Slice Processing Path Overview
        2. 11.4.4.2 VIP Slice Processing Path Multiplexers
          1. 11.4.4.2.1 VIP_CSC Multiplexers
          2. 11.4.4.2.2 VIP_SC Multiplexer
          3. 11.4.4.2.3 Output to VPDMA Multiplexers
        3. 11.4.4.3 VIP Slice Processing Path Examples
          1. 11.4.4.3.1 Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
          2. 11.4.4.3.2 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
          3. 11.4.4.3.3 Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
          4. 11.4.4.3.4 Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
          5. 11.4.4.3.5 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
          6. 11.4.4.3.6 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
          7. 11.4.4.3.7 Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
          8. 11.4.4.3.8 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
          9. 11.4.4.3.9 Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
      5. 11.4.5 VIP Parser
        1. 11.4.5.1  Features
        2. 11.4.5.2  Repacker
        3. 11.4.5.3  Analog Video
        4. 11.4.5.4  Digitized Video
        5. 11.4.5.5  Frame Buffers
        6. 11.4.5.6  Input Data Interface
          1. 11.4.5.6.1  8b Interface Mode
          2. 11.4.5.6.2  16b Interface Mode
          3. 11.4.5.6.3  24b Interface Mode
          4. 11.4.5.6.4  Signal Relationships
          5. 11.4.5.6.5  General 5 Pin Interfaces
          6. 11.4.5.6.6  Signal Subsets—4 Pin VSYNC, ACTVID, and FID
          7. 11.4.5.6.7  Signal Subsets—4 Pin VSYNC, HSYNC, and FID
          8. 11.4.5.6.8  Vertical Sync
          9. 11.4.5.6.9  Field ID Determination Using Dedicated Signal
          10. 11.4.5.6.10 Field ID Determination Using VSYNC Skew
          11. 11.4.5.6.11 Rationale for FID Determination By VSYNC Skew
          12. 11.4.5.6.12 ACTVID Framing
          13. 11.4.5.6.13 Ancillary Data Storage in Descrete Sync Mode
        7. 11.4.5.7  BT.656 Style Embedded Sync
          1. 11.4.5.7.1 Data Input
          2. 11.4.5.7.2 Sync Words
          3. 11.4.5.7.3 Error Correction
          4. 11.4.5.7.4 Embedded Sync Ancillary Data
          5. 11.4.5.7.5 Embedded Sync RGB 24-bit Data
        8. 11.4.5.8  Source Multiplexing
          1. 11.4.5.8.1  Multiplexing Scenarios
          2. 11.4.5.8.2  2-Way Multiplexing
          3. 11.4.5.8.3  4-Way Multiplexing
          4. 11.4.5.8.4  Line Multiplexing
          5. 11.4.5.8.5  Super Frame Concept in Line Multiplexing
          6. 11.4.5.8.6  8-bit Data Interface in Line Multiplexing
          7. 11.4.5.8.7  16-bit Data Interface in Line Multiplexing
          8. 11.4.5.8.8  Split Lines in Line Multiplex Mode
          9. 11.4.5.8.9  Meta Data
          10. 11.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping
        9. 11.4.5.9  Channel ID Extraction for 2x/4x Multiplexed Source
          1. 11.4.5.9.1 Channel ID Extraction Overview
          2. 11.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
          3. 11.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
        10. 11.4.5.10 Embedded Sync Mux Modes and Data Bus Widths
        11. 11.4.5.11 Ancillary and Active Video Cropping
        12. 11.4.5.12 Interrupts
        13. 11.4.5.13 VDET Interrupt
        14. 11.4.5.14 Source Video Size
        15. 11.4.5.15 Clipping
        16. 11.4.5.16 Current and Last FID Value
        17. 11.4.5.17 Disable Handling
        18. 11.4.5.18 Picture Size Interrupt
        19. 11.4.5.19 Discrete Sync Signals
          1. 11.4.5.19.1 VBLNK and HBLNK
          2. 11.4.5.19.2 BLNK and ACTVID (1)
          3. 11.4.5.19.3 VBLNK and ACTVID(2)
          4. 11.4.5.19.4 VBLNK and HSYNC
          5. 11.4.5.19.5 VSYNC and HBLNK
          6. 11.4.5.19.6 VSYNC and ACTIVID(1)
          7. 11.4.5.19.7 VSYNC and ACTIVID(2)
          8. 11.4.5.19.8 VSYNC and HSYNC
          9. 11.4.5.19.9 Line and Pixel Capture Examples
        20. 11.4.5.20 VIP Overflow Detection and Recovery
      6. 11.4.6 VIP Color Space Converter (CSC)
        1. 11.4.6.1 CSC Features
        2. 11.4.6.2 CSC Functional Description
          1. 11.4.6.2.1 HDTV Application
            1. 11.4.6.2.1.1 HDTV Application with Video Data Range
            2. 11.4.6.2.1.2 HDTV Application with Graphics Data Range
            3. 11.4.6.2.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 11.4.6.2.2 SDTV Application
            1. 11.4.6.2.2.1 SDTV Application with Video Data Range
            2. 11.4.6.2.2.2 SDTV Application with Graphics Data Range
            3. 11.4.6.2.2.3 Quantized Coefficients for Color Space Converter in SDTV
        3. 11.4.6.3 CSC Bypass Mode
      7. 11.4.7 VIP Scaler (SC)
        1. 11.4.7.1 SC Features
        2. 11.4.7.2 SC Functional Description
          1. 11.4.7.2.1 Trimmer
          2. 11.4.7.2.2 2084
          3. 11.4.7.2.3 Peaking
          4. 11.4.7.2.4 Vertical Scaler
            1. 11.4.7.2.4.1 Running Average Filter
            2. 11.4.7.2.4.2 Vertical Scaler Configuration Parameters
          5. 11.4.7.2.5 Horizontal Scaler
            1. 11.4.7.2.5.1 Half Decimation Filter
            2. 11.4.7.2.5.2 Polyphase Filter
            3. 11.4.7.2.5.3 Nonlinear Horizontal Scaling
            4. 11.4.7.2.5.4 Horizontal Scaler Configuration Registers
          6. 11.4.7.2.6 Basic Configurations
          7. 11.4.7.2.7 Coefficient Memory
            1. 11.4.7.2.7.1 Overview
            2. 11.4.7.2.7.2 Physical Coefficient SRAM Layout
            3. 11.4.7.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 11.4.7.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 11.4.7.2.7.5 VPI Control Interface
            6. 11.4.7.2.7.6 Coefficient Table Selection Guide
        3. 11.4.7.3 SC Code
          1. 11.4.7.3.1 Generate Coefficient Memory Image
          2. 11.4.7.3.2 Scaler Configuration Calculation
          3. 11.4.7.3.3 Typical Configuration Values
        4. 11.4.7.4 SC Coefficient Data Files
          1. 11.4.7.4.1 HS Polyphase Filter Coefficients
            1. 11.4.7.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 11.4.7.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 11.4.7.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 11.4.7.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 11.4.7.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 11.4.7.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 11.4.7.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 11.4.7.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 11.4.7.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 11.4.7.4.2 VS Polyphase Filter Coefficients
            1. 11.4.7.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 11.4.7.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 11.4.7.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 11.4.7.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 11.4.7.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 11.4.7.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 11.4.7.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 11.4.7.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 11.4.7.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 11.4.7.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 11.4.7.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 11.4.7.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 11.4.7.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 11.4.7.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
          3. 11.4.7.4.3 VS (Bilinear Filter Coefficients)
            1. 11.4.7.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      8. 11.4.8 VIP Video Port Direct Memory Access (VPDMA)
        1. 11.4.8.1  VPDMA Introduction
        2. 11.4.8.2  VPDMA Basic Definitions
          1. 11.4.8.2.1 Client
          2. 11.4.8.2.2 Channel
          3. 11.4.8.2.3 List
          4. 11.4.8.2.4 Data Formats Supported
        3. 11.4.8.3  2141
        4. 11.4.8.4  VPDMA Client Buffering and Functionality
        5. 11.4.8.5  VPDMA Channels Assignment
        6. 11.4.8.6  VPDMA MFLAG Mechanism
        7. 11.4.8.7  VPDMA Interrupts
        8. 11.4.8.8  VPDMA Descriptors
          1. 11.4.8.8.1 Data Transfer Descriptors
            1. 11.4.8.8.1.1 Data Packet Descriptor Word 0 (Data)
              1. 11.4.8.8.1.1.1 Data Type
              2. 11.4.8.8.1.1.2 Notify
              3. 11.4.8.8.1.1.3 Field
              4. 11.4.8.8.1.1.4 Even Line Skip
              5. 11.4.8.8.1.1.5 Odd Line Skip
              6. 11.4.8.8.1.1.6 Line Stride
            2. 11.4.8.8.1.2 Data Packet Descriptor Word 1
              1. 11.4.8.8.1.2.1 Line Length
              2. 11.4.8.8.1.2.2 Transfer Height
            3. 11.4.8.8.1.3 Data Packet Descriptor Word 2
              1. 11.4.8.8.1.3.1 Start Address
            4. 11.4.8.8.1.4 Data Packet Descriptor Word 3
              1. 11.4.8.8.1.4.1 Packet Type
              2. 11.4.8.8.1.4.2 Mode
              3. 11.4.8.8.1.4.3 Direction
              4. 11.4.8.8.1.4.4 Channel
              5. 11.4.8.8.1.4.5 Priority
              6. 11.4.8.8.1.4.6 Next Channel
            5. 11.4.8.8.1.5 Data Packet Descriptor Word 4
              1. 11.4.8.8.1.5.1 Inbound data
                1. 11.4.8.8.1.5.1.1 Frame Width
                2. 11.4.8.8.1.5.1.2 Frame Height
              2. 11.4.8.8.1.5.2 Outbound data
                1. 11.4.8.8.1.5.2.1 Descriptor Write Address
                2. 11.4.8.8.1.5.2.2 Write Descriptor
                3. 11.4.8.8.1.5.2.3 Drop Data
            6. 11.4.8.8.1.6 Data Packet Descriptor Word 5
              1. 11.4.8.8.1.6.1 Outbound data
                1. 11.4.8.8.1.6.1.1 Max Width
                2. 11.4.8.8.1.6.1.2 Max Height
          2. 11.4.8.8.2 Configuration Descriptor
            1. 11.4.8.8.2.1 Configuration Descriptor Header Word0
            2. 11.4.8.8.2.2 Configuration Descriptor Header Word1
              1. 11.4.8.8.2.2.1 Number of Data Words
            3. 11.4.8.8.2.3 Configuration Descriptor Header Word2
              1. 11.4.8.8.2.3.1 Payload Location
            4. 11.4.8.8.2.4 Configuration Descriptor Header Word3
              1. 11.4.8.8.2.4.1 Packet Type
              2. 11.4.8.8.2.4.2 Direct
              3. 11.4.8.8.2.4.3 Class
                1. 11.4.8.8.2.4.3.1 Address Data Block Format
              4. 11.4.8.8.2.4.4 Destination
              5. 11.4.8.8.2.4.5 Descriptor Length
          3. 11.4.8.8.3 Control Descriptor
            1. 11.4.8.8.3.1 Generic Control Descriptor Format
            2. 11.4.8.8.3.2 Control Descriptor Header Description
              1. 11.4.8.8.3.2.1 Packet Type
              2. 11.4.8.8.3.2.2 Source
              3. 11.4.8.8.3.2.3 Control
            3. 11.4.8.8.3.3 Control Descriptor Types
              1. 11.4.8.8.3.3.1 Sync on Client
              2. 11.4.8.8.3.3.2 Sync on List
              3. 11.4.8.8.3.3.3 Sync on External Event
              4. 11.4.8.8.3.3.4 Sync on Channel
              5. 11.4.8.8.3.3.5 Sync on LM Timer
              6. 11.4.8.8.3.3.6 Change Client Interrupt
              7. 11.4.8.8.3.3.7 Send Interrupt
              8. 11.4.8.8.3.3.8 Reload List
              9. 11.4.8.8.3.3.9 Abort Channel
        9. 11.4.8.9  VPDMA Configuration
          1. 11.4.8.9.1 Regular List
          2. 11.4.8.9.2 Video Input Ports
            1. 11.4.8.9.2.1 Multiplexed Data Streams
            2. 11.4.8.9.2.2 Single YUV Color Separate
            3. 11.4.8.9.2.3 Dual YUV Interleaved
        10. 11.4.8.10 VPDMA Data Formats
          1. 11.4.8.10.1 YUV Data Formats
            1. 11.4.8.10.1.1 Y 4:4:4 (Data Type 0)
            2. 11.4.8.10.1.2 Y 4:2:2 (Data Type 1)
            3. 11.4.8.10.1.3 Y 4:2:0 (Data Type 2)
            4. 11.4.8.10.1.4 C 4:4:4 (Data Type 4)
            5. 11.4.8.10.1.5 C 4:2:2 (Data Type 5)
            6. 11.4.8.10.1.6 C 4:2:0 (Data Type 6)
            7. 11.4.8.10.1.7 YC 4:2:2 (Data Type 7)
            8. 11.4.8.10.1.8 YC 4:4:4 (Data Type 8)
            9. 11.4.8.10.1.9 CY 4:2:2 (Data Type 23)
          2. 11.4.8.10.2 RGB Data Formats
            1. 11.4.8.10.2.1  RGB16-565 (Data Type 0)
            2. 11.4.8.10.2.2  ARGB-1555 (Data Type 1)
            3. 11.4.8.10.2.3  ARGB-4444 (Data Type 2)
            4. 11.4.8.10.2.4  RGBA-5551 (Data Type 3)
            5. 11.4.8.10.2.5  RGBA-4444 (Data Type 4)
            6. 11.4.8.10.2.6  ARGB24-6666 (Data Type 5)
            7. 11.4.8.10.2.7  RGB24-888 (Data Type 6)
            8. 11.4.8.10.2.8  ARGB32-8888 (Data Type 7)
            9. 11.4.8.10.2.9  RGBA24-6666 (Data Type 8)
            10. 11.4.8.10.2.10 RGBA32-8888 (Data Type 9)
          3. 11.4.8.10.3 Miscellaneous Data Type
    5. 11.5 VIP Register Manual
      1. 11.5.1 VIP Instance Summary
      2. 11.5.2 VIP Top Level Registers
        1. 11.5.2.1 VIP Top Level Register Summary
        2. 11.5.2.2 VIP Top Level Register Description
      3. 11.5.3 VIP Parser Registers
        1. 11.5.3.1 VIP Parser Register Summary
        2. 11.5.3.2 VIP Parser Register Description
      4. 11.5.4 VIP CSC Registers
        1. 11.5.4.1 VIP CSC Register Summary
        2. 11.5.4.2 VIP CSC Register Description
      5. 11.5.5 VIP SC registers
        1. 11.5.5.1 VIP SC Register Summary
        2. 11.5.5.2 VIP SC Register Description
      6. 11.5.6 VIP VPDMA Registers
        1. 11.5.6.1 VIP VPDMA Register Summary
        2. 11.5.6.2 VIP VPDMA Register Description
  14. 12Video Processing Engine
    1. 12.1 VPE Overview
    2. 12.2 VPE Integration
    3. 12.3 VPE Functional Description
      1. 12.3.1  VPE Block Diagram
      2. 12.3.2  VPE VC1 Range Mapping/Range Reduction
      3. 12.3.3  VPE Deinterlacer (DEI)
        1. 12.3.3.1 Functional Description
        2. 12.3.3.2 Bypass Mode
        3. 12.3.3.3 2263
          1. 12.3.3.3.1 VPDMA Interface
          2. 12.3.3.3.2 MDT
          3. 12.3.3.3.3 EDI
          4. 12.3.3.3.4 FMD
          5. 12.3.3.3.5 MUX
          6. 12.3.3.3.6 LINE BUFFER
      4. 12.3.4  VPE Scaler (SC)
        1. 12.3.4.1 SC Features
        2. 12.3.4.2 SC Functional Description
          1. 12.3.4.2.1 Trimmer
          2. 12.3.4.2.2 2274
          3. 12.3.4.2.3 Peaking
          4. 12.3.4.2.4 Vertical Scaler
            1. 12.3.4.2.4.1 Running Average Filter
            2. 12.3.4.2.4.2 Vertical Scaler Configuration Parameters
          5. 12.3.4.2.5 Horizontal Scaler
            1. 12.3.4.2.5.1 Half Decimation Filter
            2. 12.3.4.2.5.2 Polyphase Filter
            3. 12.3.4.2.5.3 Nonlinear Horizontal Scaling
            4. 12.3.4.2.5.4 Horizontal Scaler Configuration Registers
          6. 12.3.4.2.6 Basic Configurations
          7. 12.3.4.2.7 Coefficient Memory
            1. 12.3.4.2.7.1 Overview
            2. 12.3.4.2.7.2 Physical Coefficient SRAM Layout
            3. 12.3.4.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 12.3.4.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 12.3.4.2.7.5 VPI Control Interface
            6. 12.3.4.2.7.6 Coefficient Table Selection Guide
        3. 12.3.4.3 SC Code
          1. 12.3.4.3.1 Generate Coefficient Memory Image
          2. 12.3.4.3.2 Scaler Configuration Calculation
          3. 12.3.4.3.3 Typical Configuration Values
        4. 12.3.4.4 SC Coefficient Data Files
          1. 12.3.4.4.1 HS Polyphase Filter Coefficients
            1. 12.3.4.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 12.3.4.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 12.3.4.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 12.3.4.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 12.3.4.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 12.3.4.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 12.3.4.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 12.3.4.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 12.3.4.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 12.3.4.4.2 VS Polyphase Filter Coefficients
            1. 12.3.4.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 12.3.4.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 12.3.4.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 12.3.4.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 12.3.4.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 12.3.4.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 12.3.4.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 12.3.4.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 12.3.4.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 12.3.4.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 12.3.4.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 12.3.4.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 12.3.4.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 12.3.4.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
              9. 12.3.4.4.2.6.9 ppcoef_scale_1x_ver_5tap.dat
          3. 12.3.4.4.3 VS (Bilinear Filter Coefficients)
            1. 12.3.4.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      5. 12.3.5  VPE Color Space Converter (CSC)
        1. 12.3.5.1 CSC Features
        2. 12.3.5.2 CSC Functional Description
        3. 12.3.5.3 2328
          1. 12.3.5.3.1 HDTV Application
            1. 12.3.5.3.1.1 HDTV Application with Video Data Range
            2. 12.3.5.3.1.2 HDTV Application with Graphics Data Range
            3. 12.3.5.3.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 12.3.5.3.2 SDTV Application
            1. 12.3.5.3.2.1 SDTV Application with Video Data Range
            2. 12.3.5.3.2.2 SDTV Application with Graphics Data Range
            3. 12.3.5.3.2.3 Quantized Coefficients for Color Space Converter in SDTV
        4. 12.3.5.4 CSC Bypass Mode
      6. 12.3.6  VPE Chroma Up-Sampler (CHR_US)
        1. 12.3.6.1 Features
        2. 12.3.6.2 Functional Description
        3. 12.3.6.3 For Interlaced YUV420 Input Data
        4. 12.3.6.4 Edge Effects
        5. 12.3.6.5 Modes of Operation (VPDMA)
        6. 12.3.6.6 Coefficient Configuration
      7. 12.3.7  VPE Chroma Down-Sampler (CHR_DS)
      8. 12.3.8  VPE YUV422 to YUV444 Conversion
      9. 12.3.9  VPE Video Port Direct Memory Access (VPDMA)
        1. 12.3.9.1 VPDMA Introduction
        2. 12.3.9.2 VPDMA Basic Definitions
          1. 12.3.9.2.1 Client
          2. 12.3.9.2.2 Channel
          3. 12.3.9.2.3 List
          4. 12.3.9.2.4 Data Formats Supported
        3. 12.3.9.3 VPDMA Client Buffering and Functionality
        4. 12.3.9.4 VPDMA Channels Assignment
        5. 12.3.9.5 VPDMA Interrupts
        6. 12.3.9.6 VPDMA Descriptors
          1. 12.3.9.6.1 Data Transfer Descriptors
            1. 12.3.9.6.1.1 Data Packet Descriptor Word 0 (Data)
              1. 12.3.9.6.1.1.1 Data Type
              2. 12.3.9.6.1.1.2 Notify
              3. 12.3.9.6.1.1.3 Field
              4. 12.3.9.6.1.1.4 1D
              5. 12.3.9.6.1.1.5 Even Line Skip
              6. 12.3.9.6.1.1.6 Odd Line Skip
              7. 12.3.9.6.1.1.7 Line Stride
            2. 12.3.9.6.1.2 Data Packet Descriptor Word 1
              1. 12.3.9.6.1.2.1 Line Length
              2. 12.3.9.6.1.2.2 Transfer Height
            3. 12.3.9.6.1.3 Data Packet Descriptor Word 2
              1. 12.3.9.6.1.3.1 Start Address
            4. 12.3.9.6.1.4 Data Packet Descriptor Word 3
              1. 12.3.9.6.1.4.1 Packet Type
              2. 12.3.9.6.1.4.2 Mode
              3. 12.3.9.6.1.4.3 Direction
              4. 12.3.9.6.1.4.4 Channel
              5. 12.3.9.6.1.4.5 Priority
              6. 12.3.9.6.1.4.6 Next Channel
            5. 12.3.9.6.1.5 Data Packet Descriptor Word 4
              1. 12.3.9.6.1.5.1 Inbound data
                1. 12.3.9.6.1.5.1.1 Frame Width
                2. 12.3.9.6.1.5.1.2 Frame Height
              2. 12.3.9.6.1.5.2 Outbound data
                1. 12.3.9.6.1.5.2.1 Descriptor Write Address
                2. 12.3.9.6.1.5.2.2 Write Descriptor
                3. 12.3.9.6.1.5.2.3 Drop Data
                4. 12.3.9.6.1.5.2.4 Use Descriptor Register
            6. 12.3.9.6.1.6 Data Packet Descriptor Word 5
              1. 12.3.9.6.1.6.1 Outbound data
                1. 12.3.9.6.1.6.1.1 Max Width
                2. 12.3.9.6.1.6.1.2 Max Height
            7. 12.3.9.6.1.7 Data Packet Descriptor Word 6/7 (Data)
          2. 12.3.9.6.2 Configuration Descriptor
            1. 12.3.9.6.2.1 Configuration Descriptor Header Word0
            2. 12.3.9.6.2.2 Configuration Descriptor Header Word1
              1. 12.3.9.6.2.2.1 Number of Data Words
            3. 12.3.9.6.2.3 Configuration Descriptor Header Word2
              1. 12.3.9.6.2.3.1 Payload Location
            4. 12.3.9.6.2.4 Configuration Descriptor Header Word3
              1. 12.3.9.6.2.4.1 Packet Type
              2. 12.3.9.6.2.4.2 Direct
              3. 12.3.9.6.2.4.3 Class
                1. 12.3.9.6.2.4.3.1 Address Data Block Format
              4. 12.3.9.6.2.4.4 Destination
              5. 12.3.9.6.2.4.5 Descriptor Length
          3. 12.3.9.6.3 Control Descriptor
            1. 12.3.9.6.3.1 Generic Control Descriptor Format
            2. 12.3.9.6.3.2 Control Descriptor Header Description
              1. 12.3.9.6.3.2.1 Packet Type
              2. 12.3.9.6.3.2.2 Source
              3. 12.3.9.6.3.2.3 Control
            3. 12.3.9.6.3.3 Control Descriptor Types
              1. 12.3.9.6.3.3.1 Sync on Client
              2. 12.3.9.6.3.3.2 Sync on List
              3. 12.3.9.6.3.3.3 Sync on External Event
              4. 12.3.9.6.3.3.4 Sync on Channel
              5. 12.3.9.6.3.3.5 Sync on LM Timer
              6. 12.3.9.6.3.3.6 Change Client Interrupt
              7. 12.3.9.6.3.3.7 Send Interrupt
              8. 12.3.9.6.3.3.8 Reload List
              9. 12.3.9.6.3.3.9 Abort Channel
        7. 12.3.9.7 VPDMA Configuration
          1. 12.3.9.7.1 Regular List
          2. 12.3.9.7.2 Video Input Ports
            1. 12.3.9.7.2.1 Single YUV Color Separate
            2. 12.3.9.7.2.2 Dual YUV Interleaved
            3. 12.3.9.7.2.3 Single RGB Stream
        8. 12.3.9.8 VPDMA Data Formats
          1. 12.3.9.8.1 YUV Data Formats
            1. 12.3.9.8.1.1 Y 4:4:4 (Data Type 0)
            2. 12.3.9.8.1.2 Y 4:2:2 (Data Type 1)
            3. 12.3.9.8.1.3 Y 4:2:0 (Data Type 2)
            4. 12.3.9.8.1.4 C 4:4:4 (Data Type 4)
            5. 12.3.9.8.1.5 C 4:2:2 (Data Type 5)
            6. 12.3.9.8.1.6 C 4:2:0 (Data Type 6)
            7. 12.3.9.8.1.7 YC 4:2:2 (Data Type 7)
            8. 12.3.9.8.1.8 YC 4:4:4 (Data Type 8)
            9. 12.3.9.8.1.9 CY 4:2:2 (Data Type 23)
          2. 12.3.9.8.2 RGB Data Formats
            1. 12.3.9.8.2.1 Input Data Formats
              1. 12.3.9.8.2.1.1  RGB16-565 (Data Type 0)
              2. 12.3.9.8.2.1.2  ARGB-1555 (Data Type 1)
              3. 12.3.9.8.2.1.3  ARGB-4444 (Data Type 2)
              4. 12.3.9.8.2.1.4  RGBA-5551 (Data Type 3)
              5. 12.3.9.8.2.1.5  RGBA-4444 (Data Type 4)
              6. 12.3.9.8.2.1.6  ARGB24-6666 (Data Type 5)
              7. 12.3.9.8.2.1.7  RGB24-888 (Data Type 6)
              8. 12.3.9.8.2.1.8  ARGB32-8888 (Data Type 7)
              9. 12.3.9.8.2.1.9  RGBA24-6666 (Data Type 8)
              10. 12.3.9.8.2.1.10 RGBA32-8888 (Data Type 9)
            2. 12.3.9.8.2.2 Output Data Formats
              1. 12.3.9.8.2.2.1  RGB16-565 (Data Type 0)
              2. 12.3.9.8.2.2.2  ARGB-1555 (Data Type 1)
              3. 12.3.9.8.2.2.3  ARGB-4444 (Data Type 2)
              4. 12.3.9.8.2.2.4  RGBA-5551 (Data Type 3)
              5. 12.3.9.8.2.2.5  RGBA-4444 (Data Type 4)
              6. 12.3.9.8.2.2.6  ARGB24-6666 (Data Type 5)
              7. 12.3.9.8.2.2.7  RGB24-888 (Data Type 6)
              8. 12.3.9.8.2.2.8  ARGB32-8888 (Data Type 7)
              9. 12.3.9.8.2.2.9  RGBA24-6666 (Data Type 8)
              10. 12.3.9.8.2.2.10 RGBA32-8888 (Data Type 9)
          3. 12.3.9.8.3 Miscellaneous Data Type
      10. 12.3.10 VPE Software Reset
      11. 12.3.11 VPE Power and Clocks Management
        1. 12.3.11.1 VPE Clocks
        2. 12.3.11.2 VPE Idle Mode
        3. 12.3.11.3 VPE StandBy Mode
    4. 12.4 VPE Register Manual
      1. 12.4.1 VPE Instance Summary
      2. 12.4.2 VPE_CSC Registers
        1. 12.4.2.1 VPE_CSC Register Summary
        2. 12.4.2.2 VPE_CSC Register Description
      3. 12.4.3 VPE_SC Registers
        1. 12.4.3.1 VPE_SC Register Summary
        2. 12.4.3.2 VPE_SC Register Description
      4. 12.4.4 VPE_CHR_US Registers
        1. 12.4.4.1 VPE_CHR_US Register Summary
        2. 12.4.4.2 VPE_CHR_US Register Description
      5. 12.4.5 VPE_DEI Registers
        1. 12.4.5.1 VPE_DEI Register Summary
        2. 12.4.5.2 VPE_DEI Register Description
      6. 12.4.6 VPE_VPDMA Registers
        1. 12.4.6.1 VPE_VPDMA Register Summary
        2. 12.4.6.2 VPE_VPDMA Register Description
      7. 12.4.7 VPE_TOP_LEVEL Registers
        1. 12.4.7.1 VPE_TOP_LEVEL Register Summary
        2. 12.4.7.2 VPE_TOP_LEVEL Register Description
  15. 13Display Subsystem
    1. 13.1 Display Subsystem Overview
      1. 13.1.1 Display Subsystem Environment
        1. 13.1.1.1 Display Subsystem LCD Support
          1. 13.1.1.1.1 Display Subsystem LCD with Parallel Interfaces
        2. 13.1.1.2 Display Subsystem TV Display Support
          1. 13.1.1.2.1 Display Subsystem TV With Parallel Interfaces
          2. 13.1.1.2.2 Display Subsystem TV With Serial Interfaces
      2. 13.1.2 Display Subsystem Integration
        1. 13.1.2.1 Display Subsystem Clocks
        2. 13.1.2.2 Display Subsystem Resets
        3. 13.1.2.3 Display Subsystem Power Management
          1. 13.1.2.3.1 Display Subsystem Standby Mode
          2. 13.1.2.3.2 2501
          3. 13.1.2.3.3 Display Subsystem Wake-Up Mode
      3. 13.1.3 Display Subsystem DPLL Controllers Functional Description
        1. 13.1.3.1 DPLL Controllers Overview
        2. 13.1.3.2 OCP2SCP2 Functional Description
          1. 13.1.3.2.1 OCP2SCP2 Reset
            1. 13.1.3.2.1.1 Hardware Reset
            2. 13.1.3.2.1.2 Software Reset
          2. 13.1.3.2.2 OCP2SCP2 Power Management
            1. 13.1.3.2.2.1 Idle Mode
            2. 13.1.3.2.2.2 Clock Gating
          3. 13.1.3.2.3 OCP2SCP2 Timing Registers
        3. 13.1.3.3 DPLL_VIDEO Functional Description
          1. 13.1.3.3.1 DPLL_VIDEO Controller Architecture
          2. 13.1.3.3.2 DPLL_VIDEO Operations
          3. 13.1.3.3.3 DPLL_VIDEO Error Handling
          4. 13.1.3.3.4 DPLL_VIDEO Software Reset
          5. 13.1.3.3.5 DPLL_VIDEO Power Management
          6. 13.1.3.3.6 DPLL_VIDEO HSDIVIDER Loading Operation
          7. 13.1.3.3.7 DPLL_VIDEO Clock Sequence
          8. 13.1.3.3.8 DPLL_VIDEO Go Sequence
          9. 13.1.3.3.9 DPLL_VIDEO Recommended Values
        4. 13.1.3.4 DPLL_HDMI Functional Description
          1. 13.1.3.4.1  DPLL_HDMI and PLLCTRL_HDMI Overview
          2. 13.1.3.4.2  DPLL_HDMI and PLLCTRL_HDMI Architecture
          3. 13.1.3.4.3  DPLL_HDMI Operations
          4. 13.1.3.4.4  DPLL_HDMI Register Access
          5. 13.1.3.4.5  DPLL_HDMI Error Handling
          6. 13.1.3.4.6  DPLL_HDMI Software Reset
          7. 13.1.3.4.7  DPLL_HDMI Power Management
          8. 13.1.3.4.8  DPLL_HDMI Lock Sequence
          9. 13.1.3.4.9  DPLL_HDMI Go Sequence
          10. 13.1.3.4.10 DPLL_HDMI Recommended Values
      4. 13.1.4 Display Subsystem Programming Guide
      5. 13.1.5 Display Subsystem Register Manual
        1. 13.1.5.1 Display Subsystem Instance Summary
        2. 13.1.5.2 Display Subsystem Registers
          1. 13.1.5.2.1 Display Subsystem Registers Mapping Summary
          2. 13.1.5.2.2 Display Subsystem Register Description
        3. 13.1.5.3 OCP2SCP2 registers
          1. 13.1.5.3.1 OCP2SCP2 Register Summary
          2. 13.1.5.3.2 OCP2SCP Register Description
        4. 13.1.5.4 DPLL_VIDEO Registers
          1. 13.1.5.4.1 DPLL_VIDEO Register Summary
          2. 13.1.5.4.2 DPLL_VIDEO Register Description
        5. 13.1.5.5 DPLL_HDMI Registers
          1. 13.1.5.5.1 DPLL_HDMI Registers Mapping Summary
          2. 13.1.5.5.2 DPLL_HDMI Register Description
        6. 13.1.5.6 HDMI_WP Registers
          1. 13.1.5.6.1 HDMI_WP Registers Mapping Summary
          2. 13.1.5.6.2 HDMI_WP Register Description
        7. 13.1.5.7 DSI Registers
          1. 13.1.5.7.1 DSI Register Summary
          2. 13.1.5.7.2 DSI Register Description
    2. 13.2 Display Controller
      1. 13.2.1 DISPC Overview
      2. 13.2.2 DISPC Environment
        1. 13.2.2.1 DISPC LCD Output and Data Format for the Parallel Interface
        2. 13.2.2.2 DISPC Transaction Timing Diagrams
        3. 13.2.2.3 DISPC TV Output and Data Format for the Parallel Interface
      3. 13.2.3 DISPC Integration
      4. 13.2.4 DISPC Functional Description
        1. 13.2.4.1  DISPC Clock Configuration
        2. 13.2.4.2  DISPC Software Reset
        3. 13.2.4.3  DISPC Power Management
          1. 13.2.4.3.1 DISPC Idle Mode
          2. 13.2.4.3.2 DISPC StandBy Mode
          3. 13.2.4.3.3 DISPC Wakeup
        4. 13.2.4.4  DISPC Interrupt Requests
        5. 13.2.4.5  DISPC DMA Requests
        6. 13.2.4.6  DISPC DMA Engine
          1. 13.2.4.6.1 DISPC Addressing and Bursts
          2. 13.2.4.6.2 DISPC Immediate Base Address Flip Mechanism
          3. 13.2.4.6.3 DISPC DMA Buffers
            1. 13.2.4.6.3.1 DISPC READ DMA Buffers (GFX and VID Pipelines)
            2. 13.2.4.6.3.2 DISPC WRITE DMA Buffer (WB Pipeline)
          4. 13.2.4.6.4 DISPC MFLAG Mechanism and Arbitration
          5. 13.2.4.6.5 DISPC Predecimation
          6. 13.2.4.6.6 DISPC Progressive-to-Interlaced Format Conversion
          7. 13.2.4.6.7 DISPC Arbitration
          8. 13.2.4.6.8 DISPC DMA Power Modes
            1. 13.2.4.6.8.1 DISPC DMA Low-Power Mode
            2. 13.2.4.6.8.2 DISPC DMA Ultralow-Power Mode
        7. 13.2.4.7  DISPC Rotation and Mirroring
        8. 13.2.4.8  DISPC Memory Format
        9. 13.2.4.9  DISPC Graphics Pipeline
          1. 13.2.4.9.1 DISPC Replication Logic
          2. 13.2.4.9.2 DISPC Antiflicker Filter
        10. 13.2.4.10 DISPC Video Pipelines
          1. 13.2.4.10.1 DISPC Replication Logic
          2. 13.2.4.10.2 DISPC VC-1 Range Mapping Unit
          3. 13.2.4.10.3 DISPC CSC Unit YUV to RGB
            1. 13.2.4.10.3.1 DISPC Chrominance Resampling
          4. 13.2.4.10.4 DISPC Scaler Unit
            1. 13.2.4.10.4.1 DISPC Scaling Algorithms
            2. 13.2.4.10.4.2 DISPC Scaling limitations
        11. 13.2.4.11 DISPC Write-Back Pipeline
          1. 13.2.4.11.1 DISPC Write-Back CSC Unit RGB to YUV
          2. 13.2.4.11.2 DISPC Write-Back Scaler Unit
          3. 13.2.4.11.3 DISPC Write-Back RGB Truncation Logic
        12. 13.2.4.12 DISPC Hardware Cursor
        13. 13.2.4.13 DISPC LCD Outputs
          1. 13.2.4.13.1 DISPC Overlay Manager
            1. 13.2.4.13.1.1 DISPC Priority Rule
            2. 13.2.4.13.1.2 DISPC Alpha Blender
            3. 13.2.4.13.1.3 DISPC Transparency Color Keys
            4. 13.2.4.13.1.4 DISPC Overlay Optimization
          2. 13.2.4.13.2 DISPC Gamma Correction Unit
          3. 13.2.4.13.3 DISPC Color Phase Rotation Unit
          4. 13.2.4.13.4 DISPC Color Space Conversion
          5. 13.2.4.13.5 DISPC BT.656 and BT.1120 Modes
            1. 13.2.4.13.5.1 Blanking
            2. 13.2.4.13.5.2 EAV and SAV
          6. 13.2.4.13.6 DISPC Active Matrix
            1. 13.2.4.13.6.1 DISPC Spatial/Temporal Dithering
            2. 13.2.4.13.6.2 DISPC Multiple Cycle Output Format (TDM)
          7. 13.2.4.13.7 DISPC Synchronized Buffer Update
          8. 13.2.4.13.8 DISPC Timing Generator and Panel Settings
        14. 13.2.4.14 DISPC TV Output
          1. 13.2.4.14.1 DISPC Overlay Manager
          2. 13.2.4.14.2 DISPC Gamma Correction Unit
          3. 13.2.4.14.3 DISPC Synchronized Buffer Update
          4. 13.2.4.14.4 DISPC Timing and TV Format Settings
        15. 13.2.4.15 DISPC Frame Width Considerations
        16. 13.2.4.16 DISPC Extended 3D Support
          1. 13.2.4.16.1 DISPC Extended 3D Support - Line Alternative Format
          2. 13.2.4.16.2 2627
          3. 13.2.4.16.3 DISPC Extended 3D Support - Frame Packing Format Format
          4. 13.2.4.16.4 DISPC Extended 3D Support - DLP 3D Format
        17. 13.2.4.17 DISPC Shadow Registers
      5. 13.2.5 DISPC Programming Guide
        1. 13.2.5.1 DISPC Low-Level Programming Models
          1. 13.2.5.1.1 DISPC Global Initialization
            1. 13.2.5.1.1.1 DISPC Surrounding Modules Global Initialization
          2. 13.2.5.1.2 DISPC Operational Modes Configuration
            1. 13.2.5.1.2.1 DISPC DMA Configuration
              1. 13.2.5.1.2.1.1 DISPC Main Sequence – DISPC DMA Channel Configuration
            2. 13.2.5.1.2.2 DISPC GFX Pipeline Configuration
              1. 13.2.5.1.2.2.1 DISPC Main Sequence – Configure the GFX Pipeline
              2. 13.2.5.1.2.2.2 DISPC Subsequence – Configure the GFX Window
              3. 13.2.5.1.2.2.3 DISPC Subsequence – Configure the GFX Pipeline Processing
              4. 13.2.5.1.2.2.4 DISPC Subsequence – Configure the GFX Pipeline Layer Output
            3. 13.2.5.1.2.3 DISPC Video Pipeline Configuration
              1. 13.2.5.1.2.3.1 DISPC Main Sequence – Configure the Video Pipeline
              2. 13.2.5.1.2.3.2 DISPC Subsequence – Configure the Video Window
              3. 13.2.5.1.2.3.3 DISPC Subsequence – Configure the Video Pipeline Processing
              4. 13.2.5.1.2.3.4 DISPC Subsequence – Configure the VC-1 Range Mapping
              5. 13.2.5.1.2.3.5 DISPC Subsequence – Configure the Video Color Space Conversion
              6. 13.2.5.1.2.3.6 DISPC Subsequence – Configure the Video Scaler Unit
              7. 13.2.5.1.2.3.7 DISPC Subsequence – Configure the Video Pipeline Layer Output
            4. 13.2.5.1.2.4 DISPC WB Pipeline Configuration
              1. 13.2.5.1.2.4.1 DISPC Main Sequence – Configure the WB Pipeline
              2. 13.2.5.1.2.4.2 DISPC Subsequence – Configure the Capture Window
              3. 13.2.5.1.2.4.3 DISPC Subsequence – Configure the WB Scaler Unit
              4. 13.2.5.1.2.4.4 DISPC Subsequence – Configure the WB Color Space Conversion Unit
            5. 13.2.5.1.2.5 DISPC LCD Output Configuration
              1. 13.2.5.1.2.5.1 DISPC Main Sequence – Configure the LCD Output
              2. 13.2.5.1.2.5.2 DISPC Subsequence – Configure the Overlay Manager
              3. 13.2.5.1.2.5.3 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
              4. 13.2.5.1.2.5.4 DISPC Subsequence – Configure the Color Phase Rotation
              5. 13.2.5.1.2.5.5 DISPC Subsequence – Configure the LCD Panel Timings and Parameters
              6. 13.2.5.1.2.5.6 DISPC Subsequence – Configure BT.656 or BT.1120 Mode
            6. 13.2.5.1.2.6 DISPC TV Output Configuration
              1. 13.2.5.1.2.6.1 DISPC Main Sequence – Configure the TV Output
                1. 13.2.5.1.2.6.1.1 DISPC Subsequence – Configure the TV Overlay Manager
                2. 13.2.5.1.2.6.1.2 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
                3. 13.2.5.1.2.6.1.3 DISPC Subsequence – Configure the TV Panel Timings and Parameters
      6. 13.2.6 DISPC Register Manual
        1. 13.2.6.1 DISPC Instance Summary
        2. 13.2.6.2 DISPC Logical Register Mapping
        3. 13.2.6.3 DISPC Registers
          1. 13.2.6.3.1 DISPC Register Summary
          2. 13.2.6.3.2 DISPC Register Description
    3. 13.3 High-Definition Multimedia Interface
      1. 13.3.1 HDMI Overview
        1. 13.3.1.1 HDMI Main Features
        2. 13.3.1.2 HDMI Video Formats and Timings
          1. 13.3.1.2.1 HDMI CEA-861-D Video Formats and Timings
          2. 13.3.1.2.2 VESA DMT Video Formats and Timings
  16. 143D Graphics Accelerator
    1. 14.1 GPU Overview
      1. 14.1.1 GPU Features Overview
      2. 14.1.2 Graphics Feature Overview
    2. 14.2 GPU Integration
    3. 14.3 GPU Functional Description
      1. 14.3.1 GPU Block Diagram
      2. 14.3.2 GPU Clock Configuration
      3. 14.3.3 GPU Software Reset
      4. 14.3.4 GPU Power Management
      5. 14.3.5 GPU Thermal Management
      6. 14.3.6 GPU Interrupt Requests
    4. 14.4 GPU Register Manual
      1. 14.4.1 GPU Instance Summary
      2. 14.4.2 GPU Registers
        1. 14.4.2.1 GPU_WRAPPER Register Summary
        2. 14.4.2.2 GPU_WRAPPER Register Description
  17. 152D Graphics Accelerator
    1. 15.1 BB2D Overview
      1. 15.1.1 BB2D Key Features Overview
    2. 15.2 BB2D Integration
    3. 15.3 BB2D Functional Description
      1. 15.3.1 BB2D Block Diagram
      2. 15.3.2 BB2D Clock Configuration
      3. 15.3.3 BB2D Software Reset
      4. 15.3.4 BB2D Power Management
    4. 15.4 BB2D Register Manual
      1. 15.4.1 BB2D Instance Summary
      2. 15.4.2 BB2D Registers
        1. 15.4.2.1 BB2D Register Summary
        2. 15.4.2.2 BB2D Register Description
  18. 16Interconnect
    1. 16.1 Interconnect Overview
      1. 16.1.1 Terminology
      2. 16.1.2 Architecture Overview
    2. 16.2 L3_MAIN Interconnect
      1. 16.2.1 L3_MAIN Interconnect Overview
      2. 16.2.2 L3_MAIN Interconnect Integration
      3. 16.2.3 L3_MAIN Interconnect Functional Description
        1. 16.2.3.1 Module Use in L3_MAIN Interconnect
        2. 16.2.3.2 Module Distribution
          1. 16.2.3.2.1 L3_MAIN Interconnect Agents
          2. 16.2.3.2.2 L3_MAIN Connectivity Matrix
            1. 16.2.3.2.2.1 Clock Domain Mapping of the L3_MAIN Interconnect Modules
            2. 16.2.3.2.2.2 2724
          3. 16.2.3.2.3 Master NIU Identification
        3. 16.2.3.3 Bandwidth Regulators
        4. 16.2.3.4 Bandwidth Limiters
        5. 16.2.3.5 Flag Muxing
          1. 16.2.3.5.1 Flag Mux Time-out
        6. 16.2.3.6 Statistic Collectors Group
        7. 16.2.3.7 L3_MAIN Protection and Firewalls
          1. 16.2.3.7.1 L3_MAIN Firewall Reset
            1. 16.2.3.7.1.1 L3_MAIN Firewall – Exported Reset Values
          2. 16.2.3.7.2 Power Management
          3. 16.2.3.7.3 L3_MAIN Firewall Functionality
            1. 16.2.3.7.3.1 Protection Regions
            2. 16.2.3.7.3.2 L3_MAIN Firewall Registers Overview
            3. 16.2.3.7.3.3 Protection Mechanism per Region Examples
            4. 16.2.3.7.3.4 L3_MAIN Firewall Error Logging
            5. 16.2.3.7.3.5 L3_MAIN Firewall Default Configuration
        8. 16.2.3.8 L3_MAIN Interconnect Error Handling
          1. 16.2.3.8.1 Global Error-Routing Scheme
          2. 16.2.3.8.2 Slave NIU Error Logging
          3. 16.2.3.8.3 Flag Mux Error Logging
          4. 16.2.3.8.4 Severity Level of Standard and Custom Errors
          5. 16.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN
      4. 16.2.4 L3_MAIN Interconnect Programming Guide
        1. 16.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models
          1. 16.2.4.1.1 Global Initialization
            1. 16.2.4.1.1.1 Global Initialization of Surrounding Modules
        2. 16.2.4.2 Operational Modes Configuration
          1. 16.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode
            1. 16.2.4.2.1.1 Main Sequence: L3_MAIN Interconnect Error Analysis Mode
              1. 16.2.4.2.1.1.1 Subsequence: L3_MAIN Custom Error Identification
              2. 16.2.4.2.1.1.2 Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
              3. 16.2.4.2.1.1.3 Subsequence: L3_MAIN Interconnect Standard Error Identification
              4. 16.2.4.2.1.1.4 Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
      5. 16.2.5 L3_MAIN Interconnect Register Manual
        1. 16.2.5.1 L3_MAIN Register Group Summary
          1. 16.2.5.1.1 L3_MAIN Firewall Registers Summary and Description
            1. 16.2.5.1.1.1 L3_MAIN Firewall Registers Summary
            2. 16.2.5.1.1.2 L3_MAIN Firewall Registers Description
          2. 16.2.5.1.2 L3_MAIN Host Register Summary and Description
            1. 16.2.5.1.2.1 L3_MAIN HOST Register Summary
            2. 16.2.5.1.2.2 L3_MAIN HOST Register Description
          3. 16.2.5.1.3 L3_MAIN TARG Register Summary and Description
            1. 16.2.5.1.3.1 L3_MAIN TARG Register Summary
            2. 16.2.5.1.3.2 L3_MAIN TARG Register Description
          4. 16.2.5.1.4 L3_MAIN FLAGMUX Registers Summary and Description
            1. 16.2.5.1.4.1 L3_MAIN FLAGMUX Registers Summary
            2. 16.2.5.1.4.2 L3_MAIN FLAGMUX Rebisters Description
          5. 16.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
            1. 16.2.5.1.5.1 L3_MAIN FLAGMUX CLK1MERGE Registers Summary
            2. 16.2.5.1.5.2 L3_MAIN FLAGMUX CLK1MERGE Registers Description
          6. 16.2.5.1.6 L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
            1. 16.2.5.1.6.1 L3_MAIN FLAGMUX TIMEOUT Registers Summary
            2. 16.2.5.1.6.2 L3_MAIN FLAGMUX TIMEOUT Registers Description
          7. 16.2.5.1.7 L3_MAIN BW Regulator Register Summary and Description
            1. 16.2.5.1.7.1 L3_MAIN BW_REGULATOR Register Summary
            2. 16.2.5.1.7.2 L3_MAIN BW_REGULATOR Register Description
          8. 16.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description
            1. 16.2.5.1.8.1 L3_MAIN BW Limiter Register Summary
            2. 16.2.5.1.8.2 L3_MAIN BW Limiter Register Description
          9. 16.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description
            1. 16.2.5.1.9.1 L3_MAIN STATCOLL Register Summary
            2. 16.2.5.1.9.2 L3_MAIN STATCOLL Register Description
    3. 16.3 L4 Interconnects
      1. 16.3.1 L4 Interconnect Overview
      2. 16.3.2 L4 Interconnect Integration
      3. 16.3.3 L4 Interconnect Functional Description
        1. 16.3.3.1 Module Distribution
          1. 16.3.3.1.1 L4_PER1 Interconnect Agents
          2. 16.3.3.1.2 L4_PER2 Interconnect Agents
          3. 16.3.3.1.3 L4_PER3 Interconnect Agents
          4. 16.3.3.1.4 L4_CFG Interconnect Agents
          5. 16.3.3.1.5 L4_WKUP Interconnect Agents
        2. 16.3.3.2 Power Management
        3. 16.3.3.3 L4 Firewalls
          1. 16.3.3.3.1 Protection Group
          2. 16.3.3.3.2 Segments and Regions
          3. 16.3.3.3.3 L4 Firewall Address and Protection Register Settings
        4. 16.3.3.4 L4 Error Detection and Reporting
          1. 16.3.3.4.1 IA and TA Error Detection and Logging
          2. 16.3.3.4.2 Time-Out
          3. 16.3.3.4.3 Error Reporting
          4. 16.3.3.4.4 Error Recovery
          5. 16.3.3.4.5 Firewall Error Logging in the Control Module
      4. 16.3.4 L4 Interconnect Programming Guide
        1. 16.3.4.1 L4 Interconnect Low-level Programming Models
          1. 16.3.4.1.1 Global Initialization
            1. 16.3.4.1.1.1 Surrounding Modules Global Initialization
          2. 16.3.4.1.2 Operational Modes Configuration
            1. 16.3.4.1.2.1 L4 Interconnect Error Analysis Mode
              1. 16.3.4.1.2.1.1 Main Sequence: L4 Interconnect Error Analysis Mode
              2. 16.3.4.1.2.1.2 Subsequence: L4 Interconnect Protection Violation Error Identification
              3. 16.3.4.1.2.1.3 Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
              4. 16.3.4.1.2.1.4 Subsequence: L4 Interconnect Reset TA and Module
            2. 16.3.4.1.2.2 L4 Interconnect Time-Out Configuration Mode
              1. 16.3.4.1.2.2.1 Main Sequence: L4 Interconnect Time-Out Configuration Mode
            3. 16.3.4.1.2.3 L4 Interconnect Firewall Configuration Mode
              1. 16.3.4.1.2.3.1 Main Sequence: L4 Interconnect Firewall Configuration Mode
      5. 16.3.5 L4 Interconnects Register Manual
        1. 16.3.5.1 L4 Interconnects Instance Summary
        2. 16.3.5.2 L4 Initiator Agent (L4 IA)
          1. 16.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary
          2. 16.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description
        3. 16.3.5.3 L4 Target Agent (L4 TA)
          1. 16.3.5.3.1 L4 Target Agent (L4 TA) Register Summary
          2. 16.3.5.3.2 L4 Target Agent (L4 TA) Register Description
        4. 16.3.5.4 L4 Link Agent (L4 LA)
          1. 16.3.5.4.1 L4 Link Agent (L4 LA) Register Summary
          2. 16.3.5.4.2 L4 Link Agent (L4 LA) Register Description
        5. 16.3.5.5 L4 Address Protection (L4 AP)
          1. 16.3.5.5.1 L4 Address Protection (L4 AP) Register Summary
          2. 16.3.5.5.2 L4 Address Protection (L4 AP) Register Description
  19. 17Memory Subsystem
    1. 17.1 Memory Subsystem Overview
      1. 17.1.1 DMM Overview
      2. 17.1.2 TILER Overview
      3. 17.1.3 EMIF Overview
      4. 17.1.4 GPMC Overview
      5. 17.1.5 ELM Overview
      6. 17.1.6 OCM Overview
    2. 17.2 Dynamic Memory Manager
      1. 17.2.1 DMM Overview
      2. 17.2.2 DMM Integration
        1. 17.2.2.1 DMM Configuration
      3. 17.2.3 DMM Functional Description
        1. 17.2.3.1 DMM Block Diagram
        2. 17.2.3.2 DMM Clock Configuration
        3. 17.2.3.3 DMM Power Management
        4. 17.2.3.4 DMM Interrupt Requests
        5. 17.2.3.5 DMM
          1. 17.2.3.5.1 DMM Concepts
            1. 17.2.3.5.1.1 Dynamic Mapping
            2. 17.2.3.5.1.2 Address Mapping
            3. 17.2.3.5.1.3 Address Translation
              1. 17.2.3.5.1.3.1 PAT View Mappings
              2. 17.2.3.5.1.3.2 PAT View Map Base Address
              3. 17.2.3.5.1.3.3 PAT Views
                1. 17.2.3.5.1.3.3.1 PAT Direct Access Translation
                2. 17.2.3.5.1.3.3.2 PAT Indirect Access Translation
                3. 17.2.3.5.1.3.3.3 PAT View Configuration
                4. 17.2.3.5.1.3.3.4 PAT Address Translation LUT
                5. 17.2.3.5.1.3.3.5 Direct Access to the PAT Table Vectors
                6. 17.2.3.5.1.3.3.6 Automatic Refill Through the Refill Engines
          2. 17.2.3.5.2 DMM Transaction Flows
            1. 17.2.3.5.2.1 Nontiled Transaction Flow
            2. 17.2.3.5.2.2 Tiled Transaction Flow
          3. 17.2.3.5.3 DMM Internal Macro-Architecture
            1. 17.2.3.5.3.1 LISA Description
            2. 17.2.3.5.3.2 PAT Description
            3. 17.2.3.5.3.3 PEG Description
            4. 17.2.3.5.3.4 LISA Interconnect Arbitration
            5. 17.2.3.5.3.5 ROBIN Description
            6. 17.2.3.5.3.6 TILER Description
        6. 17.2.3.6 TILER
          1. 17.2.3.6.1 TILER Concepts
            1. 17.2.3.6.1.1 TILER Rationale
              1. 17.2.3.6.1.1.1 The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
              2. 17.2.3.6.1.1.2 A View is a 512-MiB Virtual Address Space Composed of Four Containers
              3. 17.2.3.6.1.1.3 A Container is a 128-MiB Virtual Address Space
              4. 17.2.3.6.1.1.4 A Page is a 4-kiB Virtual Address Space
              5. 17.2.3.6.1.1.5 A Tile is a 1-kiB Address Space
              6. 17.2.3.6.1.1.6 2885
              7. 17.2.3.6.1.1.7 A Subtile is a 128-Bit Address Space
            2. 17.2.3.6.1.2 TILER Modes
              1. 17.2.3.6.1.2.1 Bypass Mode
              2. 17.2.3.6.1.2.2 Page Mode
              3. 17.2.3.6.1.2.3 Tiled Mode
            3. 17.2.3.6.1.3 Object Container Definition
            4. 17.2.3.6.1.4 Page Definition
              1. 17.2.3.6.1.4.1 Container Geometry With 4-kiB Pages
              2. 17.2.3.6.1.4.2 Container Geometry and Page Mapping Summary
            5. 17.2.3.6.1.5 Orientation
            6. 17.2.3.6.1.6 Tile Definition
            7. 17.2.3.6.1.7 Subtiles
              1. 17.2.3.6.1.7.1 Subtiling Definition
            8. 17.2.3.6.1.8 TILER Virtual Addressing
              1. 17.2.3.6.1.8.1 Page Mode Virtual Addressing and Characteristics
              2. 17.2.3.6.1.8.2 Tiled Mode Virtual Addressing and Characteristics
              3. 17.2.3.6.1.8.3 Element Ordering in the TILER Container
                1. 17.2.3.6.1.8.3.1 Natural View or 0-Degree View (Orientation 0)
                2. 17.2.3.6.1.8.3.2 0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
                3. 17.2.3.6.1.8.3.3 0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
                4. 17.2.3.6.1.8.3.4 180-Degree View (Orientation 3)
                5. 17.2.3.6.1.8.3.5 90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
                6. 17.2.3.6.1.8.3.6 270-Degree View (Orientation 5)
                7. 17.2.3.6.1.8.3.7 90-Degree View (Orientation 6)
                8. 17.2.3.6.1.8.3.8 90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
          2. 17.2.3.6.2 TILER Macro-Architecture
          3. 17.2.3.6.3 TILER Guidelines for Initiators
            1. 17.2.3.6.3.1 Buffered Raster-Based Initiators
              1. 17.2.3.6.3.1.1 Buffer Size
              2. 17.2.3.6.3.1.2 Performance
      4. 17.2.4 DMM Use Cases and Tips
        1. 17.2.4.1 PAT Use Cases
          1. 17.2.4.1.1 Simple Manual Area Refill
          2. 17.2.4.1.2 Single Auto-Configured Area Refill
          3. 17.2.4.1.3 Chained Auto-Configured Area Refill
          4. 17.2.4.1.4 Synchronized Auto-Configured Area Refill
          5. 17.2.4.1.5 Cyclic Synchronized Auto-Configured Area Refill
        2. 17.2.4.2 Addressing Management with LISA
          1. 17.2.4.2.1 Case 1: Use of One Memory Controller
          2. 17.2.4.2.2 Case 2: Use of Two Memory Controllers
            1. 17.2.4.2.2.1 Address Upper Bits Shifting
      5. 17.2.5 DMM Basic Programming Model
        1. 17.2.5.1 Global Initialization
        2. 17.2.5.2 DMM Module Global Initialization
        3. 17.2.5.3 DMM Operational Modes Configuration
          1. 17.2.5.3.1 Different Operational Modes
          2. 17.2.5.3.2 Configuration Settings and LUT Refill
          3. 17.2.5.3.3 Interleaving Settings
          4. 17.2.5.3.4 Aliased Tiled View Orientation Settings and LUT Refill
          5. 17.2.5.3.5 Priority Settings
          6. 17.2.5.3.6 Error Handling
          7. 17.2.5.3.7 PAT Programming Model
            1. 17.2.5.3.7.1 PAT in Direct Translation Mode
            2. 17.2.5.3.7.2 PAT in Indirect Translation Mode
        4. 17.2.5.4 Addressing an Object in Tiled Mode
          1. 17.2.5.4.1 Frame-Buffer Addressing
          2. 17.2.5.4.2 TILER Page Mapping
        5. 17.2.5.5 Addressing an Object in Page Mode
        6. 17.2.5.6 Sharing Containers Between Different Modes
      6. 17.2.6 DMM Register Manual
        1. 17.2.6.1 DMM Instance Summary
        2. 17.2.6.2 DMM Registers
          1. 17.2.6.2.1 DMM Register Summary
          2. 17.2.6.2.2 DMM Register Description
    3. 17.3 EMIF Controller
      1. 17.3.1 EMIF Controller Overview
      2. 17.3.2 EMIF Module Environment
      3. 17.3.3 EMIF Module Integration
      4. 17.3.4 EMIF Functional Description
        1. 17.3.4.1  Block Diagram
          1. 17.3.4.1.1 Local Interface
          2. 17.3.4.1.2 FIFO Description
          3. 17.3.4.1.3 MPU Port Restrictions
          4. 17.3.4.1.4 Arbitration of Commands in the Command FIFO
        2. 17.3.4.2  Clock Management
          1. 17.3.4.2.1 EMIF_FICLK Overview
          2. 17.3.4.2.2 EMIF Dependency on MPU Clock Rate
        3. 17.3.4.3  Reset
        4. 17.3.4.4  System Power Management
          1. 17.3.4.4.1 Power-Down Mode
          2. 17.3.4.4.2 Self-Refresh Mode
        5. 17.3.4.5  Interrupt Requests
        6. 17.3.4.6  SDRAM Refresh Scheduling
        7. 17.3.4.7  SDRAM Initialization
          1. 17.3.4.7.1 DDR2 SDRAM Initialization
          2. 17.3.4.7.2 DDR3 SDRAM Initialization
        8. 17.3.4.8  DDR3 Read-Write Leveling
          1. 17.3.4.8.1 Full Leveling
          2. 17.3.4.8.2 Software Leveling
        9. 17.3.4.9  EMIF Access Cycles
        10. 17.3.4.10 Turnaround Time
        11. 17.3.4.11 PHY DLL Calibration
        12. 17.3.4.12 SDRAM Address Mapping
          1. 17.3.4.12.1 Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
          2. 17.3.4.12.2 Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
          3. 17.3.4.12.3 Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
          4. 17.3.4.12.4 Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
          5. 17.3.4.12.5 Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
          6. 17.3.4.12.6 Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
          7. 17.3.4.12.7 Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
          8. 17.3.4.12.8 2986
          9. 17.3.4.12.9 Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
        13. 17.3.4.13 DDR3 Output Impedance Calibration
        14. 17.3.4.14 Error Correction And Detection Feature
          1. 17.3.4.14.1 Read-Modify-Write Module
        15. 17.3.4.15 Class of Service
        16. 17.3.4.16 Performance Counters
          1. 17.3.4.16.1 Performance Counters General Examples
        17. 17.3.4.17 Forcing CKE to tri-state
      5. 17.3.5 EMIF Programming Guide
        1. 17.3.5.1 EMIF Low-Level Programming Models
          1. 17.3.5.1.1 Global Initialization
            1. 17.3.5.1.1.1 EMIF Configuration Sequence
          2. 17.3.5.1.2 Operational Modes Configuration
            1. 17.3.5.1.2.1 EMIF Output Impedance Calibration Mode
            2. 17.3.5.1.2.2 EMIF SDRAM Self-Refresh
            3. 17.3.5.1.2.3 EMIF SDRAM Power-Down Mode
            4. 17.3.5.1.2.4 EMIF ECC Configuration
      6. 17.3.6 EMIF Register Manual
        1. 17.3.6.1 EMIF Instance Summary
        2. 17.3.6.2 EMIF Registers
          1. 17.3.6.2.1 EMIF Register Summary
          2. 17.3.6.2.2 EMIF Register Description
    4. 17.4 General-Purpose Memory Controller
      1. 17.4.1 GPMC Overview
      2. 17.4.2 GPMC Environment
        1. 17.4.2.1 GPMC Modes
        2. 17.4.2.2 GPMC Signals
      3. 17.4.3 GPMC Integration
      4. 17.4.4 GPMC Functional Description
        1. 17.4.4.1  GPMC Block Diagram
        2. 17.4.4.2  GPMC Clock Configuration
        3. 17.4.4.3  GPMC Software Reset
        4. 17.4.4.4  GPMC Power Management
        5. 17.4.4.5  GPMC Interrupt Requests
        6. 17.4.4.6  L3 Interconnect Interface
        7. 17.4.4.7  GPMC Address and Data Bus
          1. 17.4.4.7.1 GPMC I/O Configuration Setting
          2. 17.4.4.7.2 GPMC CS0 Default Configuration at Device Reset
        8. 17.4.4.8  Address Decoder and Chip-Select Configuration
          1. 17.4.4.8.1 Chip-Select Base Address and Region Size
          2. 17.4.4.8.2 Access Protocol
            1. 17.4.4.8.2.1 Supported Devices
            2. 17.4.4.8.2.2 Access Size Adaptation and Device Width
            3. 17.4.4.8.2.3 Address/Data-Multiplexing Interface
          3. 17.4.4.8.3 External Signals
            1. 17.4.4.8.3.1 Wait Pin Monitoring Control
              1. 17.4.4.8.3.1.1 Wait Monitoring During Asynchronous Read Access
              2. 17.4.4.8.3.1.2 Wait Monitoring During Asynchronous Write Access
              3. 17.4.4.8.3.1.3 Wait Monitoring During Synchronous Read Access
              4. 17.4.4.8.3.1.4 Wait Monitoring During Synchronous Write Access
              5. 17.4.4.8.3.1.5 Wait With NAND Device
              6. 17.4.4.8.3.1.6 Idle Cycle Control Between Successive Accesses
                1. 17.4.4.8.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                2. 17.4.4.8.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                3. 17.4.4.8.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
              7. 17.4.4.8.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
            2. 17.4.4.8.3.2 Reset
            3. 17.4.4.8.3.3 Byte Enable (nBE1/nBE0)
          4. 17.4.4.8.4 Error Handling
        9. 17.4.4.9  Timing Setting
          1. 17.4.4.9.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
          2. 17.4.4.9.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
          3. 17.4.4.9.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
          4. 17.4.4.9.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
          5. 17.4.4.9.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
          6. 17.4.4.9.6  GPMC_CLK
          7. 17.4.4.9.7  GPMC_CLK and Control Signals Setup and Hold
          8. 17.4.4.9.8  Access Time (RDACCESSTIME / WRACCESSTIME)
            1. 17.4.4.9.8.1 Access Time on Read Access
            2. 17.4.4.9.8.2 Access Time on Write Access
          9. 17.4.4.9.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
            1. 17.4.4.9.9.1 Page Burst Access Time on Read Access
            2. 17.4.4.9.9.2 Page Burst Access Time on Write Access
          10. 17.4.4.9.10 Bus Keeping Support
        10. 17.4.4.10 NOR Access Description
          1. 17.4.4.10.1 Asynchronous Access Description
            1. 17.4.4.10.1.1 Access on Address/Data Multiplexed Devices
              1. 17.4.4.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
              2. 17.4.4.10.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
              3. 17.4.4.10.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
            2. 17.4.4.10.1.2 Access on Address/Address/Data-Multiplexed Devices
              1. 17.4.4.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
              2. 17.4.4.10.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
              3. 17.4.4.10.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
          2. 17.4.4.10.2 Synchronous Access Description
            1. 17.4.4.10.2.1 Synchronous Single Read
            2. 17.4.4.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
            3. 17.4.4.10.2.3 Synchronous Single Write
            4. 17.4.4.10.2.4 Synchronous Multiple (Burst) Write
          3. 17.4.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
            1. 17.4.4.10.3.1 Asynchronous Single-Read Operation on Nonmultiplexed Device
            2. 17.4.4.10.3.2 Asynchronous Single-Write Operation on Nonmultiplexed Device
            3. 17.4.4.10.3.3 Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
            4. 17.4.4.10.3.4 Synchronous Operations on a Nonmultiplexed Device
          4. 17.4.4.10.4 Page and Burst Support
          5. 17.4.4.10.5 System Burst vs External Device Burst Support
        11. 17.4.4.11 pSRAM Access Specificities
        12. 17.4.4.12 NAND Access Description
          1. 17.4.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
            1. 17.4.4.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
            2. 17.4.4.12.1.2 NAND Device Command and Address Phase Control
            3. 17.4.4.12.1.3 Command Latch Cycle
            4. 17.4.4.12.1.4 Address Latch Cycle
            5. 17.4.4.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
            6. 17.4.4.12.1.6 NAND Device General Chip-Select Timing Control Requirement
            7. 17.4.4.12.1.7 Read and Write Access Size Adaptation
              1. 17.4.4.12.1.7.1 8-Bit-Wide NAND Device
              2. 17.4.4.12.1.7.2 16-Bit-Wide NAND Device
          2. 17.4.4.12.2 NAND Device-Ready Pin
            1. 17.4.4.12.2.1 Ready Pin Monitored by Software Polling
            2. 17.4.4.12.2.2 Ready Pin Monitored by Hardware Interrupt
          3. 17.4.4.12.3 ECC Calculator
            1. 17.4.4.12.3.1 Hamming Code
              1. 17.4.4.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size
              2. 17.4.4.12.3.1.2 ECC Enabling
              3. 17.4.4.12.3.1.3 ECC Computation
              4. 17.4.4.12.3.1.4 ECC Comparison and Correction
              5. 17.4.4.12.3.1.5 ECC Calculation Based on 8-Bit Word
              6. 17.4.4.12.3.1.6 ECC Calculation Based on 16-Bit Word
            2. 17.4.4.12.3.2 BCH Code
              1. 17.4.4.12.3.2.1 Requirements
              2. 17.4.4.12.3.2.2 Memory Mapping of BCH Codeword
                1. 17.4.4.12.3.2.2.1 Memory Mapping of Data Message
                2. 17.4.4.12.3.2.2.2 Memory-Mapping of the ECC
                3. 17.4.4.12.3.2.2.3 Wrapping Modes
                  1. 4.4.12.3.2.2.3.1  Manual Mode (0x0)
                  2. 4.4.12.3.2.2.3.2  Mode 0x1
                  3. 4.4.12.3.2.2.3.3  Mode 0xA (10)
                  4. 4.4.12.3.2.2.3.4  Mode 0x2
                  5. 4.4.12.3.2.2.3.5  Mode 0x3
                  6. 4.4.12.3.2.2.3.6  Mode 0x7
                  7. 4.4.12.3.2.2.3.7  Mode 0x8
                  8. 4.4.12.3.2.2.3.8  Mode 0x4
                  9. 4.4.12.3.2.2.3.9  Mode 0x9
                  10. 4.4.12.3.2.2.3.10 Mode 0x5
                  11. 4.4.12.3.2.2.3.11 Mode 0xB (11)
                  12. 4.4.12.3.2.2.3.12 Mode 0x6
              3. 17.4.4.12.3.2.3 Supported NAND Page Mappings and ECC Schemes
                1. 17.4.4.12.3.2.3.1 Per-Sector Spare Mappings
                2. 17.4.4.12.3.2.3.2 Pooled Spare Mapping
                3. 17.4.4.12.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
          4. 17.4.4.12.4 Prefetch and Write-Posting Engine
            1. 17.4.4.12.4.1 General Facts About the Engine Configuration
            2. 17.4.4.12.4.2 Prefetch Mode
            3. 17.4.4.12.4.3 FIFO Control in Prefetch Mode
            4. 17.4.4.12.4.4 Write-Posting Mode
            5. 17.4.4.12.4.5 FIFO Control in Write-Posting Mode
            6. 17.4.4.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
            7. 17.4.4.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
      5. 17.4.5 GPMC Basic Programming Model
        1. 17.4.5.1 GPMC High-Level Programming Model Overview
        2. 17.4.5.2 GPMC Initialization
        3. 17.4.5.3 GPMC Configuration in NOR Mode
        4. 17.4.5.4 GPMC Configuration in NAND Mode
        5. 17.4.5.5 Set Memory Access
        6. 17.4.5.6 GPMC Timing Parameters
          1. 17.4.5.6.1 GPMC Timing Parameters Formulas
            1. 17.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
            2. 17.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
            3. 17.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      6. 17.4.6 GPMC Use Cases and Tips
        1. 17.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses
          1. 17.4.6.1.1 External Memory Attached to the GPMC Module
          2. 17.4.6.1.2 Typical GPMC Setup
            1. 17.4.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access
            2. 17.4.6.1.2.2 GPMC Configuration for Asynchronous Read Access
            3. 17.4.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
        2. 17.4.6.2 How to Choose a Suitable Memory to Use With the GPMC
          1. 17.4.6.2.1 Supported Memories or Devices
            1. 17.4.6.2.1.1 Memory Pin Multiplexing
            2. 17.4.6.2.1.2 NAND Interface Protocol
            3. 17.4.6.2.1.3 NOR Interface Protocol
            4. 17.4.6.2.1.4 Other Technologies
            5. 17.4.6.2.1.5 Supported Protocols
          2. 17.4.6.2.2 GPMC Features and Settings
      7. 17.4.7 GPMC Register Manual
        1. 17.4.7.1 GPMC Register Summary
        2. 17.4.7.2 GPMC Register Descriptions
    5. 17.5 Error Location Module
      1. 17.5.1 Error Location Module Overview
      2. 17.5.2 ELM Integration
      3. 17.5.3 ELM Functional Description
        1. 17.5.3.1 ELM Software Reset
        2. 17.5.3.2 ELM Power Management
        3. 17.5.3.3 ELM Interrupt Requests
        4. 17.5.3.4 Processing Initialization
        5. 17.5.3.5 Processing Sequence
        6. 17.5.3.6 Processing Completion
      4. 17.5.4 ELM Basic Programming Model
        1. 17.5.4.1 ELM Low-Level Programming Model
          1. 17.5.4.1.1 Processing Initialization
          2. 17.5.4.1.2 Read Results
          3. 17.5.4.1.3 3179
        2. 17.5.4.2 Use Case: ELM Used in Continuous Mode
        3. 17.5.4.3 Use Case: ELM Used in Page Mode
      5. 17.5.5 ELM Register Manual
        1. 17.5.5.1 ELM Instance Summary
        2. 17.5.5.2 ELM Registers
          1. 17.5.5.2.1 ELM Register Summary
          2. 17.5.5.2.2 ELM Register Description
    6. 17.6 On-Chip Memory (OCM) Subsystem
      1. 17.6.1 OCM Subsystem Overview
      2. 17.6.2 OCM Subsystem Integration
      3. 17.6.3 OCM Subsystem Functional Desctiption
        1. 17.6.3.1  Block Diagram
        2. 17.6.3.2  Resets
        3. 17.6.3.3  Clock Management
        4. 17.6.3.4  Interrupt Requests
        5. 17.6.3.5  OCM Subsystem Memory Regions
        6. 17.6.3.6  OCM Controller Modes Of Operation
        7. 17.6.3.7  ECC Associated FIFOs
        8. 17.6.3.8  ECC Counters And Corrected Bit Distribution Register
        9. 17.6.3.9  ECC Support
        10. 17.6.3.10 Circular Buffer (CBUF) Support
        11. 17.6.3.11 CBUF Mode Error Handling
          1. 17.6.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space
          2. 17.6.3.11.2 VBUF Access Not Starting At The Base Address
          3. 17.6.3.11.3 Illegal Address Change Between Two Same Type Accesses
          4. 17.6.3.11.4 Illegal Frame SIze (Short Frame Detection)
          5. 17.6.3.11.5 CBUF Overflow
          6. 17.6.3.11.6 CBUF Underflow
        12. 17.6.3.12 Status Reporting
      4. 17.6.4 OCM Subsystem Register Manual
        1. 17.6.4.1 OCM Subsystem Instance Summary
        2. 17.6.4.2 OCM Subsystem Registers
          1. 17.6.4.2.1 OCM Subsystem Register Summary
          2. 17.6.4.2.2 OCM Subsystem Register Description
  20. 18DMA Controllers
    1. 18.1 System DMA
      1. 18.1.1 DMA_SYSTEM Module Overview
      2. 18.1.2 DMA_SYSTEM Controller Environment
      3. 18.1.3 DMA_SYSTEM Module Integration
        1. 18.1.3.1 DMA Requests to the DMA_SYSTEM Controller
        2. 18.1.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs
      4. 18.1.4 DMA_SYSTEM Functional Description
        1. 18.1.4.1  DMA_SYSTEM Controller Power Management
        2. 18.1.4.2  DMA_SYSTEM Controller Interrupt Requests
          1. 18.1.4.2.1 Interrupt Generation
        3. 18.1.4.3  Logical Channel Transfer Overview
        4. 18.1.4.4  FIFO Queue Memory Pool
        5. 18.1.4.5  Addressing Modes
        6. 18.1.4.6  Packed Accesses
        7. 18.1.4.7  Burst Transactions
        8. 18.1.4.8  Endianism Conversion
        9. 18.1.4.9  Transfer Synchronization
          1. 18.1.4.9.1 Software Synchronization
          2. 18.1.4.9.2 Hardware Synchronization
        10. 18.1.4.10 Thread Budget Allocation
        11. 18.1.4.11 FIFO Budget Allocation
        12. 18.1.4.12 Chained Logical Channel Transfers
        13. 18.1.4.13 Reprogramming an Active Channel
        14. 18.1.4.14 Packet Synchronization
        15. 18.1.4.15 Graphics Acceleration Support
        16. 18.1.4.16 Supervisor Modes
        17. 18.1.4.17 Posted and Nonposted Writes
        18. 18.1.4.18 Disabling a Channel During Transfer
        19. 18.1.4.19 FIFO Draining Mechanism
        20. 18.1.4.20 Linked List
          1. 18.1.4.20.1 Overview
          2. 18.1.4.20.2 Link-List Transfer Profile
          3. 18.1.4.20.3 Descriptors
            1. 18.1.4.20.3.1 Type 1
            2. 18.1.4.20.3.2 Type 2
            3. 18.1.4.20.3.3 Type 3
          4. 18.1.4.20.4 Linked-List Control and Monitoring
            1. 18.1.4.20.4.1 Transfer Mode Setting
            2. 18.1.4.20.4.2 Starting a Linked List
            3. 18.1.4.20.4.3 Monitoring a Linked-List Progression
            4. 18.1.4.20.4.4 Interrupt During Linked-List Execution
            5. 18.1.4.20.4.5 Pause a Linked List
            6. 18.1.4.20.4.6 Stop a Linked List (Abort or Drain)
              1. 18.1.4.20.4.6.1 Drain
              2. 18.1.4.20.4.6.2 Abort
            7. 18.1.4.20.4.7 Status Bit Behavior
            8. 18.1.4.20.4.8 Linked-List Channel Linking
      5. 18.1.5 DMA_SYSTEM Basic Programming Model
        1. 18.1.5.1 Setup Configuration
        2. 18.1.5.2 Software-Triggered (Nonsynchronized) Transfer
        3. 18.1.5.3 Hardware-Synchronized Transfer
        4. 18.1.5.4 Synchronized Transfer Monitoring Using CDAC
        5. 18.1.5.5 Concurrent Software and Hardware Synchronization
        6. 18.1.5.6 Chained Transfer
        7. 18.1.5.7 90-Degree Clockwise Image Rotation
        8. 18.1.5.8 Graphic Operations
        9. 18.1.5.9 Linked-List Programming Guidelines
      6. 18.1.6 DMA_SYSTEM Register Manual
        1. 18.1.6.1 DMA_SYSTEM Instance Summary
        2. 18.1.6.2 DMA_SYSTEM Registers
          1. 18.1.6.2.1 DMA_SYSTEM Register Summary
          2. 18.1.6.2.2 DMA_SYSTEM Register Description
    2. 18.2 Enhanced DMA
      1. 18.2.1 EDMA Module Overview
        1. 18.2.1.1 EDMA Features
        2. 18.2.1.2 3280
        3. 18.2.1.3 EDMA Controllers Configuration
      2. 18.2.2 EDMA Controller Environment
      3. 18.2.3 EDMA Controller Integration
        1. 18.2.3.1 EDMA Requests to the EDMA Controller
      4. 18.2.4 EDMA Controller Functional Description
        1. 18.2.4.1  Block Diagram
          1. 18.2.4.1.1 Third-Party Channel Controller
          2. 18.2.4.1.2 Third-Party Transfer Controller
        2. 18.2.4.2  Types of EDMA controller Transfers
          1. 18.2.4.2.1 A-Synchronized Transfers
          2. 18.2.4.2.2 AB-Synchronized Transfers
        3. 18.2.4.3  Parameter RAM (PaRAM)
          1. 18.2.4.3.1 PaRAM
          2. 18.2.4.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 18.2.4.3.2.1  Channel Options Parameter (OPT)
            2. 18.2.4.3.2.2  Channel Source Address (SRC)
            3. 18.2.4.3.2.3  Channel Destination Address (DST)
            4. 18.2.4.3.2.4  Count for 1st Dimension (ACNT)
            5. 18.2.4.3.2.5  Count for 2nd Dimension (BCNT)
            6. 18.2.4.3.2.6  Count for 3rd Dimension (CCNT)
            7. 18.2.4.3.2.7  BCNT Reload (BCNTRLD)
            8. 18.2.4.3.2.8  Source B Index (SBIDX)
            9. 18.2.4.3.2.9  Destination B Index (DBIDX)
            10. 18.2.4.3.2.10 Source C Index (SCIDX)
            11. 18.2.4.3.2.11 Destination C Index (DCIDX)
            12. 18.2.4.3.2.12 Link Address (LINK)
          3. 18.2.4.3.3 Null PaRAM Set
          4. 18.2.4.3.4 Dummy PaRAM Set
          5. 18.2.4.3.5 Dummy Versus Null Transfer Comparison
          6. 18.2.4.3.6 Parameter Set Updates
          7. 18.2.4.3.7 Linking Transfers
          8. 18.2.4.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 18.2.4.3.9 Element Size
        4. 18.2.4.4  Initiating a DMA Transfer
          1. 18.2.4.4.1 DMA Channel
            1. 18.2.4.4.1.1 Event-Triggered Transfer Request
            2. 18.2.4.4.1.2 Manually-Triggered Transfer Request
            3. 18.2.4.4.1.3 Chain-Triggered Transfer Request
          2. 18.2.4.4.2 QDMA Channels
            1. 18.2.4.4.2.1 Auto-triggered and Link-Triggered Transfer Request
          3. 18.2.4.4.3 Comparison Between DMA and QDMA Channels
        5. 18.2.4.5  Completion of a DMA Transfer
          1. 18.2.4.5.1 Normal Completion
          2. 18.2.4.5.2 Early Completion
          3. 18.2.4.5.3 Dummy or Null Completion
        6. 18.2.4.6  Event, Channel, and PaRAM Mapping
          1. 18.2.4.6.1 DMA Channel to PaRAM Mapping
          2. 18.2.4.6.2 QDMA Channel to PaRAM Mapping
        7. 18.2.4.7  EDMA Channel Controller Regions
          1. 18.2.4.7.1 Region Overview
          2. 18.2.4.7.2 Channel Controller Regions
            1. 18.2.4.7.2.1 Resource Pool Division Across Two Regions
          3. 18.2.4.7.3 Region Interrupts
        8. 18.2.4.8  Chaining EDMA Channels
        9. 18.2.4.9  EDMA Interrupts
          1. 18.2.4.9.1 Transfer Completion Interrupts
            1. 18.2.4.9.1.1 Enabling Transfer Completion Interrupts
            2. 18.2.4.9.1.2 Clearing Transfer Completion Interrupts
          2. 18.2.4.9.2 EDMA Interrupt Servicing
          3. 18.2.4.9.3 Interrupt Servicing
          4. 18.2.4.9.4 3341
          5. 18.2.4.9.5 Interrupt Servicing
          6. 18.2.4.9.6 Interrupt Evaluation Operations
          7. 18.2.4.9.7 Error Interrupts
          8. 18.2.4.9.8 3345
        10. 18.2.4.10 Memory Protection
          1. 18.2.4.10.1 Active Memory Protection
          2. 18.2.4.10.2 Proxy Memory Protection
        11. 18.2.4.11 Event Queue(s)
          1. 18.2.4.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 18.2.4.11.2 Queue RAM Debug Visibility
          3. 18.2.4.11.3 Queue Resource Tracking
          4. 18.2.4.11.4 Performance Considerations
        12. 18.2.4.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 18.2.4.12.1 Architecture Details
            1. 18.2.4.12.1.1 Command Fragmentation
            2. 18.2.4.12.1.2 TR Pipelining
            3. 18.2.4.12.1.3 Command Fragmentation (DBS = 64)
            4. 18.2.4.12.1.4 Performance Tuning
          2. 18.2.4.12.2 Memory Protection
          3. 18.2.4.12.3 Error Generation
          4. 18.2.4.12.4 Debug Features
            1. 18.2.4.12.4.1 Destination FIFO Register Pointer
          5. 18.2.4.12.5 EDMA_TPTC Configuration
        13. 18.2.4.13 Event Dataflow
        14. 18.2.4.14 EDMA controller Prioritization
          1. 18.2.4.14.1 Channel Priority
          2. 18.2.4.14.2 Trigger Source Priority
          3. 18.2.4.14.3 Dequeue Priority
        15. 18.2.4.15 EDMA Power, Reset and Clock Management
          1. 18.2.4.15.1 Clock and Power Management
          2. 18.2.4.15.2 Reset Considerations
        16. 18.2.4.16 Emulation Considerations
      5. 18.2.5 EDMA Transfer Examples
        1. 18.2.5.1 Block Move Example
        2. 18.2.5.2 Subframe Extraction Example
        3. 18.2.5.3 Data Sorting Example
        4. 18.2.5.4 Peripheral Servicing Example
          1. 18.2.5.4.1 Non-bursting Peripherals
          2. 18.2.5.4.2 Bursting Peripherals
          3. 18.2.5.4.3 Continuous Operation
            1. 18.2.5.4.3.1 Receive Channel
            2. 18.2.5.4.3.2 Transmit Channel
            3. 18.2.5.4.3.3 3384
          4. 18.2.5.4.4 Ping-Pong Buffering
            1. 18.2.5.4.4.1 Synchronization with the CPU
          5. 18.2.5.4.5 Transfer Chaining Examples
            1. 18.2.5.4.5.1 Servicing Input/Output FIFOs with a Single Event
            2. 18.2.5.4.5.2 Breaking Up Large Transfers with Intermediate Chaining
        5. 18.2.5.5 Setting Up an EDMA Transfer
          1. 18.2.5.5.1 3391
      6. 18.2.6 EDMA Debug Checklist and Programming Tips
        1. 18.2.6.1 EDMA Debug Checklist
        2. 18.2.6.2 EDMA Programming Tips
      7. 18.2.7 EDMA Register Manual
        1. 18.2.7.1 EDMA Instance Summary
        2. 18.2.7.2 EDMA Registers
          1. 18.2.7.2.1 EDMA Register Summary
          2. 18.2.7.2.2 EDMA Register Description
            1. 18.2.7.2.2.1 EDMA_TPCC Register Description
            2. 18.2.7.2.2.2 EDMA_TPTC0 and EDMA_TPTC1 Register Description
  21. 19Interrupt Controllers
    1. 19.1 Interrupt Controllers Overview
    2. 19.2 Interrupt Controllers Environment
    3. 19.3 Interrupt Controllers Integration
      1. 19.3.1 Interrupt Requests to MPU_INTC
      2. 19.3.2 Interrupt Requests to DSP1_INTC
      3. 19.3.3 Interrupt Requests to DSP2_INTC
      4. 19.3.4 Interrupt Requests to IPU1_Cx_INTC
      5. 19.3.5 Interrupt Requests to IPU2_Cx_INTC
      6. 19.3.6 Interrupt Requests to EVE1_INTC1
      7. 19.3.7 Interrupt Requests to EVE2_INTC1
      8. 19.3.8 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
    4. 19.4 Interrupt Controllers Functional Description
  22. 20Control Module
    1. 20.1 Control Module Overview
    2. 20.2 Control Module Environment
    3. 20.3 Control Module Integration
    4. 20.4 Control Module Functional Description
      1. 20.4.1 Control Module Clock Configuration
      2. 20.4.2 Control Module Resets
      3. 20.4.3 Control Module Power Management
        1. 20.4.3.1 Power Management Protocols
      4. 20.4.4 Hardware Requests
      5. 20.4.5 Control Module Initialization
      6. 20.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
        1. 20.4.6.1  Pad Configuration
          1. 20.4.6.1.1 Pad Configuration Registers
            1. 20.4.6.1.1.1 Permanent PU/PD disabling
          2. 20.4.6.1.2 Pull Selection
          3. 20.4.6.1.3 Pad multiplexing
          4. 20.4.6.1.4 IOSETs
          5. 20.4.6.1.5 Virtual IO Timing Modes
          6. 20.4.6.1.6 Manual IO Timing Modes
          7. 20.4.6.1.7 Isolation Requirements
          8. 20.4.6.1.8 IO Delay Recalibration
        2. 20.4.6.2  Thermal Management Related Registers
          1. 20.4.6.2.1 Temperature Sensors Control Registers
          2. 20.4.6.2.2 Registers For The Thermal Alert Comparators
          3. 20.4.6.2.3 Thermal Shutdown Comparators
          4. 20.4.6.2.4 Temperature Timestamp Registers
          5. 20.4.6.2.5 Other Thermal Management Related Registers
          6. 20.4.6.2.6 Summary of the Thermal Management Related Registers
          7. 20.4.6.2.7 ADC Values Versus Temperature
        3. 20.4.6.3  PBIAS Cell And MMC1 I/O Cells Control Registers
        4. 20.4.6.4  IRQ_CROSSBAR Module Functional Description
        5. 20.4.6.5  DMA_CROSSBAR Module Functional Description
        6. 20.4.6.6  SDRAM Initiator Priority Registers
        7. 20.4.6.7  L3_MAIN Initiator Priority Registers
        8. 20.4.6.8  Memory Region Lock Registers
        9. 20.4.6.9  NMI Mapping To Respective Cores
        10. 20.4.6.10 Software Controls for the DDR2/DDR3 I/O Cells
        11. 20.4.6.11 Reference Voltage for the Device DDR2/DDR3 Receivers
        12. 20.4.6.12 AVS Class 0 Associated Registers
        13. 20.4.6.13 ABB Associated Registers
        14. 20.4.6.14 Registers For Other Miscellaneous Functions
          1. 20.4.6.14.1 System Boot Status Settings
          2. 20.4.6.14.2 Force MPU Write Nonposted Transactions
          3. 20.4.6.14.3 Firewall Error Status Registers
          4. 20.4.6.14.4 Settings Related To Different Peripheral Modules
      7. 20.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
        1. 20.4.7.1 Registers For Basic EMIF Configuration
    5. 20.5 Control Module Register Manual
    6. 20.6 IODELAYCONFIG Module Integration
    7. 20.7 IODELAYCONFIG Module Register Manual
  23. 21Mailbox
    1. 21.1 Mailbox Overview
    2. 21.2 Mailbox Integration
      1. 21.2.1 System MAILBOX Integration
      2. 21.2.2 IVA Mailbox Integration
      3. 21.2.3 EVE Mailbox Integration
    3. 21.3 Mailbox Functional Description
      1. 21.3.1 Mailbox Block Diagram
        1. 21.3.1.1 3474
      2. 21.3.2 Mailbox Software Reset
      3. 21.3.3 Mailbox Power Management
      4. 21.3.4 Mailbox Interrupt Requests
      5. 21.3.5 Mailbox Assignment
        1. 21.3.5.1 Description
      6. 21.3.6 Sending and Receiving Messages
        1. 21.3.6.1 Description
      7. 21.3.7 16-Bit Register Access
        1. 21.3.7.1 Description
      8. 21.3.8 Example of Communication
    4. 21.4 Mailbox Programming Guide
      1. 21.4.1 Mailbox Low-level Programming Models
        1. 21.4.1.1 Global Initialization
          1. 21.4.1.1.1 Surrounding Modules Global Initialization
          2. 21.4.1.1.2 Mailbox Global Initialization
            1. 21.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
        2. 21.4.1.2 Mailbox Operational Modes Configuration
          1. 21.4.1.2.1 Mailbox Processing modes
            1. 21.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
            2. 21.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
            3. 21.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
            4. 21.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
        3. 21.4.1.3 Mailbox Events Servicing
          1. 21.4.1.3.1 Events Servicing in Sending Mode
          2. 21.4.1.3.2 Events Servicing in Receiving Mode
    5. 21.5 Mailbox Register Manual
      1. 21.5.1 Mailbox Instance Summary
      2. 21.5.2 Mailbox Registers
        1. 21.5.2.1 Mailbox Register Summary
        2. 21.5.2.2 Mailbox Register Description
  24. 22Memory Management Units
    1. 22.1 MMU Overview
    2. 22.2 MMU Integration
    3. 22.3 MMU Functional Description
      1. 22.3.1 MMU Block Diagram
        1. 22.3.1.1 MMU Address Translation Process
        2. 22.3.1.2 Translation Tables
          1. 22.3.1.2.1 Translation Table Hierarchy
          2. 22.3.1.2.2 First-Level Translation Table
            1. 22.3.1.2.2.1 First-Level Descriptor Format
            2. 22.3.1.2.2.2 First-Level Page Descriptor Format
            3. 22.3.1.2.2.3 First-Level Section Descriptor Format
            4. 22.3.1.2.2.4 Section Translation Summary
            5. 22.3.1.2.2.5 Supersection Translation Summary
          3. 22.3.1.2.3 Two-Level Translation
            1. 22.3.1.2.3.1 Second-Level Descriptor Format
            2. 22.3.1.2.3.2 Small Page Translation Summary
            3. 22.3.1.2.3.3 Large Page Translation Summary
        3. 22.3.1.3 Translation Lookaside Buffer
          1. 22.3.1.3.1 TLB Entry Format
        4. 22.3.1.4 No Translation (Bypass) Regions
      2. 22.3.2 MMU Software Reset
      3. 22.3.3 MMU Power Management
      4. 22.3.4 MMU Interrupt Requests
      5. 22.3.5 MMU Error Handling
    4. 22.4 MMU Low-level Programming Models
      1. 22.4.1 Global Initialization
        1. 22.4.1.1 Surrounding Modules Global Initialization
        2. 22.4.1.2 MMU Global Initialization
          1. 22.4.1.2.1 Main Sequence - MMU Global Initialization
          2. 22.4.1.2.2 Subsequence - Configure a TLB entry
        3. 22.4.1.3 Operational Modes Configuration
          1. 22.4.1.3.1 Main Sequence - Writing TLB Entries Statically
          2. 22.4.1.3.2 Main Sequence - Protecting TLB Entries
          3. 22.4.1.3.3 Main Sequence - Deleting TLB Entries
          4. 22.4.1.3.4 Main Sequence - Read TLB Entries
    5. 22.5 MMU Register Manual
      1. 22.5.1 MMU Instance Summary
      2. 22.5.2 MMU Registers
        1. 22.5.2.1 MMU Register Summary
        2. 22.5.2.2 MMU Register Description
  25. 23Spinlock
    1. 23.1 Spinlock Overview
    2. 23.2 Spinlock Integration
    3. 23.3 Spinlock Functional Description
      1. 23.3.1 Spinlock Software Reset
      2. 23.3.2 Spinlock Power Management
      3. 23.3.3 About Spinlocks
      4. 23.3.4 Spinlock Functional Operation
    4. 23.4 Spinlock Programming Guide
      1. 23.4.1 Spinlock Low-level Programming Models
        1. 23.4.1.1 Surrounding Modules Global Initialization
        2. 23.4.1.2 Basic Spinlock Operations
          1. 23.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
          2. 23.4.1.2.2 Take and Release Spinlock
    5. 23.5 Spinlock Register Manual
      1. 23.5.1 Spinlock Instance Summary
      2. 23.5.2 Spinlock Registers
        1. 23.5.2.1 Spinlock Register Summary
        2. 23.5.2.2 Spinlock Register Description
  26. 24Timers
    1. 24.1 Timers Overview
    2. 24.2 General-Purpose Timers
      1. 24.2.1 General-Purpose Timers Overview
        1. 24.2.1.1 GP Timer Features
      2. 24.2.2 GP Timer Environment
        1. 24.2.2.1 GP Timer External System Interface
      3. 24.2.3 GP Timer Integration
      4. 24.2.4 GP Timer Functional Description
        1. 24.2.4.1  GP Timer Block Diagram
        2. 24.2.4.2  TIMER1, TIMER2 and TIMER10 Power Management
          1. 24.2.4.2.1 Wake-Up Capability
        3. 24.2.4.3  Power Management of Other GP Timers
          1. 24.2.4.3.1 Wake-Up Capability
        4. 24.2.4.4  Software Reset
        5. 24.2.4.5  GP Timer Interrupts
        6. 24.2.4.6  Timer Mode Functionality
          1. 24.2.4.6.1 1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
        7. 24.2.4.7  Capture Mode Functionality
        8. 24.2.4.8  Compare Mode Functionality
        9. 24.2.4.9  Prescaler Functionality
        10. 24.2.4.10 Pulse-Width Modulation
        11. 24.2.4.11 Timer Counting Rate
        12. 24.2.4.12 Timer Under Emulation
        13. 24.2.4.13 Accessing GP Timer Registers
          1. 24.2.4.13.1 Writing to Timer Registers
            1. 24.2.4.13.1.1 Write Posting Synchronization Mode
            2. 24.2.4.13.1.2 Write Nonposting Synchronization Mode
          2. 24.2.4.13.2 Reading From Timer Counter Registers
            1. 24.2.4.13.2.1 Read Posted
            2. 24.2.4.13.2.2 Read Non-Posted
        14. 24.2.4.14 Posted Mode Selection
      5. 24.2.5 GP Timer Low-Level Programming Models
        1. 24.2.5.1 Global Initialization
          1. 24.2.5.1.1 Global Initialization of Surrounding Modules
          2. 24.2.5.1.2 GP Timer Module Global Initialization
            1. 24.2.5.1.2.1 Main Sequence – GP Timer Module Global Initialization
        2. 24.2.5.2 Operational Mode Configuration
          1. 24.2.5.2.1 GP Timer Mode
            1. 24.2.5.2.1.1 Main Sequence – GP Timer Mode Configuration
          2. 24.2.5.2.2 GP Timer Compare Mode
            1. 24.2.5.2.2.1 Main Sequence – GP Timer Compare Mode Configuration
          3. 24.2.5.2.3 GP Timer Capture Mode
            1. 24.2.5.2.3.1 Main Sequence – GP Timer Capture Mode Configuration
            2. 24.2.5.2.3.2 Subsequence – Initialize Capture Mode
            3. 24.2.5.2.3.3 Subsequence – Detect Event
          4. 24.2.5.2.4 GP Timer PWM Mode
            1. 24.2.5.2.4.1 Main Sequence – GP Timer PWM Mode Configuration
      6. 24.2.6 GP Timer Register Manual
        1. 24.2.6.1 GP Timer Instance Summary
        2. 24.2.6.2 GP Timer Registers
          1. 24.2.6.2.1 GP Timer Register Summary
          2. 24.2.6.2.2 GP Timer Register Description
          3. 24.2.6.2.3 TIMER1, TIMER2, and TIMER10 Register Description
    3. 24.3 32-kHz Synchronized Timer (COUNTER_32K)
      1. 24.3.1 32-kHz Synchronized Timer Overview
        1. 24.3.1.1 32-kHz Synchronized Timer Features
      2. 24.3.2 32-kHz Synchronized Timer Integration
      3. 24.3.3 32-kHz Synchronized Timer Functional Description
        1. 24.3.3.1 Reading the 32-kHz Synchronized Timer
      4. 24.3.4 COUNTER_32K Timer Register Manual
        1. 24.3.4.1 COUNTER_32K Timer Register Mapping Summary
        2. 24.3.4.2 COUNTER_32K Timer Register Description
    4. 24.4 Watchdog Timer
      1. 24.4.1 Watchdog Timer Overview
        1. 24.4.1.1 Watchdog Timer Features
      2. 24.4.2 Watchdog Timer Integration
      3. 24.4.3 Watchdog Timer Functional Description
        1. 24.4.3.1  Power Management
          1. 24.4.3.1.1 Wake-Up Capability
        2. 24.4.3.2  Interrupts
        3. 24.4.3.3  General Watchdog Timer Operation
        4. 24.4.3.4  Reset Context
        5. 24.4.3.5  Overflow/Reset Generation
        6. 24.4.3.6  Prescaler Value/Timer Reset Frequency
        7. 24.4.3.7  Triggering a Timer Reload
        8. 24.4.3.8  Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
        9. 24.4.3.9  Modifying Timer Count/Load Values and Prescaler Setting
        10. 24.4.3.10 Watchdog Counter Register Access Restriction (WCRR)
        11. 24.4.3.11 Watchdog Timer Interrupt Generation
        12. 24.4.3.12 Watchdog Timer Under Emulation
        13. 24.4.3.13 Accessing Watchdog Timer Registers
      4. 24.4.4 Watchdog Timer Low-Level Programming Model
        1. 24.4.4.1 Global Initialization
          1. 24.4.4.1.1 Surrounding Modules Global Initialization
          2. 24.4.4.1.2 Watchdog Timer Module Global Initialization
            1. 24.4.4.1.2.1 Main Sequence – Watchdog Timer Module Global Initialization
        2. 24.4.4.2 Operational Mode Configuration
          1. 24.4.4.2.1 Watchdog Timer Basic Configuration
            1. 24.4.4.2.1.1 Main Sequence – Watchdog Timer Basic Configuration
            2. 24.4.4.2.1.2 Subsequence – Disable the Watchdog Timer
            3. 24.4.4.2.1.3 Subsequence – Enable the Watchdog Timer
      5. 24.4.5 Watchdog Timer Register Manual
        1. 24.4.5.1 Watchdog Timer Instance Summary
        2. 24.4.5.2 Watchdog Timer Registers
          1. 24.4.5.2.1 Watchdog Timer Register Summary
          2. 24.4.5.2.2 3661
          3. 24.4.5.2.3 Watchdog Timer Register Description
  27. 25Real-Time Clock (RTC)
    1. 25.1 RTC Overview
      1. 25.1.1 RTC Features
    2. 25.2 RTC Environment
      1. 25.2.1 RTC External Interface
    3. 25.3 RTC Integration
    4. 25.4 RTC Functional Description
      1. 25.4.1 Clock Source
      2. 25.4.2 Interrupt Support
        1. 25.4.2.1 CPU Interrupts
        2. 25.4.2.2 Interrupt Description
          1. 25.4.2.2.1 Timer Interrupt (timer_intr)
          2. 25.4.2.2.2 Alarm Interrupt (alarm_intr)
      3. 25.4.3 RTC Programming/Usage Guide
        1. 25.4.3.1 Time/Calendar Data Format
        2. 25.4.3.2 Register Access
        3. 25.4.3.3 Register Spurious Write Protection
        4. 25.4.3.4 Reading the Timer/Calendar (TC) Registers
          1. 25.4.3.4.1 Rounding Seconds
        5. 25.4.3.5 Modifying the TC Registers
          1. 25.4.3.5.1 General Registers
        6. 25.4.3.6 Crystal Compensation
      4. 25.4.4 Scratch Registers
      5. 25.4.5 Debouncing
      6. 25.4.6 Power Management
        1. 25.4.6.1 Device-Level Power Management
        2. 25.4.6.2 Subsystem-Level Power Management — PMIC Mode
    5. 25.5 RTC Low-Level Programming Guide
      1. 25.5.1 Global Initialization
        1. 25.5.1.1 Surrounding Modules Global Initialization
        2. 25.5.1.2 RTC Module Global Initialization
          1. 25.5.1.2.1 Main Sequence – RTC Module Global Initialization
    6. 25.6 RTC Register Manual
      1. 25.6.1 RTC Instance Summary
      2. 25.6.2 RTC_SS Registers
        1. 25.6.2.1 RTC_SS Register Summary
        2. 25.6.2.2 RTC_SS Register Description
  28. 26Serial Communication Interfaces
    1. 26.1  Multimaster High-Speed I2C Controller
      1. 26.1.1 HS I2C Overview
      2. 26.1.2 HS I2C Environment
        1. 26.1.2.1 HS I2C Typical Application
          1. 26.1.2.1.1 HS I2C Pins for Typical Connections in I2C Mode
          2. 26.1.2.1.2 HS I2C Interface Typical Connections
        2. 26.1.2.2 HS I2C Typical Connection Protocol and Data Format
          1. 26.1.2.2.1  HS I2C Serial Data Format
          2. 26.1.2.2.2  HS I2C Data Validity
          3. 26.1.2.2.3  HS I2C Start and Stop Conditions
          4. 26.1.2.2.4  HS I2C Addressing
            1. 26.1.2.2.4.1 Data Transfer Formats in F/S Mode
            2. 26.1.2.2.4.2 Data Transfer Format in HS Mode
          5. 26.1.2.2.5  HS I2C Master Transmitter
          6. 26.1.2.2.6  HS I2C Master Receiver
          7. 26.1.2.2.7  HS I2C Slave Transmitter
          8. 26.1.2.2.8  HS I2C Slave Receiver
          9. 26.1.2.2.9  HS I2C Bus Arbitration
          10. 26.1.2.2.10 HS I2C Clock Generation and Synchronization
      3. 26.1.3 HS I2C Integration
      4. 26.1.4 HS I2C Functional Description
        1. 26.1.4.1  HS I2C Block Diagram
        2. 26.1.4.2  HS I2C Clocks
          1. 26.1.4.2.1 HS I2C Clocking
          2. 26.1.4.2.2 HS I2C Automatic Blocking of the I2C Clock Feature
        3. 26.1.4.3  HS I2C Software Reset
        4. 26.1.4.4  HS I2C Power Management
        5. 26.1.4.5  HS I2C Interrupt Requests
        6. 26.1.4.6  HS I2C DMA Requests
        7. 26.1.4.7  HS I2C Programmable Multislave Channel Feature
        8. 26.1.4.8  HS I2C FIFO Management
          1. 26.1.4.8.1 HS I2C FIFO Interrupt Mode
          2. 26.1.4.8.2 HS I2C FIFO Polling Mode
          3. 26.1.4.8.3 HS I2C FIFO DMA Mode
          4. 26.1.4.8.4 HS I2C Draining Feature
        9. 26.1.4.9  HS I2C Noise Filter
        10. 26.1.4.10 HS I2C System Test Mode
      5. 26.1.5 HS I2C Programming Guide
        1. 26.1.5.1 HS I2C Low-Level Programming Models
          1. 26.1.5.1.1 HS I2C Programming Model
            1. 26.1.5.1.1.1 Main Program
              1. 26.1.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
              2. 26.1.5.1.1.1.2 Initialize the I2C Controller
              3. 26.1.5.1.1.1.3 Configure Slave Address and the Data Control Register
              4. 26.1.5.1.1.1.4 Initiate a Transfer
              5. 26.1.5.1.1.1.5 Receive Data
              6. 26.1.5.1.1.1.6 Transmit Data
            2. 26.1.5.1.1.2 Interrupt Subroutine Sequence
            3. 26.1.5.1.1.3 Programming Flow-Diagrams
      6. 26.1.6 HS I2C Register Manual
        1. 26.1.6.1 HS I2C Instance Summary
        2. 26.1.6.2 HS I2C Registers
          1. 26.1.6.2.1 HS I2C Register Summary
          2. 26.1.6.2.2 HS I2C Register Description
    2. 26.2  HDQ/1-Wire
      1. 26.2.1 HDQ1W Overview
      2. 26.2.2 HDQ1W Environment
        1. 26.2.2.1 HDQ1W Functional Modes
        2. 26.2.2.2 HDQ and 1-Wire (SDQ) Protocols
          1. 26.2.2.2.1 HDQ Protocol Initialization (Default)
          2. 26.2.2.2.2 1-Wire (SDQ) Protocol Initialization
          3. 26.2.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols)
      3. 26.2.3 HDQ1W Integration
      4. 26.2.4 HDQ1W Functional Description
        1. 26.2.4.1 HDQ1W Block Diagram
        2. 26.2.4.2 HDQ1W Clocking Configuration
          1. 26.2.4.2.1 HDQ1W Clocks
        3. 26.2.4.3 HDQ1W Hardware and Software Reset
        4. 26.2.4.4 HDQ1W Power Management
          1. 26.2.4.4.1 Auto-Idle Mode
          2. 26.2.4.4.2 Power-Down Mode
          3. 26.2.4.4.3 3772
        5. 26.2.4.5 HDQ Interrupt Requests
        6. 26.2.4.6 HDQ Mode (Default)
          1. 26.2.4.6.1 HDQ Mode Features
          2. 26.2.4.6.2 Description
          3. 26.2.4.6.3 Single-Bit Mode
          4. 26.2.4.6.4 Interrupt Conditions
        7. 26.2.4.7 1-Wire Mode
          1. 26.2.4.7.1 1-Wire Mode Features
          2. 26.2.4.7.2 Description
          3. 26.2.4.7.3 1-Wire Single-Bit Mode Operation
          4. 26.2.4.7.4 Interrupt Conditions
          5. 26.2.4.7.5 Status Flags
        8. 26.2.4.8 BITFSM Delay
      5. 26.2.5 HDQ1W Low-Level Programming Model
        1. 26.2.5.1 Global Initialization
          1. 26.2.5.1.1 Surrounding Modules Global Initialization
          2. 26.2.5.1.2 HDQ1W Module Global Initialization
        2. 26.2.5.2 HDQ Operational Modes Configuration
          1. 26.2.5.2.1 Main Sequence - HDQ Write Operation Mode
          2. 26.2.5.2.2 Main Sequence - HDQ Read Operation Mode
            1. 26.2.5.2.2.1 Sub-sequence - Initialize HDQ Slave
        3. 26.2.5.3 1-Wire Operational Modes Configuration
          1. 26.2.5.3.1 Main Sequence - 1-Wire Write Operation Mode
          2. 26.2.5.3.2 Main Sequence - 1-Wire Read Operation Mode
          3. 26.2.5.3.3 Sub-sequence - Initialize 1-Wire Slave
      6. 26.2.6 HDQ1W Register Manual
        1. 26.2.6.1 HDQ1W Instance Summary
        2. 26.2.6.2 HDQ1W Registers
          1. 26.2.6.2.1 HDQ1W Register Summary
          2. 26.2.6.2.2 HDQ1W Register Description
    3. 26.3  UART/IrDA/CIR
      1. 26.3.1 UART/IrDA/CIR Overview
        1. 26.3.1.1 UART Features
        2. 26.3.1.2 IrDA Features
        3. 26.3.1.3 CIR Features
      2. 26.3.2 UART/IrDA/CIR Environment
        1. 26.3.2.1 UART Interface
          1. 26.3.2.1.1 System Using UART Communication With Hardware Handshake
          2. 26.3.2.1.2 UART Interface Description
          3. 26.3.2.1.3 UART Protocol and Data Format
        2. 26.3.2.2 IrDA Functional Interfaces
          1. 26.3.2.2.1 System Using IrDA Communication Protocol
          2. 26.3.2.2.2 IrDA Interface Description
          3. 26.3.2.2.3 IrDA Protocol and Data Format
            1. 26.3.2.2.3.1 SIR Mode
              1. 26.3.2.2.3.1.1 Frame Format
              2. 26.3.2.2.3.1.2 Asynchronous Transparency
              3. 26.3.2.2.3.1.3 Abort Sequence
              4. 26.3.2.2.3.1.4 Pulse Shaping
              5. 26.3.2.2.3.1.5 Encoder
              6. 26.3.2.2.3.1.6 Decoder
              7. 26.3.2.2.3.1.7 IR Address Checking
            2. 26.3.2.2.3.2 SIR Free-Format Mode
            3. 26.3.2.2.3.3 MIR Mode
              1. 26.3.2.2.3.3.1 MIR Encoder/Decoder
              2. 26.3.2.2.3.3.2 SIP Generation
            4. 26.3.2.2.3.4 FIR Mode
        3. 26.3.2.3 CIR Functional Interfaces
          1. 26.3.2.3.1 System Using CIR Communication Protocol With Remote Control
          2. 26.3.2.3.2 CIR Interface Description
          3. 26.3.2.3.3 CIR Protocol and Data Format
            1. 26.3.2.3.3.1 Carrier Modulation
            2. 26.3.2.3.3.2 Pulse Duty Cycle
            3. 26.3.2.3.3.3 Consumer IR Encoding/Decoding
      3. 26.3.3 UART/IrDA/CIR Integration
        1. 26.3.3.1 3838
      4. 26.3.4 UART/IrDA/CIR Functional Description
        1. 26.3.4.1 Block Diagram
        2. 26.3.4.2 Clock Configuration
        3. 26.3.4.3 Software Reset
        4. 26.3.4.4 Power Management
          1. 26.3.4.4.1 UART Mode Power Management
            1. 26.3.4.4.1.1 Module Power Saving
            2. 26.3.4.4.1.2 System Power Saving
          2. 26.3.4.4.2 IrDA Mode Power Management (UART3 Only)
            1. 26.3.4.4.2.1 Module Power Saving
            2. 26.3.4.4.2.2 System Power Saving
          3. 26.3.4.4.3 CIR Mode Power Management (UART3 Only)
            1. 26.3.4.4.3.1 Module Power Saving
            2. 26.3.4.4.3.2 System Power Saving
          4. 26.3.4.4.4 Local Power Management
        5. 26.3.4.5 Interrupt Requests
          1. 26.3.4.5.1 UART Mode Interrupt Management
            1. 26.3.4.5.1.1 UART Interrupts
            2. 26.3.4.5.1.2 Wake-Up Interrupt
          2. 26.3.4.5.2 IrDA Mode Interrupt Management
            1. 26.3.4.5.2.1 IrDA Interrupts
            2. 26.3.4.5.2.2 Wake-Up Interrupts
          3. 26.3.4.5.3 CIR Mode Interrupt Management
            1. 26.3.4.5.3.1 CIR Interrupts
            2. 26.3.4.5.3.2 Wake-Up Interrupts
        6. 26.3.4.6 FIFO Management
          1. 26.3.4.6.1 FIFO Trigger
            1. 26.3.4.6.1.1 Transmit FIFO Trigger
            2. 26.3.4.6.1.2 Receive FIFO Trigger
          2. 26.3.4.6.2 FIFO Interrupt Mode
          3. 26.3.4.6.3 FIFO Polled Mode Operation
          4. 26.3.4.6.4 FIFO DMA Mode Operation
            1. 26.3.4.6.4.1 DMA sequence to disable TX DMA
            2. 26.3.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
            3. 26.3.4.6.4.3 DMA Transmission
            4. 26.3.4.6.4.4 DMA Reception
        7. 26.3.4.7 Mode Selection
          1. 26.3.4.7.1 Register Access Modes
            1. 26.3.4.7.1.1 Operational Mode and Configuration Modes
            2. 26.3.4.7.1.2 Register Access Submode
            3. 26.3.4.7.1.3 Registers Available for the Register Access Modes
          2. 26.3.4.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
            1. 26.3.4.7.2.1 Registers Available for the UART Function
            2. 26.3.4.7.2.2 Registers Available for the IrDA Function (UART3 Only)
            3. 26.3.4.7.2.3 Registers Available for the CIR Function (UART3 Only)
        8. 26.3.4.8 Protocol Formatting
          1. 26.3.4.8.1 UART Mode
            1. 26.3.4.8.1.1 UART Clock Generation: Baud Rate Generation
            2. 26.3.4.8.1.2 Choosing the Appropriate Divisor Value
            3. 26.3.4.8.1.3 UART Data Formatting
              1. 26.3.4.8.1.3.1 Frame Formatting
              2. 26.3.4.8.1.3.2 Hardware Flow Control
              3. 26.3.4.8.1.3.3 Software Flow Control
                1. 26.3.4.8.1.3.3.1 Receive (RX)
                2. 26.3.4.8.1.3.3.2 Transmit (TX)
              4. 26.3.4.8.1.3.4 Autobauding Modes
              5. 26.3.4.8.1.3.5 Error Detection
              6. 26.3.4.8.1.3.6 Overrun During Receive
              7. 26.3.4.8.1.3.7 Time-Out and Break Conditions
                1. 26.3.4.8.1.3.7.1 Time-Out Counter
                2. 26.3.4.8.1.3.7.2 Break Condition
          2. 26.3.4.8.2 IrDA Mode (UART3 Only)
            1. 26.3.4.8.2.1 IrDA Clock Generation: Baud Generator
            2. 26.3.4.8.2.2 Choosing the Appropriate Divisor Value
            3. 26.3.4.8.2.3 IrDA Data Formatting
              1. 26.3.4.8.2.3.1 IR RX Polarity Control
              2. 26.3.4.8.2.3.2 IrDA Reception Control
              3. 26.3.4.8.2.3.3 IR Address Checking
              4. 26.3.4.8.2.3.4 Frame Closing
              5. 26.3.4.8.2.3.5 Store and Controlled Transmission
              6. 26.3.4.8.2.3.6 Error Detection
              7. 26.3.4.8.2.3.7 Underrun During Transmission
              8. 26.3.4.8.2.3.8 Overrun During Receive
              9. 26.3.4.8.2.3.9 Status FIFO
            4. 26.3.4.8.2.4 SIR Mode Data Formatting
              1. 26.3.4.8.2.4.1 Abort Sequence
              2. 26.3.4.8.2.4.2 Pulse Shaping
              3. 26.3.4.8.2.4.3 SIR Free Format Programming
            5. 26.3.4.8.2.5 MIR and FIR Mode Data Formatting
          3. 26.3.4.8.3 CIR Mode (UART3 Only)
            1. 26.3.4.8.3.1 CIR Mode Clock Generation
            2. 26.3.4.8.3.2 CIR Data Formatting
              1. 26.3.4.8.3.2.1 IR RX Polarity Control
              2. 26.3.4.8.3.2.2 CIR Transmission
      5. 26.3.5 UART/IrDA/CIR Basic Programming Model
        1. 26.3.5.1 Global Initialization
          1. 26.3.5.1.1 Surrounding Modules Global Initialization
          2. 26.3.5.1.2 UART/IrDA/CIR Module Global Initialization
        2. 26.3.5.2 Mode selection
        3. 26.3.5.3 Submode selection
        4. 26.3.5.4 Load FIFO trigger and DMA mode settings
          1. 26.3.5.4.1 DMA mode Settings
          2. 26.3.5.4.2 FIFO Trigger Settings
        5. 26.3.5.5 Protocol, Baud rate and interrupt settings
          1. 26.3.5.5.1 Baud rate settings
          2. 26.3.5.5.2 Interrupt settings
          3. 26.3.5.5.3 Protocol settings
          4. 26.3.5.5.4 UART/IrDA(SIR/MIR/FIR)/CIR
        6. 26.3.5.6 Hardware and Software Flow Control Configuration
          1. 26.3.5.6.1 Hardware Flow Control Configuration
          2. 26.3.5.6.2 Software Flow Control Configuration
        7. 26.3.5.7 IrDA Programming Model (UART3 Only)
          1. 26.3.5.7.1 SIR mode
            1. 26.3.5.7.1.1 Receive
            2. 26.3.5.7.1.2 Transmit
          2. 26.3.5.7.2 MIR mode
            1. 26.3.5.7.2.1 Receive
            2. 26.3.5.7.2.2 Transmit
          3. 26.3.5.7.3 FIR mode
            1. 26.3.5.7.3.1 Receive
            2. 26.3.5.7.3.2 Transmit
      6. 26.3.6 UART/IrDA/CIR Register Manual
        1. 26.3.6.1 UART/IrDA/CIR Instance Summary
        2. 26.3.6.2 UART/IrDA/CIR Registers
          1. 26.3.6.2.1 UART/IrDA/CIR Register Summary
          2. 26.3.6.2.2 UART/IrDA/CIR Register Description
    4. 26.4  Multichannel Serial Peripheral Interface
      1. 26.4.1 McSPI Overview
      2. 26.4.2 McSPI Environment
        1. 26.4.2.1 Basic McSPI Pins for Master Mode
        2. 26.4.2.2 Basic McSPI Pins for Slave Mode
        3. 26.4.2.3 Multichannel SPI Protocol and Data Format
          1. 26.4.2.3.1 Transfer Format
        4. 26.4.2.4 SPI in Master Mode
        5. 26.4.2.5 SPI in Slave Mode
      3. 26.4.3 McSPI Integration
      4. 26.4.4 McSPI Functional Description
        1. 26.4.4.1 McSPI Block Diagram
        2. 26.4.4.2 Reset
        3. 26.4.4.3 Master Mode
          1. 26.4.4.3.1 Master Mode Features
          2. 26.4.4.3.2 Master Transmit-and-Receive Mode (Full Duplex)
          3. 26.4.4.3.3 Master Transmit-Only Mode (Half Duplex)
          4. 26.4.4.3.4 Master Receive-Only Mode (Half Duplex)
          5. 26.4.4.3.5 Single-Channel Master Mode
            1. 26.4.4.3.5.1 Programming Tips When Switching to Another Channel
            2. 26.4.4.3.5.2 Force SPIEN[x] Mode
            3. 26.4.4.3.5.3 Turbo Mode
          6. 26.4.4.3.6 Start-Bit Mode
          7. 26.4.4.3.7 Chip-Select Timing Control
          8. 26.4.4.3.8 Programmable SPI Clock
            1. 26.4.4.3.8.1 Clock Ratio Granularity
        4. 26.4.4.4 Slave Mode
          1. 26.4.4.4.1 Dedicated Resources
          2. 26.4.4.4.2 Slave Transmit-and-Receive Mode
          3. 26.4.4.4.3 Slave Transmit-Only Mode
          4. 26.4.4.4.4 Slave Receive-Only Mode
        5. 26.4.4.5 3-Pin or 4-Pin Mode
        6. 26.4.4.6 FIFO Buffer Management
          1. 26.4.4.6.1 Buffer Almost Full
          2. 26.4.4.6.2 Buffer Almost Empty
          3. 26.4.4.6.3 End of Transfer Management
        7. 26.4.4.7 Interrupts
          1. 26.4.4.7.1 Interrupt Events in Master Mode
            1. 26.4.4.7.1.1 TXx_EMPTY
            2. 26.4.4.7.1.2 TXx_UNDERFLOW
            3. 26.4.4.7.1.3 RXx_ FULL
            4. 26.4.4.7.1.4 End Of Word Count
          2. 26.4.4.7.2 Interrupt Events in Slave Mode
            1. 26.4.4.7.2.1 TXx_EMPTY
            2. 26.4.4.7.2.2 TXx_UNDERFLOW
            3. 26.4.4.7.2.3 RXx_FULL
            4. 26.4.4.7.2.4 RX0_OVERFLOW
            5. 26.4.4.7.2.5 End Of Word Count
          3. 26.4.4.7.3 Interrupt-Driven Operation
          4. 26.4.4.7.4 Polling
        8. 26.4.4.8 DMA Requests
        9. 26.4.4.9 Power Saving Management
          1. 26.4.4.9.1 Normal Mode
          2. 26.4.4.9.2 Idle Mode
            1. 26.4.4.9.2.1 Wake-Up Event in Smart-Idle Mode
            2. 26.4.4.9.2.2 Transitions From Smart-Idle Mode to Normal Mode
            3. 26.4.4.9.2.3 Force-Idle Mode
      5. 26.4.5 McSPI Programming Guide
        1. 26.4.5.1 Global Initialization
          1. 26.4.5.1.1 Surrounding Modules Global Initialization
          2. 26.4.5.1.2 McSPI Global Initialization
            1. 26.4.5.1.2.1 Main Sequence – McSPI Global Initialization
        2. 26.4.5.2 Operational Mode Configuration
          1. 26.4.5.2.1 McSPI Operational Modes
            1. 26.4.5.2.1.1 Common Transfer Sequence
            2. 26.4.5.2.1.2 End of Transfer Sequences
            3. 26.4.5.2.1.3 Transmit-and-Receive (Master and Slave)
            4. 26.4.5.2.1.4 Transmit-Only (Master and Slave)
              1. 26.4.5.2.1.4.1 Based on Interrupt Requests
              2. 26.4.5.2.1.4.2 Based on DMA Write Requests
            5. 26.4.5.2.1.5 Master Normal Receive-Only
              1. 26.4.5.2.1.5.1 Based on Interrupt Requests
              2. 26.4.5.2.1.5.2 Based on DMA Read Requests
            6. 26.4.5.2.1.6 Master Turbo Receive-Only
              1. 26.4.5.2.1.6.1 Based on Interrupt Requests
              2. 26.4.5.2.1.6.2 Based on DMA Read Requests
            7. 26.4.5.2.1.7 Slave Receive-Only
            8. 26.4.5.2.1.8 Transfer Procedures With FIFO
              1. 26.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
              2. 26.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
              3. 26.4.5.2.1.8.3 Transmit-and-Receive With Word Count
              4. 26.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
              5. 26.4.5.2.1.8.5 Transmit-Only
              6. 26.4.5.2.1.8.6 Receive-Only With Word Count
              7. 26.4.5.2.1.8.7 Receive-Only Without Word Count
        3. 26.4.5.3 Common Transfer Procedures Without FIFO – Polling Method
          1. 26.4.5.3.1 Receive-Only Procedure – Polling Method
          2. 26.4.5.3.2 Receive-Only Procedure – Interrupt Method
          3. 26.4.5.3.3 Transmit-Only Procedure – Polling Method
          4. 26.4.5.3.4 Transmit-and-Receive Procedure – Polling Method
      6. 26.4.6 McSPI Register Manual
        1. 26.4.6.1 McSPI Instance Summary
        2. 26.4.6.2 McSPI Registers
          1. 26.4.6.2.1 McSPI Register Summary
          2. 26.4.6.2.2 McSPI Register Description
    5. 26.5  Quad Serial Peripheral Interface
      1. 26.5.1 Quad Serial Peripheral Interface Overview
      2. 26.5.2 QSPI Environment
      3. 26.5.3 QSPI Integration
      4. 26.5.4 QSPI Functional Description
        1. 26.5.4.1 QSPI Block Diagram
          1. 26.5.4.1.1 SFI Register Control
          2. 26.5.4.1.2 SFI Translator
          3. 26.5.4.1.3 SPI Control Interface
          4. 26.5.4.1.4 SPI Clock Generator
          5. 26.5.4.1.5 SPI Control State-Machine
          6. 26.5.4.1.6 SPI Data Shifter
        2. 26.5.4.2 QSPI Clock Configuration
        3. 26.5.4.3 QSPI Interrupt Requests
        4. 26.5.4.4 QSPI Memory Regions
      5. 26.5.5 QSPI Register Manual
        1. 26.5.5.1 QSPI Instance Summary
        2. 26.5.5.2 QSPI registers
          1. 26.5.5.2.1 QSPI Register Summary
          2. 26.5.5.2.2 QSPI Register Description
    6. 26.6  Multichannel Audio Serial Port
      1. 26.6.1 McASP Overview
      2. 26.6.2 McASP Environment
        1. 26.6.2.1 McASP Signals
        2. 26.6.2.2 Protocols and Data Formats
          1. 26.6.2.2.1 Protocols Supported
          2. 26.6.2.2.2 Definition of Terms
          3. 26.6.2.2.3 TDM Format
          4. 26.6.2.2.4 I2S Format
          5. 26.6.2.2.5 S/PDIF Coding Format
            1. 26.6.2.2.5.1 Biphase-Mark Code
            2. 26.6.2.2.5.2 S/PDIF Subframe Format
            3. 26.6.2.2.5.3 Frame Format
      3. 26.6.3 McASP Integration
      4. 26.6.4 McASP Functional Description
        1. 26.6.4.1  McASP Block Diagram
        2. 26.6.4.2  McASP Clock and Frame-Sync Configurations
          1. 26.6.4.2.1 McASP Transmit Clock
          2. 26.6.4.2.2 McASP Receive Clock
          3. 26.6.4.2.3 Frame-Sync Generator
          4. 26.6.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
        3. 26.6.4.3  Serializers
        4. 26.6.4.4  Format Units
          1. 26.6.4.4.1 Transmit Format Unit
            1. 26.6.4.4.1.1 TDM Mode Transmission Data Alignment Settings
            2. 26.6.4.4.1.2 DIT Mode Transmission Data Alignment Settings
          2. 26.6.4.4.2 Receive Format Unit
            1. 26.6.4.4.2.1 TDM Mode Reception Data Alignment Settings
        5. 26.6.4.5  State-Machines
        6. 26.6.4.6  TDM Sequencers
        7. 26.6.4.7  McASP Software Reset
        8. 26.6.4.8  McASP Power Management
        9. 26.6.4.9  Transfer Modes
          1. 26.6.4.9.1 Burst Transfer Mode
          2. 26.6.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode
            1. 26.6.4.9.2.1 TDM Time Slots Generation and Processing
            2. 26.6.4.9.2.2 Special 384-Slot TDM Mode for Connection to External DIR
          3. 26.6.4.9.3 DIT Transfer Mode
            1. 26.6.4.9.3.1 Transmit DIT Encoding
            2. 26.6.4.9.3.2 Transmit DIT Clock and Frame-Sync Generation
            3. 26.6.4.9.3.3 DIT Channel Status and User Data Register Files
        10. 26.6.4.10 Data Transmission and Reception
          1. 26.6.4.10.1 Data Ready Status and Event/Interrupt Generation
            1. 26.6.4.10.1.1 Transmit Data Ready
            2. 26.6.4.10.1.2 Receive Data Ready
            3. 26.6.4.10.1.3 Transfers Through the Data Port (DATA)
            4. 26.6.4.10.1.4 Transfers Through the Configuration Bus (CFG)
            5. 26.6.4.10.1.5 Using a Device CPU for McASP Servicing
            6. 26.6.4.10.1.6 Using the DMA for McASP Servicing
        11. 26.6.4.11 McASP Audio FIFO (AFIFO)
          1. 26.6.4.11.1 AFIFO Data Transmission
            1. 26.6.4.11.1.1 Transmit DMA Event Pacer
          2. 26.6.4.11.2 AFIFO Data Reception
            1. 26.6.4.11.2.1 Receive DMA Event Pacer
          3. 26.6.4.11.3 Arbitration Between Transmit and Receive DMA Requests
        12. 26.6.4.12 McASP Events and Interrupt Requests
          1. 26.6.4.12.1 Transmit Data Ready Event and Interrupt
          2. 26.6.4.12.2 Receive Data Ready Event and Interrupt
          3. 26.6.4.12.3 Error Interrupt
          4. 26.6.4.12.4 Multiple Interrupts
        13. 26.6.4.13 DMA Requests
        14. 26.6.4.14 Loopback Modes
          1. 26.6.4.14.1 Loopback Mode Configurations
        15. 26.6.4.15 Error Reporting
          1. 26.6.4.15.1 Buffer Underrun Error -Transmitter
          2. 26.6.4.15.2 Buffer Overrun Error-Receiver
          3. 26.6.4.15.3 DATA Port Error - Transmitter
          4. 26.6.4.15.4 DATA Port Error - Receiver
          5. 26.6.4.15.5 Unexpected Frame Sync Error
          6. 26.6.4.15.6 Clock Failure Detection
            1. 26.6.4.15.6.1 Clock Failure Check Startup
            2. 26.6.4.15.6.2 Transmit Clock Failure Check and Recovery
            3. 26.6.4.15.6.3 Receive Clock Failure Check and Recovery
      5. 26.6.5 McASP Low-Level Programming Model
        1. 26.6.5.1 Global Initialization
          1. 26.6.5.1.1 Surrounding Modules Global Initialization
          2. 26.6.5.1.2 McASP Global Initialization
            1. 26.6.5.1.2.1 Main Sequence – McASP Global Initialization for DIT-Transmission
              1. 26.6.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
              2. 26.6.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
              3. 26.6.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
              4. 26.6.5.1.2.1.4 Subsequence - McASP Pins Functional Configuration
              5. 26.6.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
            2. 26.6.5.1.2.2 Main Sequence – McASP Global Initialization for TDM-Reception
              1. 26.6.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
              2. 26.6.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
              3. 26.6.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
              4. 26.6.5.1.2.2.4 Subsequence—McASP Receiver Pins Functional Configuration
            3. 26.6.5.1.2.3 Main Sequence – McASP Global Initialization for TDM -Transmission
              1. 26.6.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
              2. 26.6.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
              3. 26.6.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
              4. 26.6.5.1.2.3.4 Subsequence—McASP Transmit Pins Functional Configuration
        2. 26.6.5.2 Operational Modes Configuration
          1. 26.6.5.2.1 McASP Transmission Modes
            1. 26.6.5.2.1.1 Main Sequence – McASP DIT- /TDM- Polling Transmission Method
            2. 26.6.5.2.1.2 Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
            3. 26.6.5.2.1.3 Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
          2. 26.6.5.2.2 McASP Reception Modes
            1. 26.6.5.2.2.1 Main Sequence – McASP Polling Reception Method
            2. 26.6.5.2.2.2 Main Sequence – McASP TDM - Interrupt Reception Method
            3. 26.6.5.2.2.3 Main Sequence – McASP TDM - Mode DMA Reception Method
          3. 26.6.5.2.3 McASP Event Servicing
            1. 26.6.5.2.3.1 McASP DIT-/TDM- Transmit Interrupt Events Servicing
            2. 26.6.5.2.3.2 McASP TDM- Receive Interrupt Events Servicing
            3. 26.6.5.2.3.3 4175
            4. 26.6.5.2.3.4 Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
            5. 26.6.5.2.3.5 Subsequence – McASP Receive Error Handling
      6. 26.6.6 McASP Register Manual
        1. 26.6.6.1 McASP Instance Summary
        2. 26.6.6.2 McASP Registers
          1. 26.6.6.2.1 MCASP_CFG Register Summary
          2. 26.6.6.2.2 MCASP_CFG Register Description
          3. 26.6.6.2.3 MCASP_AFIFO Register Summary
          4. 26.6.6.2.4 MCASP_AFIFO Register Description
          5. 26.6.6.2.5 MCASP_DAT Register Summary
          6. 26.6.6.2.6 MCASP_DAT Register Description
    7. 26.7  SuperSpeed USB DRD
      1. 26.7.1 SuperSpeed USB DRD Subsystem Overview
        1. 26.7.1.1 Main Features
      2. 26.7.2 SuperSpeed USB DRD Subsystem Environment
        1. 26.7.2.1 SuperSpeed USB DRD Subsystem I/O Interfaces
        2. 26.7.2.2 SuperSpeed USB Subsystem Application
          1. 26.7.2.2.1 USB3.0 DRD Application
          2. 26.7.2.2.2 USB2.0 DRD Internal PHY
          3. 26.7.2.2.3 USB2.0 DRD External PHY
          4. 26.7.2.2.4 4196
          5. 26.7.2.2.5 Host Mode
          6. 26.7.2.2.6 Device Mode
      3. 26.7.3 SuperSpeed USB Subsystem Integration
    8. 26.8  SATA Controller
      1. 26.8.1 SATA Controller Overview
        1. 26.8.1.1 SATA Controller
          1. 26.8.1.1.1 AHCI Mode Overview
          2. 26.8.1.1.2 Native Command Queuing
          3. 26.8.1.1.3 SATA Transport Layer Functionalities
          4. 26.8.1.1.4 SATA Link Layer Functionalities
        2. 26.8.1.2 SATA Controller Features
      2. 26.8.2 SATA Controller Environment
      3. 26.8.3 SATA Controller Integration
      4. 26.8.4 SATA Controller Functional Description
        1. 26.8.4.1  SATA Controller Block Diagram
        2. 26.8.4.2  SATA Controller Link Layer Protocol and Data Format
          1. 26.8.4.2.1 SATA 8b/10b Parallel Encoding/Decoding
          2. 26.8.4.2.2 SATA Stream Dword Components
          3. 26.8.4.2.3 Scrambling/Descrambling Processing
        3. 26.8.4.3  Resets
          1. 26.8.4.3.1 Hardware Reset
          2. 26.8.4.3.2 Software Initiated Resets
            1. 26.8.4.3.2.1 Software Reset
            2. 26.8.4.3.2.2 Port Reset
            3. 26.8.4.3.2.3 HBA Reset
        4. 26.8.4.4  Power Management
          1. 26.8.4.4.1 SATA Specific Power Management
            1. 26.8.4.4.1.1 PARTIAL Power Mode
            2. 26.8.4.4.1.2 Slumber Power Mode
            3. 26.8.4.4.1.3 Software Control over Low Power States
            4. 26.8.4.4.1.4 Aggressive Power Management
          2. 26.8.4.4.2 Master Standby and Slave Idle Management Protocols
          3. 26.8.4.4.3 Clock Gating Synchronization
          4. 26.8.4.4.4 4230
        5. 26.8.4.5  Interrupt Requests
          1. 26.8.4.5.1 Interrupt Generation
          2. 26.8.4.5.2 Levels of Interrupt Control
          3. 26.8.4.5.3 Interrupt Events Description
            1. 26.8.4.5.3.1  Task File Error Status
            2. 26.8.4.5.3.2  Host Bus Fatal Error
            3. 26.8.4.5.3.3  Interface Fatal Error Status
            4. 26.8.4.5.3.4  Interface Non-Fatal Error Status
            5. 26.8.4.5.3.5  Overflow Status
            6. 26.8.4.5.3.6  Incorrect Port Multiplier Status
            7. 26.8.4.5.3.7  PHYReady Change Status
            8. 26.8.4.5.3.8  Port Connect Change Status
            9. 26.8.4.5.3.9  Descriptor Processed
            10. 26.8.4.5.3.10 Unknown FIS Interrupt
            11. 26.8.4.5.3.11 Set Device Bits Interrupt
            12. 26.8.4.5.3.12 DMA Setup FIS Interrupt
            13. 26.8.4.5.3.13 PIO Setup FIS Interrupt
            14. 26.8.4.5.3.14 Device to Host Register FIS Interrupt
          4. 26.8.4.5.4 Interrupt Condition Control
          5. 26.8.4.5.5 Command Completion Coalescing Interrupts
            1. 26.8.4.5.5.1 CCC Interrupt Based on Expired Timeout Value
            2. 26.8.4.5.5.2 CCC Interrupt Based on Completion Count
        6. 26.8.4.6  System Memory FIS Descriptors
          1. 26.8.4.6.1 Command List Structure Basics
          2. 26.8.4.6.2 Supported Types of Commands
          3. 26.8.4.6.3 Received FIS Structures
          4. 26.8.4.6.4 FIS Descriptors Summary
        7. 26.8.4.7  Transport Layer FIS-Based Interactions
          1. 26.8.4.7.1 Software Processing of the Port Command List
          2. 26.8.4.7.2 Handling the Received FIS Descriptors
        8. 26.8.4.8  DMA Port Configuration
        9. 26.8.4.9  Port Multiplier Operation
          1. 26.8.4.9.1 Command-Based Switching Mode
            1. 26.8.4.9.1.1 Port Multiplier NCQ and Non-NCQ Commands Generation
          2. 26.8.4.9.2 Port Multiplier Enumeration
        10. 26.8.4.10 Activity LED Generation Functionality
        11. 26.8.4.11 Supported Types of SATA Transfers
          1. 26.8.4.11.1 Supported Higher Level Protocols
        12. 26.8.4.12 SATA Controller AHCI Hardware Register Interface
      5. 26.8.5 SATA Controller Low Level Programming Model
        1. 26.8.5.1 Global Initialization
          1. 26.8.5.1.1 Surrounding Modules Global Initialization
          2. 26.8.5.1.2 SATA Controller Global Initialization
            1. 26.8.5.1.2.1 Main Sequence SATA Controller Global Initialization
            2. 26.8.5.1.2.2 SubSequence – Firmware Capability Writes
          3. 26.8.5.1.3 Issue Command - Main Sequence
          4. 26.8.5.1.4 Receive FIS—Main Sequence
      6. 26.8.6 SATA Controller Register Manual
        1. 26.8.6.1 SATA Controller Instance Summary
        2. 26.8.6.2 DWC_ahsata Registers
          1. 26.8.6.2.1 DWC_ahsata Register Summary
          2. 26.8.6.2.2 DWC_ahsata Register Description
        3. 26.8.6.3 SATAMAC_wrapper Registers
          1. 26.8.6.3.1 SATAMAC_wrapper Register Summary
          2. 26.8.6.3.2 SATAMAC_wrapper Register Description
    9. 26.9  PCIe Controller
      1. 26.9.1 PCIe Controller Subsystem Overview
        1. 26.9.1.1 PCIe Controllers Key Features
      2. 26.9.2 PCIe Controller Environment
      3. 26.9.3 PCIe Controllers Integration
      4. 26.9.4 PCIe SS Controller Functional Description
        1. 26.9.4.1 PCIe Controller Functional Block Diagram
        2. 26.9.4.2 PCIe Traffics
        3. 26.9.4.3 PCIe Controller Ports on L3_MAIN Interconnect
          1. 26.9.4.3.1 PCIe Controller Master Port
            1. 26.9.4.3.1.1 PCIe Controller Master Port to MMU Routing
          2. 26.9.4.3.2 PCIe Controller Slave Port
          3. 26.9.4.3.3 4298
        4. 26.9.4.4 PCIe Controller Reset Management
          1. 26.9.4.4.1 PCIe Reset Types and Stickiness
          2. 26.9.4.4.2 PCIe Reset Conditions
            1. 26.9.4.4.2.1 PCIe Main Reset
              1. 26.9.4.4.2.1.1 PCIe Subsystem Cold Main Reset Source
              2. 26.9.4.4.2.1.2 PCIe Subsystem Warm Main Reset Sources
            2. 26.9.4.4.2.2 PCIe Standard Specific Resets to the PCIe Core Logic
        5. 26.9.4.5 PCIe Controller Power Management
          1. 26.9.4.5.1 PCIe Protocol Power Management
            1. 26.9.4.5.1.1 PCIe Device/function power state (D-state)
            2. 26.9.4.5.1.2 PCIe Controller PIPE Powerstate (Powerdown Control)
          2. 26.9.4.5.2 PCIE Controller Clocks Management
            1. 26.9.4.5.2.1 PCIe Clock Domains
            2. 26.9.4.5.2.2 PCIe Controller Idle/Standby Clock Management Interfaces
              1. 26.9.4.5.2.2.1 PCIe Controller Master Standby Behavior
              2. 26.9.4.5.2.2.2 PCIe Controller Slave Idle/Disconnect Behavior
                1. 26.9.4.5.2.2.2.1 PCIe Controller Idle Sequence During D3cold/L3 State
        6. 26.9.4.6 PCIe Controller Interrupt Requests
          1. 26.9.4.6.1 PCIe Controller Main Hardware Management
            1. 26.9.4.6.1.1 PCIe Management Interrupt Events
            2. 26.9.4.6.1.2 PCIe Error Interrupt Events
            3. 26.9.4.6.1.3 Summary of PCIe Controller Main Hardware Interrupt Events
          2. 26.9.4.6.2 PCIe Controller Legacy and MSI Virtual Interrupts Management
            1. 26.9.4.6.2.1 Legacy PCI Interrupts (INTx)
              1. 26.9.4.6.2.1.1 Legacy PCI Interrupt Events Overview
              2. 26.9.4.6.2.1.2 Legacy PCI Interrupt Transmission (EP mode only)
              3. 26.9.4.6.2.1.3 Legacy PCI Interrupt Reception (RC mode only)
            2. 26.9.4.6.2.2 PCIe Controller Message Signaled Interrupts (MSI)
              1. 26.9.4.6.2.2.1 PCIe Specific MSI Interrupt Event Overview
              2. 26.9.4.6.2.2.2 PCIe Controller MSI Transmission Methods (EP mode)
                1. 26.9.4.6.2.2.2.1 PCIe Controller MSI transmission, hardware method
                2. 26.9.4.6.2.2.2.2 PCIe Controller MSI transmission, software method
              3. 26.9.4.6.2.2.3 PCIe Controller MSI Reception (RC mode)
          3. 26.9.4.6.3 PCIe Controller MSI Hardware Interrupt Events
        7. 26.9.4.7 PCIe Controller Address Spaces and Address Translation
        8. 26.9.4.8 PCIe Traffic Requesting and Responding
          1. 26.9.4.8.1 PCIe Memory-type (Mem) Traffic Management
            1. 26.9.4.8.1.1 PCIe Memory Requesting
            2. 26.9.4.8.1.2 PCIe Memory Responding
          2. 26.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management
            1. 26.9.4.8.2.1 RC Self-configuration (RC Only)
            2. 26.9.4.8.2.2 Configuration Requests over PCIe (RC Only)
            3. 26.9.4.8.2.3 Configuration Responding over PCIe (EP Only)
          3. 26.9.4.8.3 PCIe I/O-type (IO) traffic management
            1. 26.9.4.8.3.1 PCIe I/O requesting (RC only)
            2. 26.9.4.8.3.2 PCIe IO BAR initialization before enumeration (EP only)
            3. 26.9.4.8.3.3 PCIe I/O responding (PCI legacy EP only)
          4. 26.9.4.8.4 PCIe Message-type (Msg) traffic management
        9. 26.9.4.9 PCIe Programming Register Interface
          1. 26.9.4.9.1 PCIe Register Access
          2. 26.9.4.9.2 Double Mapping of the PCIe Local Control Registers
          3. 26.9.4.9.3 Base Address Registers (BAR) Initialization
      5. 26.9.5 PCIe Controller Low Level Programming Model
        1. 26.9.5.1 Surrounding Modules Global Initialization
        2. 26.9.5.2 Main Sequence of PCIe Controllers Initalization
      6. 26.9.6 PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
      7. 26.9.7 PCIe Controller Register Manual
        1. 26.9.7.1 PCIe Controller Instance Summary
        2. 26.9.7.2 PCIe_SS_EP_CFG_PCIe Registers
          1. 26.9.7.2.1 PCIe_SS_EP_CFG_PCIe Register Summary
          2. 26.9.7.2.2 PCIe_SS_EP_CFG_PCIe Register Description
          3. 26.9.7.2.3 4360
        3. 26.9.7.3 PCIe_SS_EP_CFG_DBICS Registers
          1. 26.9.7.3.1 PCIe_SS_EP_CFG_DBICS Register Summary
          2. 26.9.7.3.2 PCIe_SS_EP_CFG_DBICS Register Description
        4. 26.9.7.4 PCIe_SS_RC_CFG_DBICS Registers
          1. 26.9.7.4.1 PCIe_SS_RC_CFG_DBICS Register Summary
          2. 26.9.7.4.2 PCIe_SS_RC_CFG_DBICS Register Description
        5. 26.9.7.5 PCIe_SS_PL_CONF Registers
          1. 26.9.7.5.1 PCIe_SS_PL_CONF Register Summary
          2. 26.9.7.5.2 PCIe_SS_PL_CONF Register Description
        6. 26.9.7.6 PCIe_SS_EP_CFG_DBICS2 Registers
          1. 26.9.7.6.1 PCIe_SS_EP_CFG_DBICS2 Register Summary
          2. 26.9.7.6.2 PCIe_SS_EP_CFG_DBICS2 Register Description
        7. 26.9.7.7 PCIe_SS_RC_CFG_DBICS2 Registers
          1. 26.9.7.7.1 PCIe_SS_RC_CFG_DBICS2 Register Summary
          2. 26.9.7.7.2 PCIe_SS_RC_CFG_DBICS2 Register Description
        8. 26.9.7.8 PCIe_SS_TI_CONF Registers
          1. 26.9.7.8.1 PCIe_SS_TI_CONF Register Summary
          2. 26.9.7.8.2 PCIe_SS_TI_CONF Register Description
    10. 26.10 DCAN
      1. 26.10.1 DCAN Overview
        1. 26.10.1.1 Features
      2. 26.10.2 DCAN Environment
        1. 26.10.2.1 CAN Network Basics
      3. 26.10.3 DCAN Integration
      4. 26.10.4 DCAN Functional Description
        1. 26.10.4.1  Module Clocking Requirements
        2. 26.10.4.2  Interrupt Functionality
          1. 26.10.4.2.1 Message Object Interrupts
          2. 26.10.4.2.2 Status Change Interrupts
          3. 26.10.4.2.3 Error Interrupts
        3. 26.10.4.3  DMA Functionality
        4. 26.10.4.4  Local Power-Down Mode
          1. 26.10.4.4.1 Entering Local Power-Down Mode
          2. 26.10.4.4.2 Wakeup From Local Power Down
        5. 26.10.4.5  Parity Check Mechanism
          1. 26.10.4.5.1 Behavior on Parity Error
          2. 26.10.4.5.2 Parity Testing
        6. 26.10.4.6  Debug/Suspend Mode
        7. 26.10.4.7  Configuration of Message Objects Description
          1. 26.10.4.7.1 Configuration of a Transmit Object for Data Frames
          2. 26.10.4.7.2 Configuration of a Transmit Object for Remote Frames
          3. 26.10.4.7.3 Configuration of a Single Receive Object for Data Frames
          4. 26.10.4.7.4 Configuration of a Single Receive Object for Remote Frames
          5. 26.10.4.7.5 Configuration of a FIFO Buffer
        8. 26.10.4.8  Message Handling
          1. 26.10.4.8.1  Message Handler Overview
          2. 26.10.4.8.2  Receive/Transmit Priority
          3. 26.10.4.8.3  Transmission of Messages in Event Driven CAN Communication
          4. 26.10.4.8.4  Updating a Transmit Object
          5. 26.10.4.8.5  Changing a Transmit Object
          6. 26.10.4.8.6  Acceptance Filtering of Received Messages
          7. 26.10.4.8.7  Reception of Data Frames
          8. 26.10.4.8.8  Reception of Remote Frames
          9. 26.10.4.8.9  Reading Received Messages
          10. 26.10.4.8.10 Requesting New Data for a Receive Object
          11. 26.10.4.8.11 Storing Received Messages in FIFO Buffers
          12. 26.10.4.8.12 Reading From a FIFO Buffer
        9. 26.10.4.9  CAN Bit Timing
          1. 26.10.4.9.1 Bit Time and Bit Rate
            1. 26.10.4.9.1.1 Synchronization Segment
            2. 26.10.4.9.1.2 Propagation Time Segment
            3. 26.10.4.9.1.3 Phase Buffer Segments and Synchronization
            4. 26.10.4.9.1.4 Oscillator Tolerance Range
          2. 26.10.4.9.2 DCAN Bit Timing Registers
            1. 26.10.4.9.2.1 Calculation of the Bit Timing Parameters
            2. 26.10.4.9.2.2 Example for Bit Timing Calculation
        10. 26.10.4.10 Message Interface Register Sets
          1. 26.10.4.10.1 Message Interface Register Sets 1 and 2
          2. 26.10.4.10.2 IF3 Register Set
        11. 26.10.4.11 Message RAM
          1. 26.10.4.11.1 Structure of Message Objects
          2. 26.10.4.11.2 Addressing Message Objects in RAM
          3. 26.10.4.11.3 Message RAM Representation in Debug/Suspend Mode
          4. 26.10.4.11.4 Message RAM Representation in Direct Access Mode
        12. 26.10.4.12 CAN Operation
          1. 26.10.4.12.1 CAN Module Initialization
            1. 26.10.4.12.1.1 Configuration of CAN Bit Timing
            2. 26.10.4.12.1.2 Configuration of Message Objects
            3. 26.10.4.12.1.3 DCAN RAM Hardware Initialization
          2. 26.10.4.12.2 CAN Message Transfer (Normal Operation)
            1. 26.10.4.12.2.1 Automatic Retransmission
            2. 26.10.4.12.2.2 Auto-Bus-On
          3. 26.10.4.12.3 Test Modes
            1. 26.10.4.12.3.1 Silent Mode
            2. 26.10.4.12.3.2 Loopback Mode
            3. 26.10.4.12.3.3 External Loopback Mode
            4. 26.10.4.12.3.4 Loopback Mode Combined With Silent Mode
            5. 26.10.4.12.3.5 Software Control of CAN_TX Pin
        13. 26.10.4.13 GPIO Support
      5. 26.10.5 DCAN Register Manual
        1. 26.10.5.1 DCAN Instance Summary
        2. 26.10.5.2 DCAN Registers
          1. 26.10.5.2.1 DCAN Register Summary
          2. 26.10.5.2.2 DCAN Register Description
    11. 26.11 MCAN
      1. 26.11.1 MCAN Overview
        1. 26.11.1.1 Features
      2. 26.11.2 MCAN Environment
        1. 26.11.2.1 CAN Network Basics
      3. 26.11.3 MCAN Integration
      4. 26.11.4 MCAN Functional Description
        1. 26.11.4.1  Module Clocking Requirements
        2. 26.11.4.2  Interrupt and DMA Requests
          1. 26.11.4.2.1 Interrupt Requests
          2. 26.11.4.2.2 DMA Requests
          3. 26.11.4.2.3 4466
        3. 26.11.4.3  Fuseable CAN FD Operation Enable
        4. 26.11.4.4  Operating Modes
          1. 26.11.4.4.1 Software Initialization
          2. 26.11.4.4.2 Normal Operation
          3. 26.11.4.4.3 CAN FD Operation
          4. 26.11.4.4.4 Transmitter Delay Compensation
            1. 26.11.4.4.4.1 Description
            2. 26.11.4.4.4.2 Transmitter Delay Compensation Measurement
          5. 26.11.4.4.5 Restricted Operation Mode
          6. 26.11.4.4.6 Bus Monitoring Mode
          7. 26.11.4.4.7 Disabled Automatic Retransmission (DAR) Mode
            1. 26.11.4.4.7.1 Frame Transmission in DAR Mode
          8. 26.11.4.4.8 Power Down (Sleep Mode)
            1. 26.11.4.4.8.1 External Clock Stop Mode
            2. 26.11.4.4.8.2 Suspend Mode
            3. 26.11.4.4.8.3 Wakeup request
          9. 26.11.4.4.9 Test Modes
            1. 26.11.4.4.9.1 Internal Loop Back Mode
        5. 26.11.4.5  Timestamp Generation
          1. 26.11.4.5.1 External Timestamp Counter
        6. 26.11.4.6  Timeout Counter
        7. 26.11.4.7  Safety
          1. 26.11.4.7.1 ECC Wrapper
          2. 26.11.4.7.2 ECC Aggregator
            1. 26.11.4.7.2.1 ECC Aggregator Overview
            2. 26.11.4.7.2.2 ECC Aggregator Registers
            3. 26.11.4.7.2.3 Reads to ECC Control and Status Registers
            4. 26.11.4.7.2.4 ECC Interrupts
        8. 26.11.4.8  Rx Handling
          1. 26.11.4.8.1 Acceptance Filtering
            1. 26.11.4.8.1.1 Range Filter
            2. 26.11.4.8.1.2 Filter for specific IDs
            3. 26.11.4.8.1.3 Classic Bit Mask Filter
            4. 26.11.4.8.1.4 Standard Message ID Filtering
            5. 26.11.4.8.1.5 Extended Message ID Filtering
          2. 26.11.4.8.2 Rx FIFOs
            1. 26.11.4.8.2.1 Rx FIFO Blocking Mode
            2. 26.11.4.8.2.2 Rx FIFO Overwrite Mode
          3. 26.11.4.8.3 Dedicated Rx Buffers
            1. 26.11.4.8.3.1 Rx Buffer Handling
        9. 26.11.4.9  Tx Handling
          1. 26.11.4.9.1 Transmit Pause
          2. 26.11.4.9.2 Dedicated Tx Buffers
          3. 26.11.4.9.3 Tx FIFO
          4. 26.11.4.9.4 Tx Queue
          5. 26.11.4.9.5 Mixed Dedicated Tx Buffers/Tx FIFO
          6. 26.11.4.9.6 Mixed Dedicated Tx Buffers/Tx Queue
          7. 26.11.4.9.7 Transmit Cancellation
          8. 26.11.4.9.8 Tx Event Handling
        10. 26.11.4.10 FIFO Acknowledge Handling
        11. 26.11.4.11 Message RAM
          1. 26.11.4.11.1 Message RAM Configuration
          2. 26.11.4.11.2 Rx Buffer and FIFO Element
          3. 26.11.4.11.3 Tx Buffer Element
          4. 26.11.4.11.4 Tx Event FIFO Element
          5. 26.11.4.11.5 Standard Message ID Filter Element
          6. 26.11.4.11.6 Extended Message ID Filter Element
      5. 26.11.5 MCAN Register Manual
        1. 26.11.5.1 MCAN Instance Summary
        2. 26.11.5.2 MCAN Registers
          1. 26.11.5.2.1 MCAN Register Summary
          2. 26.11.5.2.2 MCAN Register Description
    12. 26.12 Gigabit Ethernet Switch (GMAC_SW)
      1. 26.12.1 GMAC_SW Overview
        1. 26.12.1.1 Features
        2. 26.12.1.2 4532
      2. 26.12.2 GMAC_SW Environment
        1. 26.12.2.1 G/MII Interface
        2. 26.12.2.2 RMII Interface
        3. 26.12.2.3 RGMII Interface
      3. 26.12.3 GMAC_SW Integration
      4. 26.12.4 GMAC_SW Functional Description
        1. 26.12.4.1  Functional Block Diagram
        2. 26.12.4.2  GMAC_SW Ports
          1. 26.12.4.2.1 Interface Mode Selection
        3. 26.12.4.3  Clocking
          1. 26.12.4.3.1 Subsystem Clocking
          2. 26.12.4.3.2 Interface Clocking
            1. 26.12.4.3.2.1 G/MII Interface Clocking
            2. 26.12.4.3.2.2 RGMII Interface Clocking
            3. 26.12.4.3.2.3 RMII Interface Clocking
            4. 26.12.4.3.2.4 MDIO Clocking
        4. 26.12.4.4  Software IDLE
        5. 26.12.4.5  Interrupt Functionality
          1. 26.12.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
          2. 26.12.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
          3. 26.12.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
          4. 26.12.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
            1. 26.12.4.5.4.1 EVNT_PEND( CPTS_PEND) Interrupt
            2. 26.12.4.5.4.2 Statistics Interrupt
            3. 26.12.4.5.4.3 Host Error interrupt
            4. 26.12.4.5.4.4 MDIO Interrupts
          5. 26.12.4.5.5 Interrupt Pacing
        6. 26.12.4.6  Reset Isolation
          1. 26.12.4.6.1 Reset Isolation Functional Description
        7. 26.12.4.7  Software Reset
        8. 26.12.4.8  CPSW_3G
          1. 26.12.4.8.1  CPDMA RX and TX Interfaces
            1. 26.12.4.8.1.1 Functional Operation
            2. 26.12.4.8.1.2 Receive DMA Interface
              1. 26.12.4.8.1.2.1 Receive DMA Host Configuration
              2. 26.12.4.8.1.2.2 Receive Channel Teardown
            3. 26.12.4.8.1.3 Transmit DMA Interface
              1. 26.12.4.8.1.3.1 Transmit DMA Host Configuration
              2. 26.12.4.8.1.3.2 Transmit Channel Teardown
            4. 26.12.4.8.1.4 Transmit Rate Limiting
            5. 26.12.4.8.1.5 Command IDLE
          2. 26.12.4.8.2  Address Lookup Engine (ALE)
            1. 26.12.4.8.2.1 Address Table Entry
              1. 26.12.4.8.2.1.1 Free Table Entry
              2. 26.12.4.8.2.1.2 Multicast Address Table Entry
              3. 26.12.4.8.2.1.3 VLAN/Multicast Address Table Entry
              4. 26.12.4.8.2.1.4 Unicast Address Table Entry
              5. 26.12.4.8.2.1.5 OUI Unicast Address Table Entry
              6. 26.12.4.8.2.1.6 VLAN/Unicast Address Table Entry
              7. 26.12.4.8.2.1.7 VLAN Table Entry
            2. 26.12.4.8.2.2 Packet Forwarding Processes
            3. 26.12.4.8.2.3 Learning Process
            4. 26.12.4.8.2.4 VLAN Aware Mode
            5. 26.12.4.8.2.5 VLAN Unaware Mode
          3. 26.12.4.8.3  Packet Priority Handling
          4. 26.12.4.8.4  FIFO Memory Control
          5. 26.12.4.8.5  FIFO Transmit Queue Control
            1. 26.12.4.8.5.1 Normal Priority Mode
            2. 26.12.4.8.5.2 Dual MAC Mode
            3. 26.12.4.8.5.3 Rate Limit Mode
          6. 26.12.4.8.6  Audio Video Bridging
            1. 26.12.4.8.6.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
              1. 26.12.4.8.6.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
              2. 26.12.4.8.6.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
            2. 26.12.4.8.6.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
              1. 26.12.4.8.6.2.1 Configuring the Device for 802.1Qav Operation:
          7. 26.12.4.8.7  Ethernet MAC Sliver (CPGMAC_SL)
            1. 26.12.4.8.7.1 G/MII Media Independent Interface
              1. 26.12.4.8.7.1.1 Data Reception
                1. 26.12.4.8.7.1.1.1 Receive Control
                2. 26.12.4.8.7.1.1.2 Receive Inter-Frame Interval
              2. 26.12.4.8.7.1.2 Data Transmission
                1. 26.12.4.8.7.1.2.1 Transmit Control
                2. 26.12.4.8.7.1.2.2 CRC Insertion
                3. 26.12.4.8.7.1.2.3 MTXER
                4. 26.12.4.8.7.1.2.4 Adaptive Performance Optimization (APO)
                5. 26.12.4.8.7.1.2.5 Inter-Packet-Gap Enforcement
                6. 26.12.4.8.7.1.2.6 Back Off
                7. 26.12.4.8.7.1.2.7 Programmable Transmit Inter-Packet Gap
                8. 26.12.4.8.7.1.2.8 Speed, Duplex and Pause Frame Support Negotiation
            2. 26.12.4.8.7.2 RMII Interface
              1. 26.12.4.8.7.2.1 Features
              2. 26.12.4.8.7.2.2 RMII Receive (RX)
              3. 26.12.4.8.7.2.3 RMII Transmit (TX)
            3. 26.12.4.8.7.3 RGMII Interface
              1. 26.12.4.8.7.3.1 RGMII Features
              2. 26.12.4.8.7.3.2 RGMII Receive (RX)
              3. 26.12.4.8.7.3.3 In-Band Mode of Operation
              4. 26.12.4.8.7.3.4 Forced Mode of Operation
              5. 26.12.4.8.7.3.5 RGMII Transmit (TX)
            4. 26.12.4.8.7.4 Frame Classification
          8. 26.12.4.8.8  Embedded Memories
          9. 26.12.4.8.9  Flow Control
            1. 26.12.4.8.9.1 CPPI Port Flow Control
            2. 26.12.4.8.9.2 Ethernet Port Flow Control
              1. 26.12.4.8.9.2.1 Receive Flow Control
                1. 26.12.4.8.9.2.1.1 Collision Based Receive Buffer Flow Control
                2. 26.12.4.8.9.2.1.2 IEEE 802.3X Based Receive Flow Control
              2. 26.12.4.8.9.2.2 Transmit Flow Control
          10. 26.12.4.8.10 Short Gap
          11. 26.12.4.8.11 Switch Latency
          12. 26.12.4.8.12 Emulation Control
          13. 26.12.4.8.13 FIFO Loopback
          14. 26.12.4.8.14 Device Level Ring (DLR) Support
          15. 26.12.4.8.15 Energy Efficient Ethernet Support (802.3az)
          16. 26.12.4.8.16 CPSW_3G Network Statistics
            1. 26.12.4.8.16.1 4639
        9. 26.12.4.9  Static Packet Filter (SPF)
          1. 26.12.4.9.1 SPF Overview
          2. 26.12.4.9.2 SPF Functional Description
            1. 26.12.4.9.2.1 SPF Block Diagram
            2. 26.12.4.9.2.2 Interrupts
            3. 26.12.4.9.2.3 Protocol Header Extractor
            4. 26.12.4.9.2.4 Programmable Rule Engine
              1. 26.12.4.9.2.4.1 Internal Registers
              2. 26.12.4.9.2.4.2 Packet Buffer
            5. 26.12.4.9.2.5 Intrusion Event Logger
            6. 26.12.4.9.2.6 Rate Limiter
            7. 26.12.4.9.2.7 Rule Engine Instruction Set Architecture
              1. 26.12.4.9.2.7.1 Instruction Format
              2. 26.12.4.9.2.7.2 Operand Field
              3. 26.12.4.9.2.7.3 Arithmetic/Logical Function Field
              4. 26.12.4.9.2.7.4 Operation Field
          3. 26.12.4.9.3 Programming Guide
            1. 26.12.4.9.3.1 Initialization Routine
            2. 26.12.4.9.3.2 Interrupt Service Routine
            3. 26.12.4.9.3.3 Rule Engine Example Program
        10. 26.12.4.10 Common Platform Time Sync (CPTS)
          1. 26.12.4.10.1 CPTS Architecture
          2. 26.12.4.10.2 CPTS Initialization
          3. 26.12.4.10.3 Time Stamp Value
          4. 26.12.4.10.4 Event FIFO
          5. 26.12.4.10.5 Time Sync Events
            1. 26.12.4.10.5.1 Time Stamp Push Event
            2. 26.12.4.10.5.2 Time Stamp Counter Rollover Event
            3. 26.12.4.10.5.3 Time Stamp Counter Half-rollover Event
            4. 26.12.4.10.5.4 Hardware Time Stamp Push Event
            5. 26.12.4.10.5.5 Ethernet Port Events
          6. 26.12.4.10.6 CPTS Interrupt Handling
        11. 26.12.4.11 CPPI Buffer Descriptors
          1. 26.12.4.11.1 TX Buffer Descriptors
            1. 26.12.4.11.1.1 CPPI TX Data Word 0
            2. 26.12.4.11.1.2 CPPI TX Data Word 1
            3. 26.12.4.11.1.3 CPPI TX Data Word 2
            4. 26.12.4.11.1.4 CPPI TX Data Word 3
          2. 26.12.4.11.2 RX Buffer Descriptors
            1. 26.12.4.11.2.1 CPPI RX Data Word 0
            2. 26.12.4.11.2.2 CPPI RX Data Word 1
            3. 26.12.4.11.2.3 CPPI RX Data Word 2
            4. 26.12.4.11.2.4 CPPI RX Data Word 3
        12. 26.12.4.12 MDIO
          1. 26.12.4.12.1 MDIO Frame Formats
          2. 26.12.4.12.2 MDIO Functional Description
      5. 26.12.5 GMAC_SW Programming Guide
        1. 26.12.5.1 Transmit Operation
        2. 26.12.5.2 Receive Operation
        3. 26.12.5.3 MDIO Software Interface
          1. 26.12.5.3.1 Initializing the MDIO Module
          2. 26.12.5.3.2 Writing Data To a PHY Register
          3. 26.12.5.3.3 Reading Data From a PHY Register
        4. 26.12.5.4 Initialization and Configuration of CPSW
      6. 26.12.6 GMAC_SW Register Manual
        1. 26.12.6.1  GMAC_SW Instance Summary
        2. 26.12.6.2  SS Registers
          1. 26.12.6.2.1 SS Register Summary
          2. 26.12.6.2.2 SS Register Description
        3. 26.12.6.3  PORT Registers
          1. 26.12.6.3.1 PORT Register Summary
          2. 26.12.6.3.2 PORT Register Description
        4. 26.12.6.4  CPDMA registers
          1. 26.12.6.4.1 CPDMA Register Summary
          2. 26.12.6.4.2 CPDMA Register Description
        5. 26.12.6.5  STATS Registers
          1. 26.12.6.5.1 STATS Register Summary
          2. 26.12.6.5.2 STATS Register Description
        6. 26.12.6.6  STATERAM Registers
          1. 26.12.6.6.1 STATERAM Register Summary
          2. 26.12.6.6.2 STATERAM Register Description
        7. 26.12.6.7  CPTS registers
          1. 26.12.6.7.1 CPTS Register Summary
          2. 26.12.6.7.2 CPTS Register Description
        8. 26.12.6.8  ALE registers
          1. 26.12.6.8.1 ALE Register Summary
          2. 26.12.6.8.2 ALE Register Description
        9. 26.12.6.9  SL registers
          1. 26.12.6.9.1 SL Register Summary
          2. 26.12.6.9.2 SL Register Description
        10. 26.12.6.10 MDIO registers
          1. 26.12.6.10.1 MDIO Register Summary
          2. 26.12.6.10.2 MDIO Register Description
        11. 26.12.6.11 WR registers
          1. 26.12.6.11.1 WR Register Summary
          2. 26.12.6.11.2 WR Register Description
        12. 26.12.6.12 SPF Registers
          1. 26.12.6.12.1 SPF Register Summary
          2. 26.12.6.12.2 SPF Register Description
    13. 26.13 Media Local Bus (MLB)
      1. 26.13.1 MLB Overview
      2. 26.13.2 MLB Environment
        1. 26.13.2.1 MLB IO Cell Controls
        2. 26.13.2.2 Doubling the MLB Clock Line Frequency
      3. 26.13.3 MLB Integration
      4. 26.13.4 MLB Functional Description
        1. 26.13.4.1 Block Diagram
          1. 26.13.4.1.1 MediaLB Core Block
          2. 26.13.4.1.2 Routing Fabric Block
          3. 26.13.4.1.3 Data Buffer RAM
          4. 26.13.4.1.4 Channel Table RAM
            1. 26.13.4.1.4.1 Channel Allocation Table
            2. 26.13.4.1.4.2 Channel Descriptor Table
          5. 26.13.4.1.5 DMA Block
            1. 26.13.4.1.5.1 Synchronous Channel Descriptor
            2. 26.13.4.1.5.2 Isochronous Channel Descriptors
            3. 26.13.4.1.5.3 Asynchronous and Control Channel Descriptors
              1. 26.13.4.1.5.3.1 Single-Packet Mode
              2. 26.13.4.1.5.3.2 Multiple-Packet Mode
        2. 26.13.4.2 Software and Data Flow for MLBSS
          1. 26.13.4.2.1 Data Flow For Receive Channels
          2. 26.13.4.2.2 Data Flow for Transmit Channels
        3. 26.13.4.3 MLB Priority On The L3_MAIN Interconnect
      5. 26.13.5 MLB Programming Guide
        1. 26.13.5.1 Global Initialization
          1. 26.13.5.1.1 Surrounding Modules Global Initialization
          2. 26.13.5.1.2 MLBSS Global Initialization
            1. 26.13.5.1.2.1 Channel Initialization
        2. 26.13.5.2 MLBSS Operational Modes Configuration
          1. 26.13.5.2.1 Channel Servicing
          2. 26.13.5.2.2 Channel Table RAM Access
      6. 26.13.6 MLB Register Manual
        1. 26.13.6.1 MLB Instance Summary
        2. 26.13.6.2 MLB registers
          1. 26.13.6.2.1 MLB Register Summary
          2. 26.13.6.2.2 MLB Register Description
  29. 27eMMC/SD/SDIO
    1. 27.1 eMMC/SD/SDIO Overview
      1. 27.1.1 eMMC/SD/SDIO Features
    2. 27.2 eMMC/SD/SDIO Environment
      1. 27.2.1 eMMC/SD/SDIO Functional Modes
        1. 27.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
      2. 27.2.2 Protocol and Data Format
        1. 27.2.2.1 Protocol
        2. 27.2.2.2 Data Format
    3. 27.3 eMMC/SD/SDIO Integration
    4. 27.4 eMMC/SD/SDIO Functional Description
      1. 27.4.1  Block Diagram
      2. 27.4.2  Resets
        1. 27.4.2.1 Hardware Reset
        2. 27.4.2.2 Software Reset
      3. 27.4.3  Power Management
      4. 27.4.4  Interrupt Requests
        1. 27.4.4.1 Interrupt-Driven Operation
        2. 27.4.4.2 Polling
        3. 27.4.4.3 Asynchronous Interrupt
      5. 27.4.5  DMA Modes
        1. 27.4.5.1 Master DMA Operations
          1. 27.4.5.1.1 Descriptor Table Description
          2. 27.4.5.1.2 Requirements for Descriptors
            1. 27.4.5.1.2.1 Data Length
            2. 27.4.5.1.2.2 Supported Features
            3. 27.4.5.1.2.3 Error Generation
          3. 27.4.5.1.3 Advanced DMA Description
        2. 27.4.5.2 Slave DMA Operations
          1. 27.4.5.2.1 DMA Receive Mode
          2. 27.4.5.2.2 DMA Transmit Mode
      6. 27.4.6  Mode Selection
      7. 27.4.7  Buffer Management
        1. 27.4.7.1 Data Buffer
          1. 27.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship
          2. 27.4.7.1.2 Data Buffer Status
      8. 27.4.8  Transfer Process
        1. 27.4.8.1 Different Types of Commands
        2. 27.4.8.2 Different Types of Responses
      9. 27.4.9  Transfer or Command Status and Errors Reporting
        1. 27.4.9.1 Busy Time-Out for R1b, R5b Response Type
        2. 27.4.9.2 Busy Time-Out After Write CRC Status
        3. 27.4.9.3 Write CRC Status Time-Out
        4. 27.4.9.4 Read Data Time-Out
        5. 27.4.9.5 Boot Acknowledge Time-Out
      10. 27.4.10 Auto Command 12 Timings
        1. 27.4.10.1 Auto CMD12 Timings During Write Transfer
        2. 27.4.10.2 Auto CMD12 Timings During Read Transfer
      11. 27.4.11 Transfer Stop
      12. 27.4.12 Output Signals Generation
        1. 27.4.12.1 Generation on Falling Edge of MMC Clock
        2. 27.4.12.2 Generation on Rising Edge of MMC Clock
      13. 27.4.13 Sampling Clock Tuning
      14. 27.4.14 Card Boot Mode Management
        1. 27.4.14.1 Boot Mode Using CMD0
        2. 27.4.14.2 Boot Mode With CMD Line Tied to 0
      15. 27.4.15 MMC CE-ATA Command Completion Disable Management
      16. 27.4.16 Test Registers
      17. 27.4.17 eMMC/SD/SDIO Hardware Status Features
    5. 27.5 eMMC/SD/SDIO Programming Guide
      1. 27.5.1 Low-Level Programming Models
        1. 27.5.1.1 Global Initialization
          1. 27.5.1.1.1 Surrounding Modules Global Initialization
          2. 27.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow
            1. 27.5.1.1.2.1 Enable Interface and Functional Clock for MMC Controller
            2. 27.5.1.1.2.2 MMCHS Soft Reset Flow
            3. 27.5.1.1.2.3 Set MMCHS Default Capabilities
            4. 27.5.1.1.2.4 Wake-Up Configuration
            5. 27.5.1.1.2.5 MMC Host and Bus Configuration
        2. 27.5.1.2 Operational Modes Configuration
          1. 27.5.1.2.1 Basic Operations for eMMC/SD/SDIO Host Controller
            1. 27.5.1.2.1.1 Card Detection, Identification, and Selection
              1. 27.5.1.2.1.1.1 CMD Line Reset Procedure
            2. 27.5.1.2.1.2 Read/Write Transfer Flow in DMA Mode With Interrupt
              1. 27.5.1.2.1.2.1 DATA Lines Reset Procedure
            3. 27.5.1.2.1.3 Read/Write Transfer Flow in DMA Mode With Polling
            4. 27.5.1.2.1.4 Read/Write Transfer Flow Without DMA With Polling
            5. 27.5.1.2.1.5 Read/Write Transfer Flow in CE-ATA Mode
            6. 27.5.1.2.1.6 Suspend-Resume Flow
              1. 27.5.1.2.1.6.1 Suspend Flow
              2. 27.5.1.2.1.6.2 Resume Flow
            7. 27.5.1.2.1.7 Basic Operations – Steps Detailed
              1. 27.5.1.2.1.7.1 Command Transfer Flow
              2. 27.5.1.2.1.7.2 MMCHS Clock Frequency Change
              3. 27.5.1.2.1.7.3 Bus Width Selection
          2. 27.5.1.2.2 Bus Voltage Selection
          3. 27.5.1.2.3 Boot Mode Configuration
            1. 27.5.1.2.3.1 Boot Using CMD0
            2. 27.5.1.2.3.2 Boot With CMD Line Tied to 0
          4. 27.5.1.2.4 SDR104/HS200 DLL Tuning Procedure
    6. 27.6 eMMC/SD/SDIO Register Manual
      1. 27.6.1 eMMC/SD/SDIO Instance Summary
      2. 27.6.2 eMMC/SD/SDIO Registers
        1. 27.6.2.1 eMMC/SD/SDIO Register Summary
        2. 27.6.2.2 eMMC/SD/SDIO Register Description
  30. 28Shared PHY Component Subsystem
    1. 28.1 SATA PHY Subsystem
      1. 28.1.1 SATA PHY Subsystem Overview
      2. 28.1.2 SATA PHY Subsystem Environment
        1. 28.1.2.1 SATA PHY I/O Signals
      3. 28.1.3 SATA PHY Subsystem Integration
      4. 28.1.4 SATA PHY Subsystem Functional Description
        1. 28.1.4.1 SATA PLL Controller L4 Interface Adapter Functional Description
        2. 28.1.4.2 SATA PHY Serializer and Deserializer Functional Descriptions
          1. 28.1.4.2.1 SATA PHY Reset
          2. 28.1.4.2.2 SATA_PHY Clocking
            1. 28.1.4.2.2.1 SATA_PHY Input Clocks
            2. 28.1.4.2.2.2 SATA_PHY Output Clocks
          3. 28.1.4.2.3 SATA_PHY Power Management
            1. 28.1.4.2.3.1 SATA_PHY Power-Up/-Down Sequences
            2. 28.1.4.2.3.2 SATA_PHY Low-Power Modes
          4. 28.1.4.2.4 SATA_PHY Hardware Requests
        3. 28.1.4.3 SATA Clock Generator Subsystem Functional Description
          1. 28.1.4.3.1 SATA DPLL Clock Generator Overview
          2. 28.1.4.3.2 SATA DPLL Clock Generator Reset
          3. 28.1.4.3.3 SATA DPLL Low-Power Modes
          4. 28.1.4.3.4 SATA DPLL Clocks Configuration
            1. 28.1.4.3.4.1 SATA DPLL Input Clock Control
            2. 28.1.4.3.4.2 SATA DPLL Output Clock Configuration
              1. 28.1.4.3.4.2.1 SATA DPLL Output Clock Gating
          5. 28.1.4.3.5 SATA DPLL Subsystem Architecture
          6. 28.1.4.3.6 SATA DPLL Clock Generator Modes and State Transitions
            1. 28.1.4.3.6.1 SATA Clock Generator Power Up
            2. 28.1.4.3.6.2 SATA DPLL Sequences
            3. 28.1.4.3.6.3 SATA DPLL Locked Mode
            4. 28.1.4.3.6.4 SATA DPLL Idle-Bypass Mode
            5. 28.1.4.3.6.5 SATA DPLL MN-Bypass Mode
            6. 28.1.4.3.6.6 SATA DPLL Error Conditions
          7. 28.1.4.3.7 SATA PLL Controller Functions
            1. 28.1.4.3.7.1 SATA PLL Controller Register Access
            2. 28.1.4.3.7.2 SATA DPLL Clock Programming Sequence
            3. 28.1.4.3.7.3 SATA DPLL Recommended Values
      5. 28.1.5 SATA PHY Subsystem Low-Level Programming Model
    2. 28.2 USB3_PHY Subsystem
      1. 28.2.1 USB3_PHY Subsystem Overview
      2. 28.2.2 USB3_PHY Subsystem Environment
        1. 28.2.2.1 USB3_PHY I/O Signals
      3. 28.2.3 USB3_PHY Subsystem Integration
      4. 28.2.4 USB3_PHY Subsystem Functional Description
        1. 28.2.4.1 Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
        2. 28.2.4.2 USB3_PHY Serializer and Deserializer Functional Descriptions
          1. 28.2.4.2.1 USB3_PHY Module Resets
            1. 28.2.4.2.1.1 Hardware Reset
            2. 28.2.4.2.1.2 Software Reset
          2. 28.2.4.2.2 USB3_PHY Subsystem Clocking
            1. 28.2.4.2.2.1 USB3_PHY Subsystem Input Clocks
            2. 28.2.4.2.2.2 USB3_PHY Subsystem Output Clocks
          3. 28.2.4.2.3 USB3_PHY Power Management
            1. 28.2.4.2.3.1 USB3_PHY Power-Up/-Down Sequences
            2. 28.2.4.2.3.2 USB3_PHY Low-Power Modes
            3. 28.2.4.2.3.3 Clock Gating
          4. 28.2.4.2.4 USB3_PHY Hardware Requests
        3. 28.2.4.3 USB3_PHY Clock Generator Subsystem Functional Description
          1. 28.2.4.3.1 USB3_PHY DPLL Clock Generator Overview
          2. 28.2.4.3.2 USB3_PHY DPLL Clock Generator Reset
          3. 28.2.4.3.3 USB3_PHY DPLL Low-Power Modes
          4. 28.2.4.3.4 USB3_PHY DPLL Clocks Configuration
            1. 28.2.4.3.4.1 USB3_PHY DPLL Input Clock Control
            2. 28.2.4.3.4.2 USB3_PHY DPLL Output Clock Configuration
              1. 28.2.4.3.4.2.1 USB3_PHY DPLL Output Clock Gating
          5. 28.2.4.3.5 USB3_PHY DPLL Subsystem Architecture
          6. 28.2.4.3.6 USB3_PHY DPLL Clock Generator Modes and State Transitions
            1. 28.2.4.3.6.1 USB3_PHY Clock Generator Power Up
            2. 28.2.4.3.6.2 USB3_PHY DPLL Sequences
            3. 28.2.4.3.6.3 USB3_PHY DPLL Locked Mode
            4. 28.2.4.3.6.4 USB3_PHY DPLL Idle-Bypass Mode
            5. 28.2.4.3.6.5 USB3_PHY DPLL MN-Bypass Mode
            6. 28.2.4.3.6.6 USB3_PHY DPLL Error Conditions
          7. 28.2.4.3.7 USB3_PHY PLL Controller Functions
            1. 28.2.4.3.7.1 USB3_PHY PLL Controller Register Access
            2. 28.2.4.3.7.2 4936
            3. 28.2.4.3.7.3 USB3_PHY DPLL Clock Programming Sequence
            4. 28.2.4.3.7.4 USB3_PHY DPLL Recommended Values
      5. 28.2.5 USB3_PHY Subsystem Low-Level Programming Model
    3. 28.3 USB3 PHY and SATA PHY Register Manual
      1. 28.3.1 USB3 PHY and SATA PHY Instance Summary
      2. 28.3.2 USB3_PHY_RX Registers
        1. 28.3.2.1 USB3_PHY_RX Register Summary
        2. 28.3.2.2 USB3_PHY_RX Register Description
      3. 28.3.3 USB3_PHY_TX Registers
        1. 28.3.3.1 USB3_PHY_TX Register Summary
        2. 28.3.3.2 USB3_PHY_TX Register Description
      4. 28.3.4 SATA_PHY_RX Registers
        1. 28.3.4.1 SATA_PHY_RX Register Summary
        2. 28.3.4.2 SATA_PHY_RX Register Description
      5. 28.3.5 SATA_PHY_TX Registers
        1. 28.3.5.1 SATA_PHY_TX Register Summary
        2. 28.3.5.2 SATA_PHY_TX Register Description
      6. 28.3.6 DPLLCTRL Registers
        1. 28.3.6.1 DPLLCTRL Register Summary
        2. 28.3.6.2 DPLLCTRL Register Description
    4. 28.4 PCIe PHY Subsystem
      1. 28.4.1 PCIe PHY Subsystem Overview
        1. 28.4.1.1 PCIe PHY Subsystem Key Features
      2. 28.4.2 PCIe PHY Subsystem Environment
        1. 28.4.2.1 PCIe PHY I/O Signals
      3. 28.4.3 PCIe Shared PHY Subsystem Integration
      4. 28.4.4 PCIe PHY Subsystem Functional Description
        1. 28.4.4.1 PCIe PHY Subsystem Block Diagram
        2. 28.4.4.2 OCP2SCP Functional Description
          1. 28.4.4.2.1 OCP2SCP Reset
            1. 28.4.4.2.1.1 Hardware Reset
            2. 28.4.4.2.1.2 Software Reset
          2. 28.4.4.2.2 OCP2SCP Power Management
            1. 28.4.4.2.2.1 Idle Mode
            2. 28.4.4.2.2.2 Clock Gating
          3. 28.4.4.2.3 OCP2SCP Timing Registers
        3. 28.4.4.3 PCIe PHY Serializer and Deserializer Functional Descriptions
          1. 28.4.4.3.1 PCIe PHY Module Resets
            1. 28.4.4.3.1.1 Hardware Reset
            2. 28.4.4.3.1.2 Software Reset
          2. 28.4.4.3.2 PCIe PHY Subsystem Clocking
            1. 28.4.4.3.2.1 PCIe PHY Subsystem Input Clocks
            2. 28.4.4.3.2.2 PCIe PHY Subsystem Output Clocks
          3. 28.4.4.3.3 PCIe PHY Power Management
            1. 28.4.4.3.3.1 PCIe PHY Power-Up/-Down Sequences
            2. 28.4.4.3.3.2 PCIe PHY Low-Power Modes
            3. 28.4.4.3.3.3 Clock Gating
          4. 28.4.4.3.4 PCIe PHY Hardware Requests
        4. 28.4.4.4 PCIe PHY Clock Generator Subsystem Functional Description
          1. 28.4.4.4.1 PCIe PHY DPLL Clock Generator
            1. 28.4.4.4.1.1 PCIe PHY DPLL Clock Generator Overview
            2. 28.4.4.4.1.2 PCIe PHY DPLL Clock Generator Reset
            3. 28.4.4.4.1.3 PCIe PHY DPLL Low-Power Modes
            4. 28.4.4.4.1.4 PCIe PHY DPLL Clocks Configuration
              1. 28.4.4.4.1.4.1 PCIe PHY DPLL Input Clock Control
              2. 28.4.4.4.1.4.2 PCIe PHY DPLL Output Clock Configuration
                1. 28.4.4.4.1.4.2.1 PCIe PHY DPLL Output Clock Gating
            5. 28.4.4.4.1.5 PCIe PHY DPLL Subsystem Architecture
            6. 28.4.4.4.1.6 PCIe PHY DPLL Clock Generator Modes and State Transitions
              1. 28.4.4.4.1.6.1 PCIe PHY Clock Generator Power Up
              2. 28.4.4.4.1.6.2 PCIe PHY DPLL Sequences
              3. 28.4.4.4.1.6.3 PCIe PHY DPLL Locked Mode
              4. 28.4.4.4.1.6.4 PCIe PHY DPLL Idle-Bypass Mode
              5. 28.4.4.4.1.6.5 PCIe PHY DPLL Low Power Stop Mode
              6. 28.4.4.4.1.6.6 PCIe PHY DPLL Clock Programming Sequence
              7. 28.4.4.4.1.6.7 PCIe PHY DPLL Recommended Values
          2. 28.4.4.4.2 PCIe PHY APLL Clock Generator
            1. 28.4.4.4.2.1 PCIe PHY APLL Clock Generator Overview
            2. 28.4.4.4.2.2 PCIe PHY APLL Clock Generator Reset
            3. 28.4.4.4.2.3 PCIe PHY APLL Low-Power Mode
            4. 28.4.4.4.2.4 PCIe PHY APLL Clocks Configuration
              1. 28.4.4.4.2.4.1 PCIe PHY APLL Input Clock Control
              2. 28.4.4.4.2.4.2 PCIe PHY APLL Output Clock Configuration
                1. 28.4.4.4.2.4.2.1 PCIe PHY APLL Output Clock Gating
            5. 28.4.4.4.2.5 PCIe PHY APLL Subsystem Architecture
            6. 28.4.4.4.2.6 PCIe PHY APLL Clock Generator Modes and State Transitions
              1. 28.4.4.4.2.6.1 PCIe PHY APLL Clock Generator Power Up
              2. 28.4.4.4.2.6.2 PCIe PHY APLL Sequences
              3. 28.4.4.4.2.6.3 PCIe PHY APLL Locked Mode
          3. 28.4.4.4.3 ACSPCIE reference clock buffer
      5. 28.4.5 PCIePHY Subsystem Low-Level Programming Model
      6. 28.4.6 PCIe PHY Subsystem Register Manual
        1. 28.4.6.1 PCIe PHY Instance Summary
          1. 28.4.6.1.1 PCIe_PHY_RX Registers
            1. 28.4.6.1.1.1 PCIe_PHY_RX Register Summary
            2. 28.4.6.1.1.2 PCIe_PHY_RX Register Description
          2. 28.4.6.1.2 PCIe_PHY_TX Registers
            1. 28.4.6.1.2.1 PCIe_PHY_TX Register Summary
            2. 28.4.6.1.2.2 PCIe_PHY_TX Register Description
          3. 28.4.6.1.3 OCP2SCP Registers
            1. 28.4.6.1.3.1 OCP2SCP Register Summary
            2. 28.4.6.1.3.2 OCP2SCP Register Description
  31. 29General-Purpose Interface
    1. 29.1 General-Purpose Interface Overview
    2. 29.2 General-Purpose Interface Environment
      1. 29.2.1 General-Purpose Interface as a Keyboard Interface
      2. 29.2.2 General-Purpose Interface Signals
    3. 29.3 General-Purpose Interface Integration
    4. 29.4 General-Purpose Interface Functional Description
      1. 29.4.1 General-Purpose Interface Block Diagram
      2. 29.4.2 General-Purpose Interface Interrupt and Wake-Up Features
        1. 29.4.2.1 Synchronous Path: Interrupt Request Generation
        2. 29.4.2.2 Asynchronous Path: Wake-Up Request Generation
        3. 29.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State
        4. 29.4.2.4 Interrupt (or Wake-Up) Line Release
      3. 29.4.3 General-Purpose Interface Clock Configuration
        1. 29.4.3.1 Clocking
      4. 29.4.4 General-Purpose Interface Hardware and Software Reset
      5. 29.4.5 General-Purpose Interface Power Management
        1. 29.4.5.1 Power Domain
        2. 29.4.5.2 Power Management
          1. 29.4.5.2.1 Idle Scheme
          2. 29.4.5.2.2 Operating Modes
          3. 29.4.5.2.3 System Power Management and Wakeup
          4. 29.4.5.2.4 Module Power Saving
      6. 29.4.6 General-Purpose Interface Interrupt and Wake-Up Requests
        1. 29.4.6.1 Interrupt Requests Generation
        2. 29.4.6.2 Wake-Up Requests Generation
      7. 29.4.7 General-Purpose Interface Channels Description
      8. 29.4.8 General-Purpose Interface Data Input/Output Capabilities
      9. 29.4.9 General-Purpose Interface Set-and-Clear Protocol
        1. 29.4.9.1 Description
        2. 29.4.9.2 Clear Instruction
          1. 29.4.9.2.1 Clear Register Addresses
          2. 29.4.9.2.2 Clear Instruction Example
        3. 29.4.9.3 Set Instruction
          1. 29.4.9.3.1 Set Register Addresses
          2. 29.4.9.3.2 Set Instruction Example
    5. 29.5 General-Purpose Interface Programming Guide
      1. 29.5.1 General-Purpose Interface Low-Level Programming Models
        1. 29.5.1.1 Global Initialization
          1. 29.5.1.1.1 Surrounding Modules Global Initialization
          2. 29.5.1.1.2 General-Purpose Interface Module Global Initialization
        2. 29.5.1.2 General-Purpose Interface Operational Modes Configuration
          1. 29.5.1.2.1 General-Purpose Interface Read Input Register
          2. 29.5.1.2.2 General-Purpose Interface Set Bit Function
          3. 29.5.1.2.3 General-Purpose Interface Clear Bit Function
    6. 29.6 General-Purpose Interface Register Manual
      1. 29.6.1 General-Purpose Interface Instance Summary
      2. 29.6.2 General-Purpose Interface Registers
        1. 29.6.2.1 General-Purpose Interface Register Summary
        2. 29.6.2.2 General-Purpose Interface Register Description
  32. 30Keyboard Controller
    1. 30.1 Keyboard Controller Overview
    2. 30.2 Keyboard Controller Environment
      1. 30.2.1 Keyboard Controller Functions/Modes
      2. 30.2.2 Keyboard Controller Signals
      3. 30.2.3 Protocols and Data Formats
    3. 30.3 Keyboard Controller Integration
    4. 30.4 Keyboard Controller Functional Description
      1. 30.4.1 Keyboard Controller Block Diagram
      2. 30.4.2 Keyboard Controller Software Reset
      3. 30.4.3 Keyboard Controller Power Management
      4. 30.4.4 Keyboard Controller Interrupt Requests
      5. 30.4.5 Keyboard Controller Software Mode
      6. 30.4.6 Keyboard Controller Hardware Decoding Modes
        1. 30.4.6.1 Functional Modes
        2. 30.4.6.2 Keyboard Controller Timer
        3. 30.4.6.3 State-Machine Status
        4. 30.4.6.4 Keyboard Controller Interrupt Generation
          1. 30.4.6.4.1 Interrupt-Generation Scheme
          2. 30.4.6.4.2 Keyboard Buffer and Missed Events (Overrun Feature)
      7. 30.4.7 Keyboard Controller Key Coding Registers
      8. 30.4.8 Keyboard Controller Register Access
        1. 30.4.8.1 Write Registers Access
        2. 30.4.8.2 Read Registers Access
    5. 30.5 Keyboard Controller Programming Guide
      1. 30.5.1 Keyboard Controller Low-Level Programming Models
        1. 30.5.1.1 Global Initialization
          1. 30.5.1.1.1 Surrounding Modules Global Initialization
          2. 30.5.1.1.2 Keyboard Controller Global Initialization
            1. 30.5.1.1.2.1 Main Sequence – Keyboard Controller Global Initialization
        2. 30.5.1.2 Operational Modes Configuration
          1. 30.5.1.2.1 Keyboard Controller in Hardware Decoding Mode (Default Mode)
            1. 30.5.1.2.1.1 Main Sequence – Keyboard Controller Hardware Mode
          2. 30.5.1.2.2 Keyboard Controller Software Scanning Mode
            1. 30.5.1.2.2.1 Main Sequence – Keyboard Controller Software Mode
          3. 30.5.1.2.3 Using the Timer
          4. 30.5.1.2.4 State-Machine Status Register
        3. 30.5.1.3 Keyboard Controller Events Servicing
    6. 30.6 Keyboard Controller Register Manual
      1. 30.6.1 Keyboard Controller Instance Summary
      2. 30.6.2 Keyboard Controller Registers
        1. 30.6.2.1 Keyboard Controller Register Summary
        2. 30.6.2.2 Keyboard Controller Register Description
  33. 31Pulse-Width Modulation Subsystem
    1. 31.1 PWM Subsystem Resources
      1. 31.1.1 PWMSS Overview
        1. 31.1.1.1 PWMSS Key Features
        2. 31.1.1.2 PWMSS Unsupported Fetaures
      2. 31.1.2 PWMSS Environment
        1. 31.1.2.1 PWMSS I/O Interface
      3. 31.1.3 PWMSS Integration
        1. 31.1.3.1 PWMSS Module Interfaces Implementation
          1. 31.1.3.1.1 Device Specific PWMSS Features
          2. 31.1.3.1.2 Daisy-Chain Connectivity between PWMSS Modules
          3. 31.1.3.1.3 eHRPWM Modules Time Base Clock Gating
      4. 31.1.4 PWMSS Subsystem Power, Reset and Clock Configuration
        1. 31.1.4.1 PWMSS Local Clock Management
        2. 31.1.4.2 PWMSS Modules Local Clock Gating
        3. 31.1.4.3 PWMSS Software Reset
      5. 31.1.5 PWMSS_CFG Register Manual
        1. 31.1.5.1 PWMSS_CFG Instance Summary
        2. 31.1.5.2 PWMSS_CFG Registers
          1. 31.1.5.2.1 PWMSS_CFG Register Summary
          2. 31.1.5.2.2 PWMSS_CFG Register Description
    2. 31.2 Enhanced PWM (ePWM) Module
    3. 31.3 Enhanced Capture (eCAP) Module
    4. 31.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
  34. 32Viterbi-Decoder Coprocessor
    1. 32.1 VCP Overview
      1. 32.1.1 VCP Features
    2. 32.2 VCP Integration
    3. 32.3 VCP Functional Description
      1. 32.3.1  VCP Block Diagram
      2. 32.3.2  VCP Internal Interfaces
        1. 32.3.2.1 VCP Power Management
          1. 32.3.2.1.1 Idle Mode
        2. 32.3.2.2 VCP Clocks
        3. 32.3.2.3 VCP Resets
        4. 32.3.2.4 Interrupt Requests
        5. 32.3.2.5 EDMA Requests
      3. 32.3.3  Functional Overview
        1. 32.3.3.1 Theoretical Basics of the Convolutional Code.
        2. 32.3.3.2 5161
      4. 32.3.4  VCP Architecture
        1. 32.3.4.1 Sliding Windows Processing
          1. 32.3.4.1.1 Tailed Traceback Mode
          2. 32.3.4.1.2 Mixed Traceback Mode
          3. 32.3.4.1.3 Convergent Traceback Mode
          4. 32.3.4.1.4 F, R, and C Limitations
          5. 32.3.4.1.5 Yamamoto Parameters
          6. 32.3.4.1.6 Input FIFO (Branch Metrics)
          7. 32.3.4.1.7 Output FIFO (Decisions)
      5. 32.3.5  VCP Input Data
        1. 32.3.5.1 Branch Metrics Calculations
      6. 32.3.6  Soft Input Dynamic Ranges
      7. 32.3.7  VCP Memory Sleep Mode
      8. 32.3.8  Decision Data
      9. 32.3.9  Endianness
        1. 32.3.9.1 Branch Metrics
          1. 32.3.9.1.1 Hard Decisions
          2. 32.3.9.1.2 Soft Decisions
      10. 32.3.10 VCP Output Parameters
      11. 32.3.11 Event Generation
        1. 32.3.11.1 VCPnXEVT Generation
        2. 32.3.11.2 VCPnREVT Generation
      12. 32.3.12 Operational Modes
        1. 32.3.12.1 Debugging Features
      13. 32.3.13 Errors and Status
    4. 32.4 VCP Modules Programming Guide
      1. 32.4.1 EDMA Resources
        1. 32.4.1.1 VCP1 and VCP2 Dedicated EDMA Resources
        2. 32.4.1.2 Special VCP EDMA Programming Considerations
          1. 32.4.1.2.1 Input Configuration Parameters Transfer
          2. 32.4.1.2.2 Branch Metrics Transfer
          3. 32.4.1.2.3 Decisions Transfer
          4. 32.4.1.2.4 Hard-Decisions Mode
          5. 32.4.1.2.5 Soft-Decisions Mode
          6. 32.4.1.2.6 Output Parameters Transfer
      2. 32.4.2 Input Configuration Words
    5. 32.5 VCP Register Manual
      1. 32.5.1 VCP1 and VCP2 Instance Summary
      2. 32.5.2 VCP Registers
        1. 32.5.2.1 VCP Register Summary
        2. 32.5.2.2 VCP1 and VCP2 Data Registers Description
        3. 32.5.2.3 VCP1 and VCP2 Configuration Registers Description
  35. 33Audio Tracking Logic
    1. 33.1 ATL Overview
    2. 33.2 ATL Environment
      1. 33.2.1 ATL Functions
      2. 33.2.2 ATL Signals Descriptions
    3. 33.3 ATL Integration
      1. 33.3.1 ATL Distribution on Interconnects
      2. 33.3.2 ATL Regions Allocations
    4. 33.4 ATL Functional Description
      1. 33.4.1 Block Diagram
      2. 33.4.2 Source Signal Control
      3. 33.4.3 ATL Clock and Reset Configuration
    5. 33.5 ATL Register Manual
      1. 33.5.1 ATL Instance Summary
      2. 33.5.2 ATL Register Summary
      3. 33.5.3 ATL Register Description
  36. 34Initialization
    1. 34.1 Initialization Overview
      1. 34.1.1 Terminology
      2. 34.1.2 Initialization Process
    2. 34.2 Preinitialization
      1. 34.2.1 Power Requirements
      2. 34.2.2 Interaction With the PMIC Companion
      3. 34.2.3 Clock, Reset, and Control
        1. 34.2.3.1 Overview
        2. 34.2.3.2 Clocking Scheme
        3. 34.2.3.3 Reset Configuration
          1. 34.2.3.3.1 ON/OFF Interconnect and Power-On-Reset
          2. 34.2.3.3.2 Warm Reset
          3. 34.2.3.3.3 Peripheral Reset by GPIO
          4. 34.2.3.3.4 Warm Reset Impact on GPIOs
        4. 34.2.3.4 PMIC Control
        5. 34.2.3.5 PMIC Request Signals
      4. 34.2.4 Sysboot Configuration
        1. 34.2.4.1 GPMC Configuration for XIP/NAND
        2. 34.2.4.2 System Clock Speed Selection
        3. 34.2.4.3 QSPI Redundant SBL Images Offset
        4. 34.2.4.4 Booting Device Order Selection
        5. 34.2.4.5 5242
        6. 34.2.4.6 Boot Peripheral Pin Multiplexing
    3. 34.3 Device Initialization by ROM Code
      1. 34.3.1 Booting Overview
        1. 34.3.1.1 Booting Types
        2. 34.3.1.2 ROM Code Architecture
      2. 34.3.2 Memory Maps
        1. 34.3.2.1 ROM Memory Map
        2. 34.3.2.2 RAM Memory Map
      3. 34.3.3 Overall Booting Sequence
      4. 34.3.4 Startup and Configuration
        1. 34.3.4.1 Startup
        2. 34.3.4.2 Control Module Configuration
        3. 34.3.4.3 PRCM Module Mode Configuration
        4. 34.3.4.4 Clocking Configuration
        5. 34.3.4.5 Booting Device List Setup
      5. 34.3.5 Peripheral Booting
        1. 34.3.5.1 Description
        2. 34.3.5.2 Initialization Phase for UART Boot
        3. 34.3.5.3 Initialization Phase for USB Boot
          1. 34.3.5.3.1 Initialization Procedure
          2. 34.3.5.3.2 SATA Peripheral Device Flashing over USB Interface
          3. 34.3.5.3.3 USB Driver Descriptors
          4. 34.3.5.3.4 5265
          5. 34.3.5.3.5 USB Customized Vendor and Product IDs
          6. 34.3.5.3.6 USB Driver Functionality
      6. 34.3.6 Fast External Booting
        1. 34.3.6.1 Overview
        2. 34.3.6.2 Fast External Booting Procedure
      7. 34.3.7 Memory Booting
        1. 34.3.7.1 Overview
        2. 34.3.7.2 Non-XIP Memory
        3. 34.3.7.3 XIP Memory
          1. 34.3.7.3.1 GPMC Initialization
        4. 34.3.7.4 NAND
          1. 34.3.7.4.1 Initialization and NAND Detection
          2. 34.3.7.4.2 NAND Read Sector Procedure
        5. 34.3.7.5 SPI/QSPI Flash Devices
        6. 34.3.7.6 eMMC Memories and SD Cards
          1. 34.3.7.6.1 eMMC Memories
            1. 34.3.7.6.1.1 System Conditions and Limitations
            2. 34.3.7.6.1.2 eMMC Memory Connection
          2. 34.3.7.6.2 SD Cards
            1. 34.3.7.6.2.1 System Conditions and Limitations
            2. 34.3.7.6.2.2 SD Card Connection
            3. 34.3.7.6.2.3 Booting Procedure
            4. 34.3.7.6.2.4 eMMC Partitions Handling in Alternative Boot Operation Mode
              1. 34.3.7.6.2.4.1 eMMC Devices Preflashing
              2. 34.3.7.6.2.4.2 eMMC Device State After ROM Code Execution
              3. 34.3.7.6.2.4.3 Consideration on device Global Warm Reset
              4. 34.3.7.6.2.4.4 Booting Image Size
              5. 34.3.7.6.2.4.5 Booting Image Layout
          3. 34.3.7.6.3 Initialization and Detection
          4. 34.3.7.6.4 Read Sector Procedure
          5. 34.3.7.6.5 File System Handling
            1. 34.3.7.6.5.1 MBR and FAT File System
        7. 34.3.7.7 SATA Device Boot Operation
          1. 34.3.7.7.1 SATA Booting Overview
          2. 34.3.7.7.2 SATA Power-Up Initialization Sequence
          3. 34.3.7.7.3 System Conditions and Limitations for SATA Boot
          4. 34.3.7.7.4 SATA Read Sector Procedure in FAT Mode
      8. 34.3.8 Image Format
        1. 34.3.8.1 Overview
        2. 34.3.8.2 Configuration Header
          1. 34.3.8.2.1 CHSETTINGS Item
          2. 34.3.8.2.2 CHFLASH Item
          3. 34.3.8.2.3 CHMMCSD Item
          4. 34.3.8.2.4 CHQSPI Item
        3. 34.3.8.3 GP Header
        4. 34.3.8.4 Image Execution
      9. 34.3.9 Tracing
    4. 34.4 Services for HLOS Support
      1. 34.4.1 Hypervisor
      2. 34.4.2 Caches Maintenance
      3. 34.4.3 CP15 Registers
      4. 34.4.4 Wakeup Generator
      5. 34.4.5 Arm Timer
      6. 34.4.6 MReq Domain
  37. 35On-Chip Debug Support
    1. 35.1  Introduction
      1. 35.1.1 Key Features
    2. 35.2  Debug Interfaces
      1. 35.2.1 IEEE1149.1
      2. 35.2.2 Debug (Trace) Port
      3. 35.2.3 Trace Connector and Board Layout Considerations
    3. 35.3  Debugger Connection
      1. 35.3.1 ICEPick Module
      2. 35.3.2 ICEPick Boot Modes
        1. 35.3.2.1 Default Boot Mode
        2. 35.3.2.2 Wait-In-Reset
      3. 35.3.3 Dynamic TAP Insertion
        1. 35.3.3.1 ICEPick Secondary TAPs
    4. 35.4  Primary Debug Support
      1. 35.4.1 Processor Native Debug Support
        1. 35.4.1.1 Cortex-A15 Processor
        2. 35.4.1.2 Cortex-M4 Processor
        3. 35.4.1.3 DSP C66x
        4. 35.4.1.4 IVA Arm968
        5. 35.4.1.5 ARP32
        6. 35.4.1.6 5341
      2. 35.4.2 Cross-Triggering
        1. 35.4.2.1 SoC-Level Cross-Triggering
        2. 35.4.2.2 Cross-Triggering With External Device
      3. 35.4.3 Suspend
        1. 35.4.3.1 Debug Aware Peripherals and Host Processors
    5. 35.5  Real-Time Debug
      1. 35.5.1 Real-Time Debug Events
        1. 35.5.1.1 Emulation Interrupts
    6. 35.6  Power, Reset, and Clock Management Debug Support
      1. 35.6.1 Power and Clock Management
        1. 35.6.1.1 Power and Clock Control Override From Debugger
          1. 35.6.1.1.1 Debugger Directives
            1. 35.6.1.1.1.1 FORCEACTIVE Debugger Directive
            2. 35.6.1.1.1.2 INHIBITSLEEP Debugger Directive
          2. 35.6.1.1.2 Intrusive Debug Model
        2. 35.6.1.2 Debug Across Power Transition
          1. 35.6.1.2.1 Nonintrusive Debug Model
          2. 35.6.1.2.2 Debug Context Save and Restore
            1. 35.6.1.2.2.1 Debug Context Save
            2. 35.6.1.2.2.2 Debug Context Restore
      2. 35.6.2 Reset Management
        1. 35.6.2.1 Debugger Directives
          1. 35.6.2.1.1 Assert Reset
          2. 35.6.2.1.2 Block Reset
          3. 35.6.2.1.3 Wait-In-Reset
    7. 35.7  Performance Monitoring
      1. 35.7.1 MPU Subsystem Performance Monitoring
        1. 35.7.1.1 Performance Monitoring Unit
        2. 35.7.1.2 L2 Cache Controller
      2. 35.7.2 IPU Subsystem Performance Monitoring
        1. 35.7.2.1 Subsystem Counter Timer Module
        2. 35.7.2.2 Cache Events
      3. 35.7.3 DSP Subsystem Performance Monitoring
        1. 35.7.3.1 Advanced Event Triggering
      4. 35.7.4 EVE Subsystem Performance Monitoring
        1. 35.7.4.1 EVE Subsystem Counter Timer Module
        2. 35.7.4.2 EVE Subsystem SCTM Events
    8. 35.8  MPU Memory Adaptor (MPU_MA) Watchpoint
    9. 35.9  Processor Trace
      1. 35.9.1 Cortex-A15 Processor Trace
      2. 35.9.2 DSP Processor Trace
      3. 35.9.3 Trace Export
        1. 35.9.3.1 Trace Exported to External Trace Receiver
        2. 35.9.3.2 Trace Captured Into On-Chip Trace Buffer
        3. 35.9.3.3 Trace Exported Through USB
    10. 35.10 System Instrumentation
      1. 35.10.1  MIPI STM (CT_STM)
      2. 35.10.2  System Trace Export
        1. 35.10.2.1 CT_STM ATB Export
        2. 35.10.2.2 Trace Streams Interleaving
      3. 35.10.3  Software Instrumentation
        1. 35.10.3.1 MPU Software Instrumentation
        2. 35.10.3.2 SoC Software Instrumentation
      4. 35.10.4  OCP Watchpoint
        1. 35.10.4.1 OCP Target Traffic Monitoring
        2. 35.10.4.2 Messages Triggered from System Events
        3. 35.10.4.3 DMA Transfer Profiling
      5. 35.10.5  IVA Pipeline
      6. 35.10.6  EVE SMSET
      7. 35.10.7  L3 NOC Statistics Collector
        1. 35.10.7.1 L3 Target Load Monitoring
        2. 35.10.7.2 L3 Master Latency Monitoring
          1. 35.10.7.2.1  SC_LAT0 Configuration
          2. 35.10.7.2.2  SC_LAT1 Configuration
          3. 35.10.7.2.3  SC_LAT2 Configuration
          4. 35.10.7.2.4  SC_LAT3 Configuration
          5. 35.10.7.2.5  SC_LAT4 Configuration
          6. 35.10.7.2.6  SC_LAT5 Configuration
          7. 35.10.7.2.7  SC_LAT6 Configuration
          8. 35.10.7.2.8  SC_LAT7 Configuration
          9. 35.10.7.2.9  SC_LAT8 Configuration
          10. 35.10.7.2.10 Statistics Collector Alarm Mode
          11. 35.10.7.2.11 Statistics Collector Suspend Mode
      8. 35.10.8  PM Instrumentation
      9. 35.10.9  CM Instrumentation
      10. 35.10.10 Master-ID Encoding
        1. 35.10.10.1 Software Masters
        2. 35.10.10.2 Hardware Masters
    11. 35.11 Concurrent Debug Modes
    12. 35.12 DRM Register Manual
      1. 35.12.1 DRM Instance Summary
      2. 35.12.2 DRM Registers
        1. 35.12.2.1 DRM Register Summary
        2. 35.12.2.2 DRM Register Description
  38. 36Revision History
13.2.6.3.2 DISPC Register Description
Table 13-169 DISPC_REVISION
Address Offset0x0000 0000
Physical Address0x5800 1000InstanceDISPC
DescriptionIP Revision
TypeR
313029282726252423222120191817161514131211109876543210
REVISION
BitsField NameDescriptionTypeReset
31:0REVISIONIP revisionRSee(1).
(1) TI internal data
Table 13-170 DISPC_SYSCONFIG
Address Offset0x0000 0010
Physical Address0x5800 1010InstanceDISPC
DescriptionThis register allows to control various parameters of the OCP interface.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMIDLEMODERESERVEDCLOCKACTIVITYRESERVEDWARMRESETSIDLEMODEENWAKEUPSOFTRESETAUTOIDLE
BitsField NameDescriptionTypeReset
31:14RESERVEDWrite 0s for future compatibility. Reads returns 0.R0x00000
13:12MIDLEMODEMaster interface power management, standby/wait controlRW0x0
0x0: Force-standby. MStandby is only asserted when the module is disabled. MStandby is only asserted when the module is disabled.
0x1: No-Standby: MStandby is never asserted.
0x2: Smart-Standby. MStandby is asserted based on the internal activity of the module.
0x3: Reserved
11:10RESERVEDWrite 0s for future compatibility. Reads returns 0R0x0
9:8CLOCKACTIVITYClocks activity during wake up mode periodRW0x0
0x0: OCP and functional clocks can be switched off.
0x1: Functional clocks can be switched off and OCP clocks are maintained during wake up period.
0x2: OCP clocks can be switched off and Functional clocks are maintained during wake up period.
0x3: OCP and functional clocks are maintained during wake-up period.
7:6RESERVEDWrite 0s for future compatibility. Reads returns 0R0x0
5WARMRESETWarm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged.RW0
0x0: Normal mode
0x1: The warm reset is set.
4:3SIDLEMODESlave interface power management, Idle req/ack controlRW0x0
0x0: Force-idle. An idle request is acknowledged unconditionally.
0x1: No-idle. An idle request is never acknowledged.
0x2: Smart-idle. Acknowledgment to an idle request is given based on the internal activity of the module.
0x3: Reserved
2ENWAKEUPWakeUp feature controlRW0
0x0: Wakeup is disabled.
0x1: Wakeup is enabled.
1SOFTRESETSoftware reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0.RW0
0x0: Normal mode
0x1: The module is reset.
0AUTOIDLEInternal interface clock gating strategyRW1
0x0: Interface clock is free-running.
0x1: Automatic interface L3_MAIN gating strategy is applied, based on the OCP interface activity. Automatic functional clock gating is also applied to the functional clock based on the module activity (for instance DISPC_<pipe>_ATTRIBUTES.ENABLE).
Table 13-171 DISPC_SYSSTATUS
Address Offset0x0000 0014
Physical Address0x5800 1014InstanceDISPC
DescriptionThis register provides status information about the module, excluding the interrupt status information.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDRESETDONE
BitsField NameDescriptionTypeReset
31:1RESERVEDWrite 0s for future compatibility. Reads return 0.R0x000000
0RESETDONEInternal reset monitoringR1
Read 0x0: Internal module reset is on-going.
Read 0x1: Reset completed
Table 13-172 DISPC_IRQSTATUS
Address Offset0x0000 0018
Physical Address0x5800 1018InstanceDISPC
DescriptionThis register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit
TypeRW
313029282726252423222120191817161514131211109876543210
FLIPIMMEDIATEDONE_IRQFRAMEDONE3_IRQACBIASCOUNTSTATUS3_IRQVSYNC3_IRQSYNCLOST3_IRQWBINCOMPLETEERROR_IRQWBBUFFEROVERFLOW_IRQFRAMEDONETV_IRQFRAMEDONEWB_IRQFRAMEDONE2_IRQACBIASCOUNTSTATUS2_IRQVID3BUFFERUNDERFLOW_IRQVID3ENDWINDOW_IRQVSYNC2_IRQSYNCLOST2_IRQWAKEUP_IRQSYNCLOSTTV_IRQSYNCLOST1_IRQVID2ENDWINDOW_IRQVID2BUFFERUNDERFLOW_IRQVID1ENDWINDOW_IRQVID1BUFFERUNDERFLOW_IRQOCPERROR_IRQPALETTEGAMMALOADING_IRQGFXENDWINDOW_IRQGFXBUFFERUNDERFLOW_IRQPROGRAMMEDLINENUMBER_IRQACBIASCOUNTSTATUS1_IRQEVSYNC_ODD_IRQEVSYNC_EVEN_IRQVSYNC1_IRQFRAMEDONE1_IRQ
BitsField NameDescriptionTypeReset
31FLIPIMMEDIATEDONE_IRQFlip Immediate Done. The DMA engine has acknowledged the immediate BA change, and software can write the new BA0.RW
W1toClr		0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
30FRAMEDONE3_IRQFrame done for the third LCD. The third LCD output has been disabled by user. All the data have been sent.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
29ACBIASCOUNT
STATUS3_IRQ		AC bias count status for the third LCDRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
28VSYNC3_IRQVertical synchronization for the third LCDRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
27SYNCLOST3_IRQSynchronization lost on the third LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the third LCD output.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
26WBUNCOMPLETE
ERROR_IRQ		Write-back DMA buffer is flushed before it is completely drained.RW
W1toClr		0
In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers are lost (implying last few pixels/lines are corrupted in the captured frame in memory). This interrupt is an indication of that case and will trigger every frame
0x0: READS: Event is false.
WRITES: Status bit unchanged
0x1: READS: Event is true (Pending)
WRITES: Status bit is reset
25WBBUFFER
OVERFLOW_IRQ		Write-back DMA buffer overflow. The DMA buffer is full.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
24FRAME
DONETV_IRQ		Frame done for the TV. The TV output has been disabled by user. All the data have been sent.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
23FRAME
DONEWB_IRQ		Frame done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory. It is available only when the write-back pipeline transfers back to memory the output of one of the pipelines. In case of overlay capture, the interrupt is not generated and the user shall use the FrameDone for the corresponding captured output.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
22FRAME
DONE2_IRQ		Frame done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
21ACBIASCOUNT
STATUS2_IRQ		AC bias count status for the secondary LCDRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
20VID3BUFFER
UNDERFLOW_IRQ		Video 3 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
19VID3END
WINDOW_IRQ		The end of the video 3 window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
18VSYNC2_IRQVertical synchronization for the secondary LCDRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
17SYNC
LOST2_IRQ		Synchronization lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
16WAKEUP_IRQWakeupRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
15SYNCLOST
TV_IRQ		Synchronization lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
14SYNC
LOST1_IRQ		Synchronizationl ost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
13VID2END
WINDOW_IRQ		The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
12VID2BUFFER
UNDERFLOW_IRQ		Video 2 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
11VID1END
WINDOW_IRQ		The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
10VID1BUFFER
UNDERFLOW_IRQ		Video 1 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
9OCPERROR_IRQOCP error. L3_MAIN Interconnect has sent SResp=ERR.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
8PALETTEGAMMA
LOADING_IRQ		Palette Gamma loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.RW
W1toClr		0
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
7GFXEND
WINDOW_IRQ		The end of the graphics wndow has been reached. It is detected by the overlay manager when the full graphics has been displayed.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
6GFXBUFFER
UNDERFLOW_IRQ		Graphics DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
5PROGRAMMED
LINENUMBER_IRQ		Programmed line number. It indicates that the scan of the primary LCD has reached the programmed user line number.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
4ACBIASCOUNT
STATUS1_IRQ		AC bias count status for the primary LCDRW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
3EVSYNC_
ODD_IRQ		VSYNC for odd field from the TV encoder (HDMI)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
2EVSYNC_
EVEN_IRQ		VSYNC for even field from the TV encoder (HDMI)RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
1VSYNC1_IRQVertical synchronization for the primary LCD.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
0FRAME
DONE1_IRQ		Frame done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.RW
W1toClr		0
0x0: READS: Event is false. WRITES: Status bit unchanged.
0x1: READS: Event is true (pending). WRITES: Status bit is reset.
Table 13-173 DISPC_IRQENABLE
Address Offset0x0000 001C
Physical Address0x5800 101CInstanceDISPC
DescriptionThis register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis
TypeRW
313029282726252423222120191817161514131211109876543210
FLIPIMMEDIATEDONE_ENFRAMEDONE3_ENACBIASCOUNTSTATUS3_ENVSYNC3_ENSYNCLOST3_ENWBUNCOMPLETEERROR_ENWBBUFFEROVERFLOW_ENFRAMEDONETV_ENFRAMEDONEWB_ENFRAMEDONE2_ENACBIASCOUNTSTATUS2_ENVID3BUFFERUNDERFLOW_ENVID3ENDWINDOW_ENVSYNC2_ENSYNCLOST2_ENWAKEUP_ENSYNCLOSTTV_ENSYNCLOST1_ENVID2ENDWINDOW_ENVID2BUFFERUNDERFLOW_ENENDVID1WINDOW_ENVID1BUFFERUNDERFLOW_ENOCPERROR_ENPALETTEGAMMA_ENGFXENDWINDOW_ENGFXBUFFERUNDERFLOW_ENPROGRAMMEDLINENUMBER_ENACBIASCOUNTSTATUS1_ENEVSYNC_ODD_ENEVSYNC_EVEN_ENVSYNC1_ENFRAMEDONE_EN
BitsField NameDescriptionTypeReset
31FLIPIMMEDIATEDONE_ENFlip Immediate Done. The DMA engine has acknowledged the immediate BA change, and software can write the new BA0.RW0
0x0: FrameDone for the primary LCD output is masked
0x1: FrameDone for the primary LCD output generates an interrupt when it occurs
30FRAME
DONE3_EN		Frame done for the third LCD. The third LCD output has been disabled by user. All the data have been sent.RW0
0x0: Frame Done for the secondary LCD is masked.
0x1: Frame Done for the secondary LCD generates an interrupt when it occurs.
29ACBIASCOUNT
STATUS3_EN		AC Bias count status for the third LCDRW0
0x0: ACBiasCountStatus for the secondary LCD output is masked
0x1: ACBiasCountStatus for the secondary LCD output generates an interrupt when it occurs
28VSYNC3_ENVertical synchronization for the third LCDRW0
0x0: VSYNC for the secondary LCD output is masked.
0x1: VSYNC for the secondary LCD output generates an interrupt when it occurs.
27SYNC
LOST3_EN		Synchronization lost on the third LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the third LCD output.RW0
0x0: Synchronization Lost on the secondary LCD output is masked.
0x1: Synchronization Lost on the secondary LCD output generates an interrupt when it occurs.
26WBUNCOMPLETE
ERROR_EN		The write back buffer has been flushed before been fully drained. Enable.RW0
0x0: Interrupt is masked.
0x1: Interrupt is enabled.
25WBBUFFER
OVERFLOW_EN		Write-back DMA buffer overflow. The DMA buffer is full.RW0
0x0: WBBufferOverflow is masked.
0x1: WBBufferOverflow generates an interrupt when it occurs.
24FRAME
DONETV_EN		Frame done for the TV. The TV output has been disabled by user. All the data have been sent.RW0
0x0: Frame Done for the TV output is masked.
0x1: Frame Done for the TV output generates an interrupt when it occurs.
23FRAME
DONEWB_EN		Frame done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory.RW0
0x0: Frame done for the write-back is masked.
0x1: Frame done for the write-back generates an interrupt when it occurs.
22FRAME
DONE2_EN		Frame done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent.RW0
0x0: Frame done for the secondary LCD is masked.
0x1: Frame done for the secondary LCD generates an interrupt when it occurs.
21ACBIASCOUNT
STATUS2_EN		AC Bias count status for the secondary LCDRW0
0x0: ACBiasCountStatus for the secondary LCD output is masked.
0x1: ACBiasCountStatus for the secondary LCD output generates an interrupt when it occurs.
20VID3BUFFER
UNDERFLOW_EN		Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)RW0
0x0: Vid3BufferUnderflow is masked.
0x1: Vid3BufferUnderflow generates an interrupt when it occurs.
19VID3END
WINDOW_EN		The end of the video 3 window has been reached. It is detected by the overlay manager when the full video 3 has been displayed.RW0
0x0: Vid3EndWindow is masked.
0x1: Vid3EndWindow generates an interrupt when it occurs.
18VSYNC2_ENVertical synchronization for the secondary LCDRW0
0x0: VSYNC for the secondary LCD output is masked.
0x1: VSYNC for the secondary LCD output generates an interrupt when it occurs.
17SYNC
LOST2_EN		Synchronization lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output.RW0
0x0: Synchronization Lost on the secondary LCD output is masked.
0x1: Synchronization Lost on the secondary LCD output generates an interrupt when it occurs.
16WAKEUP_ENWake up maskRW0
0x0: WakeUp is masked.
0x1: WakeUp generates an interrupt when it occurs.
15SYNC
LOSTTV_EN		Synchronization lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output.RW0
0x0: Synchronization Lost on the TV output is masked.
0x1: Synchronization Lost on the TV output generates an interrupt when it occurs.
14SYNC
LOST1_EN		Synchronization lost for the primary LCDRW0
0x0: SyncLost for the primary LCD output is masked.
0x1: SyncLost for the primary LCD output generates an interrupt when it occurs.
13VID2END
WINDOW_EN		The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed.RW0
0x0: Vid2EndWindow is masked.
0x1: Vid2EndWindow generates an interrupt when it occurs.
12VID2BUFFER
UNDERFLOW_EN		Video 2 DMA buffer underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)RW0
0x0: Vid2BufferUnderflow is masked.
0x1: Vid2BufferUnderflow generates an interrupt when it occurs.
11ENDVID1
WINDOW_EN		The end of the video 1 window has been reached. It is detected by the overlay manager when the full video 1 has been displayed.RW0
0x0: EndVid1Window is masked.
0x1: EndVid1Window generates an interrupt when it occurs.
10VID1BUFFER
UNDERFLOW_EN		Video 1 DMA buffer underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)RW0
0x0: Vid1bufferunderflow is masked.
0x1: Vid1bufferunderflow generates an interrupt when it occurs.
9OCPERROR_ENOCP Error. L3_MAIN Interconnect has sent SResp=ERR.RW0
0x0: OCPError is masked.
0x1: OCPError generates an interrupt when it occurs.
8PALETTE
GAMMA_EN		Palette gamma loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.RW0
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
0x0: PaletteGamma is masked.
0x1: PaletteGamma generates an interrupt when it occurs.
7GFXEND
WINDOW_EN		The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed.RW0
0x0: GfxEndWindow is masked.
0x1: GfxEndWindow generates an interrupt when it occurs.
6GFXBUFFER
UNDERFLOW_EN		Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)RW0
0x0: GfxBufferUnderflow is masked.
0x1: GfxBufferUnderflow generates an interrupt when it occurs.
5PROGRAMMED
LINENUMBER_EN		Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number.RW0
0x0: ProgrammedLineNumber is masked.
0x1: ProgrammedLineNumber generates an interrupt when it occurs.
4ACBIASCOUNT
STATUS1_EN		AC Bias count status for the primary LCDRW0
0x0: ACBiascountstatus for the primary LCD output is masked.
0x1: ACBiascountstatus for the primary LCD output generates an interrupt when it occurs.
3EVSYNC_ODD_ENVSYNC for odd field from the TV encoder (HDMI)RW0
0x0: EVSYNC_ODD for the TV output is masked.
0x1: EVSYNC_ODD for the TV output generates an interrupt when it occurs.
2EVSYNC_EVEN_ENVSYNC for even field from the TV encoder (HDMI)RW0
0x0: EVSYNC_EVEN for the TV output is masked.
0x1: EVSYNC_EVEN for the TV output generates an interrupt when it occurs.
1VSYNC1_ENVertical synchronization for the primary LCD.RW0
0x0: VSYNC for the primary LCD output is masked.
0x1: VSYNC for the primary LCD output generates an interrupt when it occurs.
0FRAMEDONE_ENFrame done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent.RW0
0x0: Frame Done for the primary LCD output is masked.
0x1: FrameDone for the primary LCD output generates an interrupt when it occurs.
Table 13-174 DISPC_CONTROL1
Address Offset0x0000 0040
Physical Address0x5800 1040InstanceDISPC
DescriptionThe control register configures the Display Controller module for the primary LCD and TV outputs.
TypeRW
313029282726252423222120191817161514131211109876543210
SPATIALTEMPORALDITHERINGFRAMESLCDENABLEPOLLCDENABLESIGNALPCKFREEENABLETDMUNUSEDBITSTDMCYCLEFORMATTDMPARALLELMODETDMENABLEHTGPOUT1GPOUT0GPIN1GPIN0OVERLAYOPTIMIZATIONSTALLMODERESERVEDTFTDATALINESSTDITHERENABLEGOTVGOLCDM8BSTNTFTMONOCOLORTVENABLELCDENABLE
BitsField NameDescriptionTypeReset
31:30SPATIALTEMPORAL
DITHERINGFRAMES		Spatial/temporal dithering number of frames for the primary LCD output
wr: VFP start period of primary LCD		RW0x0
0x0: Spatial only
0x1: Spatial and temporal over 2 frames
0x2: Spatial and temporal over 4 frames
0x3: Reserved
29LCDENABLEPOLWrite 0s for future compatibility. Reads return 0.R0
28LCDENABLESIGNALWrite 0s for future compatibility. Reads return 0.R0
27PCKFREEENABLEWrite 0s for future compatibility. Reads return 0.R0
26:25TDMUNUSEDBITSState of unused bits (TDM mode only) for the primary LCD output.
wr: VFP start period of primary LCD		RW0x0
0x0: Low level (0)
0x1: High level (1)
0x2: Unchanged from previous state
0x3: Reserved
24:23TDMCYCLEFORMATCycle format (TDM mode only) for the primary LCD output
WR: VFP start period of primary LCD		RW0x0
0x0: 1 cycle for 1 pixel
0x1: 2 cycles for 1 pixel
0x2: 3 cycles for 1 pixel
0x3: 3 cycles for 2 pixels
22:21TDMPARALLELMODEOutput interface width (TDM mode only) for the primary LCD output
WR: VFP start period of primary LCD		RW0x0
0x0: 8-bit parallel output interface selected
0x1: 9-bit parallel output interface selected
0x2: 12-bit parallel output interface selected
0x3: 16-bit parallel output interface selected
20TDMENABLEEnable the multiple cycle format for the primary LCD output.
WR: VFP start period of primary LCD		RW0
0x0: TDM disabled
0x1: TDM enabled
19:17HTHold time for TV output
WR: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)		RW0x0
16GPOUT1General purpose output signal
l WR: immediate		RW0
0x0: The GPout1 is reset.
0x1: The GPout1 is set.
15GPOUT0General Purpose Output Signal
WR:immediate		RW0
0x0: The GPout0 is reset.
0x1: The GPout0 is set.
14GPIN1General purpose input signal
WR: immediately		R0
Read 0x0: The GPin1 has been reset.
Read 0x1: The GPin1 has been set.
13GPIN0General purpose input signal
WR: immediately		R0
Read 0x0: The GPin0 has been reset.
Read 0x1: The GPin0 has been set.
12OVERLAYOPTI
MIZATION		Overlay optimization for the primary LCD output
WR: VFP start period of the primary LCD		RW0
0x0: All the data for all the enabled pipelines are fetched from memory regardless of the overlay/alpha blending configuration.
0x1: The data not used by the overlay manager because of overlap between layers with no alpha blending between them must not be fetched from memory in order to optimize the bandwidth.
11STALLMODESTALL mode for the primary LCD output
wr: VFP start period of primary LCD		RW0
0x0: Normal mode selected
0x1: STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. To generate a new frame, the software must re-enable the LCD output.
10RESERVEDReservedR0
9:8TFTDATALINESNumber of lines of the primary LCD interface
WR: VFP start period of primary LCD		RW0x0
0x0: 12-bit output aligned on the LSB of the pixel data interface
0x1: 16-bit output aligned on the LSB of the pixel data interface
0x2: 18-bit output aligned on the LSB of the pixel data interface
0x3: 24-bit output aligned on the LSB of the pixel data interface
7STDITHERENABLESpatial temporal dithering enable for the primary LCD output
WR: VFP start period of primary LCD		RW0
0x0: Spatial/temporal dithering logic disabled
0x1: Spatial/temporal dithering logic enabled
6GOTVGO command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output.
WR: immediate		RW0
0x0: The hardware has finished updating the internal shadow registers of the pipeline(s) associated with the TV output using the user values. The hardware resets the bit when the update is completed.
0x1: The user has finished to program the shadow registers of the pipeline(s) associated with the TV output and the hardware can update the internal registers at the external VSYNC.
5GOLCDGO command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output.
WR: immediate		RW0
0x0: The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the LCD output using the user values. The hardware resets the bit when the update is completed.
0x1: The user has finished to program the shadow registers of the pipeline(s) associated with the LCD output and the hardware can update the internal registers at the VFP start period
4M8BMono 8-bit mode of the primary LCD wr: VFP start period of primary LCD outputRW0
0x0: Reserved
0x1: Reserved
3STNTFTLCD Display type of the primary LCD
WR: VFP start period of primary LCD output		RW0
0x0: STN display operation enabled. STN dither logic is enabled.
0x1: Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.
2MONOCOLORMonochrome/color selection for the primary LCD
WR: VFP start period of primary LCD output		RW0
0x0: Color operation enabled (STN mode only)
0x1: Monochrome operation enabled (STN mode only)
1TVENABLEEnable the TV output wr: immediate effect only occurs at the end of the current frame.RW0
0x0: TV output disabled (at the end of the current field if interlace output when the bit is reset)
0x1: TV output enabled
0LCDENABLEEnable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frameRW0
0x0: LCD output disabled (at the end of the frame when the bit is reset)
0x1: LCD output enabled
Table 13-175 DISPC_CONFIG1
Address Offset0x0000 0044
Physical Address0x5800 1044InstanceDISPC
DescriptionThe control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTVINTERLEAVEPLCDINTERLEAVEFULLRANGECOLORCONVENABLEFIDFIRSTOUTPUTMODEENABLEBT1120ENABLEBT656ENABLETVALPHABLENDERENABLELCDALPHABLENDERENABLEBUFFERFILLINGBUFFERHANDCHECKCPRBUFFERMERGETCKTVSELECTIONTCKTVENABLETCKLCDSELECTIONTCKLCDENABLEGAMATABLEENABLEACBIASGATEDVSYNCGATEDHSYNCGATEDPIXELCLOCKGATEDPIXELDATAGATEDPALETTEGAMMATABLELOADMODEPIXELGATED
BitsField NameDescriptionTypeReset
31:30RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
29:28TVINTERLEAVETV Interleave PatternRW0x0
27:26PLCDINTERLEAVEpLCD Interleave PatternRW0x0
25FULLRANGEColor Space Conversion full range setting. wr: VFP start of primary LCDRW0
0x0: Limited range selected.
0x1: Full range selected.
24COLORCONV
ENABLE		Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCDRW0
0x0: Disable Color Space Conversion RGB to YUV
0x1: Enable Color Space Conversion RGB to YUV
23FIDFIRSTSelects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCDRW0
0x0: First field is even.
0x1: Odd field is first.
22OUTPUTMODE
ENABLE		Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCDRW0
0x0: Progressive mode selected.
0x1: Interlace mode selected.
21BT1120ENABLESelects BT.1120 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCDRW0
0x0: BT.1120 is disabled
0x1: BT.1120 is enabled.
20BT656ENABLESelects BT.656 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCDRW0
0x0: BT.656 is disabled.
0x1: BT.656 is enabled.
19TVALPHABLENDER
ENABLE		Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated pipeline connected to the TV output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: EVSYNC start of primary LCDRW0
0x0: Alpha blender is disabled.
0x1: The alpha blender is enabled.
18LCDALPHABLENDER
ENABLE		Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated with the primary LCD output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: VFP start of primary LCDRW0
0x0: Alpha blender is disabled. The color key alpha blending is used.
0x1: The alpha blender is enabled.
17BUFFERFILLINGControls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediateRW0
0x0: Each DMA buffer is refilled when it reaches LOW threshold.
0x1: All DMA buffers are refilled up to high threshold when at least one of them reaches the LOW threshold. (only active DMA buffers shall be considered and when reaching the end of the frame the DMA buffer goes to empty condition so no need to fill it again).
16RESERVEDWrite 0s for future compatibility. Reads return 0.RW0
15CPRColor phase rotation control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD outputRW0
0x0: Color Phase Rotation Disabled
0x1: Color Phase Rotation Enabled
14BUFFERMERGEBuffer merge control wr: EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory or VFP When enabled, the DISPC_GLOBAL_BUFFER register is ignored. This bit must be set to zero when the write back channel is used. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero.
WR: immediate		RW0
0x0: DMA buffer merge disabled Each DMA buffer is dedicated to one pipeline.
0x1: DMA buffer merge enabled All the DMA buffers are merged into a single one to be used by the single active pipeline.
13TCKTV
SELECTION		Transparency color key selection (TV output) wr: EVSYNCRW0
0x0: Destination transparency color key selected
0x1: Source transparency color key selected
12TCKTVENABLETransparency color key enabled (TV output)
WR: EVSYNC		RW0
0x0: Disable the transparency color key for the TV output
0x1: Enable the transparency color key for the TV output
11TCKLCD
SELECTION		Transparency color key selection (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: Destination transparency color key selected
0x1: Source transparency color key selected
10TCKLCDENABLETransparency color key enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: Disable the transparency color key for the LCD
0x1: Enable the transparency color key for the LCD
9GAMATABLE
ENABLE		For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled.RW0
0x0: Gamma table LCD2 and TV are bypassed
0x1: Gamma table LCD2 and TV are enabled
8ACBIASGATEDACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: AcBias gated disabled
0x1: AcBias gated enabled
7VSYNCGATEDVSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: VSYNC gated disabled
0x1: VSYNC gated enabled
6HSYNCGATEDHSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: HSYNC gated disabled
0x1: HSYNC gated enabled
5PIXELCLOCK
GATED		Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: Pixel clock gated disabled
0x1: Pixel clock gated enabled
4PIXELDATAGATEDPixel data gated enabled (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: Pixel data gated disabled
0x1: Pixel data gated enabled
3PALETTEGAMMA
TABLE		Palette/gamma table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the graphics pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory. In case of the table is used as gamma table, it is used for the primary LCD output only.RW0
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
0x0: LUT used as palette (only if graphics format is BITMAP1, 2, 4, and 8)
0x1: LUT used as gamma table (only if graphics format is NOT BITMAP1, 2, 4, and 8 or no graphics window present)
2:1LOADMODELoading mode for the palette/gamma table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memoryRW0x0
0x0: Palette/Gamma Table and data are loaded every frame
0x1: Palette/Gamma Table to be loaded. The user sets the bit when the palette/gamma table has to be loaded. Hardware resets the bit to 0x2 when table has been loaded. (DISPC_GFX_ATTRIBUTES.ENABLE has to be set to 1).
0x2: Frame data only loaded every frame
0x3: Palette/Gamma Table and frame data loaded on first frame then switch to 0x2 (Hardware).
0PIXELGATEDPixel gated enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD outputRW0
0x0: Pixel clock always toggles (only in TFT mode)
0x1: Pixel clock only toggles when there is valid data to display. (only in TFT mode)
Table 13-176 DISPC_DEFAULT_COLOR0
Address Offset0x0000 004C
Physical Address0x5800 104CInstanceDISPC
DescriptionThe control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDEFAULTCOLOR
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0DEFAULTCOLOR24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.RW0x000000
Table 13-177 DISPC_DEFAULT_COLOR1
Address Offset0x0000 0050
Physical Address0x5800 1050InstanceDISPC
DescriptionThe control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDEFAULTCOLOR
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0DEFAULTCOLOR24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.RW0x000000
Table 13-178 DISPC_TRANS_COLOR0
Address Offset0x0000 0054
Physical Address0x5800 1054InstanceDISPC
DescriptionThe register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTRANSCOLORKEY
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0TRANSCOLORKEYTransparency color key value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24RW0x000000
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
Table 13-179 DISPC_TRANS_COLOR1
Address Offset0x0000 0058
Physical Address0x5800 1058InstanceDISPC
DescriptionThe register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTRANSCOLORKEY
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0TRANSCOLORKEYTransparency color key value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24RW0x000000
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
Table 13-180 DISPC_LINE_STATUS
Address Offset0x0000 005C
Physical Address0x5800 105CInstanceDISPC
DescriptionThe control register indicates the current primary LCD panel display line number.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDLINENUMBER
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0LINENUMBERCurrent LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented.R0x000
Table 13-181 DISPC_LINE_NUMBER
Address Offset0x0000 0060
Physical Address0x5800 1060InstanceDISPC
DescriptionThe control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLINENUMBER
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0LINENUMBERLCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs.RW0x000
Table 13-182 DISPC_TIMING_H1
Address Offset0x0000 0064
Physical Address0x5800 1064InstanceDISPC
DescriptionThe register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
HBPHFPHSW
BitsField NameDescriptionTypeReset
31:20HBPHorizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field.RW0x000
19:8HFPHorizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field.RW0x000
7:0HSWHorizontal synchronization pulse width. Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode, this field corresponds to the horizontal blankingRW0x00
Table 13-183 DISPC_TIMING_V1
Address Offset0x0000 0068
Physical Address0x5800 1068InstanceDISPC
DescriptionThe register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
VBPVFPVSW
BitsField NameDescriptionTypeReset
31:20VBPVertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame.RW0x000
19:8VFPVertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.RW0x000
7:0VSWVertical synchronization pulse width. In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode.RW0x00
Table 13-184 DISPC_POL_FREQ1
Address Offset0x0000 006C
Physical Address0x5800 106CInstanceDISPC
DescriptionThe register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDALIGNONOFFRFIEOIPCIHSIVSACBIACB
BitsField NameDescriptionTypeReset
31:19RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
18ALIGNDefines the alignment between HSYNC and VSYNC assertion.RW0
0x0: VSYNC and HSYNC are not aligned
0x1: VSYNC and HSYNC assertions are aligned.
17ONOFFHSYNC/VSYNC Pixel clock Control On/OffRW0
0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data
0x1: HSYNC and VSYNC are driven according to bit 16
Note: Control module register CTRL_CORE_SMA_SW_1[22]DSS_CH0_ON_OFF must be set to match
16RFProgram HSYNC/VSYNC Rise or FallRW0
0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit 17 set to 1)
0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit 17 set to 1)
Note: Control module register CTRL_CORE_SMA_SW_1[16]DSS_CH0_RF must be set to match
15IEOInvert output enableRW0
0x0: Ac-bias is active high (active display mode)
0x1: Ac-bias is active low (active display mode)
14IPCInvert pixel clockRW0
0x0: Data is driven on the LCD data lines on the rising-edge of the pixel clock
0x1: Data is driven on the LCD data lines on the falling-edge of the pixel clock
Note: Control module register CTRL_CORE_SMA_SW_1[19]DSS_CH0_IPC must be set to match
13IHSInvert HSYNCRW0
0x0: Line clock pin is active high and inactive low
0x1: Line clock pin is active low and inactive high
12IVSInvert VSYNCRW0
0x0: Frame clock pin is active high and inactive low
0x1: Frame clock pin is active low and inactive high
11:8ACBIAC Bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitionsRW0x0
7:0ACBAC Bias pin frequency value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.RW0x00
Table 13-185 DISPC_DIVISOR1
Address Offset0x0000 0070
Physical Address0x5800 1070InstanceDISPC
DescriptionThe register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLCDRESERVEDPCD
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:16LCDDisplay controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid.RW0x04
15:8RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
7:0PCDPixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided by DISPC_DIVISOR1.LCD value. The values 0 is invalid.RW0x01
Table 13-186 DISPC_GLOBAL_ALPHA
Address Offset0x0000 0074
Physical Address0x5800 1074InstanceDISPC
DescriptionThe register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the third LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory for each bit field depending on the association of the each pipeline with the primary LCD, secondary LCD or TV output.
TypeRW
313029282726252423222120191817161514131211109876543210
VID3GLOBALALPHAVID2GLOBALALPHAVID1GLOBALALPHAGFXGLOBALALPHA
BitsField NameDescriptionTypeReset
31:24VID3GLOBALALPHAGlobal alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.RW0xFF
23:16VID2GLOBALALPHAGlobal alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.RW0xFF
15:8VID1GLOBALALPHAGlobal alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.RW0xFF
7:0GFXGLOBALALPHAGlobal alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque.RW0xFF
Table 13-187 DISPC_SIZE_TV
Address Offset0x0000 0078
Physical Address0x5800 1078InstanceDISPC
DescriptionThe register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLPPDELTA_LPPRESERVEDPPL
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16LPPLines per panel encoded value (from 1 to 4096) to specify the number of lines per panel.RW0x000
15:14DELTA_LPPIndicates the delta size value of the odd field compared to the even fieldRW0x0
0x0: Same size
0x1: Odd size = Even size +1
0x2: Odd size = Even Size –1
13:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11:0PPLPixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display.RW0x000
Table 13-188 DISPC_SIZE_LCD1
Address Offset0x0000 007C
Physical Address0x5800 107CInstanceDISPC
DescriptionThe register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLPPDELTA_LPPRESERVEDPPL
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16LPPLines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1).RW0x000
15:14DELTA_LPPIndicates the delta size value of the odd field compared to the even fieldRW0x0
0x0: Same size
0x1: Odd size = Even size +1
0x2: Odd size = Even Size -1
13:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11:0PPLPixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.RW0x000
Table 13-189 DISPC_GFX_BA_j
Address Offset0x0000 0080 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1080 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAGraphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-190 DISPC_GFX_POSITION
Address Offset0x0000 0088
Physical Address0x5800 1088InstanceDISPC
DescriptionThe register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16POSYY position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0POSXX position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0.RW0x000
Table 13-191 DISPC_GFX_SIZE
Address Offset0x0000 008C
Physical Address0x5800 108CInstanceDISPC
DescriptionThe register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIZEYRESERVEDSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16SIZEYNumber of lines of the graphics window. Encoded value (from 1 to 4096) to specify the number of lines of the graphics window (program to value minus 1).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0SIZEXNumber of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1).RW0x000
Table 13-192 DISPC_GFX_ATTRIBUTES
Address Offset0x0000 00A0
Physical Address0x5800 10A0InstanceDISPC
DescriptionThe register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
CHANNELOUT2BURSTTYPEPREMULTIPLYALPHAZORDERZORDERENABLEANTIFLICKERRESERVEDSUBSAMPLINGPATTERNSELFREFRESHAUTOFORCE1DTILEDMODESELFREFRESHARBITRATIONROTATIONBUFPRELOADFRAMEPACKINGMODENIBBLEMODECHANNELOUTBURSTSIZEREPLICATIONENABLEFORMATENABLE
BitsField NameDescriptionTypeReset
31:30CHANNELOUT2It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero)
wr: immediate		RW0x0
0x0: Primary LCD output selected.
0x1: Secondary LCD output selected.
0x2: Third LCD output selected.
0x3: Write-back output to the memory selected.
29BURSTTYPEThe type of burst can be INCR (incremental) or BLCK (2D block).
The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only)		RW0
0x0: INC burst type is used.
0x1: 2D block burst type is used.
28PREMULTIPLYALPHAThe field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data.
Default setting is non premultiplied alpha data.		RW0
0x0: Non premultiplyalpha data color component
0x1: Premultiplyalpha data color component
27:26ZORDERZ-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value.
If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.		RW0x0
0x0: Z-order 0: layer above solid background color and below layer with higher Z-order values.
0x1: Z-order 1: layer above layer with z-order value of 0 and below layers with z-order values of 2 and 3
0x3: Z-order 3: layer above all the other layers
0x2: Z-order 2: layer above layers with z-order value of 0 and 1 and below layer with z-order value of 3
25ZORDERENABLEZ-order Enable. The bit field ZORDER is only used when the Z-order is enabled.RW0
0x0: Z-order disabled. The Z-order of the layer is 0.
0x1: Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).
24ANTIFLICKERAntiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4)RW0
0x0: Antiflicker disabled.
0x1: Antiflicker enabled.
23:21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
20:18SUBSAMPLINGPATTERNSubsampling pattern setting.RW0x0
17SELFREFRESHAUTOAutomatic self-refresh modeRW0
0x0: The transition from Selfrefresh disabled to enabled is controlled by software
0x1: The transition from Selfrefresh disabled to enabled is controlled only by hardware
16FORCE1DTILEDMODEForce TILED regions access to 1D or 2D.RW0x0
0x0: 2D accesses for tiled regions
0x1: 1D accesses for tiled regions
15SELFREFRESHEnables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field.RW0
0x0: The graphics pipeline accesses the interconnect to fetch data from the system memory.
0x1: The graphics pipeline does not need anymore to fetch data from memory. Only the graphics DMA buffer is used. It takes effect after the frame has been loaded in the DMA buffer.
14ARBITRATIONDetermines the priority of the graphics pipeline.

When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.		RW0
0x0: The graphics pipeline is one of the normal priority pipeline.
0x1: The graphics pipeline is one of the high priority pipeline.
13:12ROTATIONGraphics rotation flagRW0x0
0x0: No rotation
0x1: Rotation by 90 degrees
0x3: Rotation by 270 degrees
0x2: Rotation by 180 degrees
11BUFPRELOADGraphics preload valueRW0
0x0: Hardware prefetches pixels up to the preload value defined in the preload register
0x1: Hardware prefetches pixels up to high threshold value
10FRAMEPACKINGMODEFrame packing mode control.RW0x0
0x0: Frame Packing mode is disabled
0x1: Frame Packing mode is enabled
9NIBBLEMODEGraphics nibble mode (only for 1-, 2- and 4 bpp)RW0
NOTE: BITMAP formats and associated Nibble Mode are not supported in this family of devices.
0x0: Nibble mode is disabled
0x1: Nibble mode is enabled
8CHANNELOUTGraphics Channel Out configuration: LCD, WB or TV.
wr: immediate		RW0
0x0: LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).
0x1: TV output selected
7:6BURSTSIZEGraphics DMA burst sizeRW0x2
0x0: 2 × 128-bit bursts
0x1: 4 × 128-bit bursts
0x3: Reserved
0x2: 8 × 128-bit bursts
5REPLICATIONENABLEGraphics replication enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or 0sRW1
0x0: Disable graphics replication logic. The conversion to ARGB32-8888 is done by adding 0s for the LSBs
0x1: Enable graphics replication logic. The conversion to ARGB32-8888 is done by duplicating the MSBs for the LSBs
4:1FORMATGraphics format.
It defines the pixel format when fetching the graphics picture into memory.		RW0x0
0x6: RGB16-565
0xA: RGBx12-4444
0x7: ARGB16-1555
0xD: RGBA32-8888
0x8: xRGB24-8888 (32-bit container)
0x9: RGB24-888 (24-bit container)
0xB: RGBA12-4444
0x4: xRGB12-4444
0x5: ARGB16-4444
0xF: xRGB15-1555
0xC: ARGB32-8888
0x3: BGRA32-8888
0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)
0ENABLEGraphics enableRW0
0x0: Graphics disabled (graphics pipeline inactive and graphics window not present)
0x1: Graphics enabled (graphics pipeline active and graphics window present on the screen)
Table 13-193 DISPC_GFX_BUF_THRESHOLD
Address Offset0x0000 00A4
Physical Address0x5800 10A4InstanceDISPC
DescriptionThe register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BUFHIGHTHRESHOLDBUFLOWTHRESHOLD
BitsField NameDescriptionTypeReset
31:16BUFHIGHTHRESHOLDDMA buffer high threshold number of 128 bits defining the threshold valueRW0x04FF
15:0BUFLOWTHRESHOLDDMA buffer low threshold number of 128 bits defining the threshold value.
The value put in this register must always be greater than zero.		RW0x04F8
Table 13-194 DISPC_GFX_BUF_SIZE_STATUS
Address Offset0x0000 00A8
Physical Address0x5800 10A8InstanceDISPC
DescriptionThe register defines the Graphics buffer size
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBUFSIZE
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:0BUFSIZEDMA buffer size in number of 128 bitsR0x0500
Table 13-195 DISPC_GFX_ROW_INC
Address Offset0x0000 00AC
Physical Address0x5800 10ACInstanceDISPC
DescriptionThe register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
ROWINC
BitsField NameDescriptionTypeReset
31:0ROWINCNumber of bytes to increment at the end of the row Encoded unsigned value to specify the number of bytes to increment at the end of the row in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1- (n+1)*bpp means decrement of n pixels.RW0x0000 0001
Table 13-196 DISPC_GFX_PIXEL_INC
Address Offset0x0000 00B0
Physical Address0x5800 10B0InstanceDISPC
DescriptionThe register configures the number of bytes to increment between two pixels. For more information, see Predecimation.
Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPIXELINC
BitsField NameDescriptionTypeReset
31:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x000000
7:0PIXELINCNumber of bytes to increment between two pixels.
Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer.
The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels.		RW0x01
Table 13-197 DISPC_GFX_TABLE_BA
Address Offset0x0000 00B8
Physical Address0x5800 10B8InstanceDISPC
DescriptionThe register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory.
NOTE: CLUT and BITMAP formats, and associated palette buffer, are not supported in this family of devices.
TypeRW
313029282726252423222120191817161514131211109876543210
TABLEBA
BitsField NameDescriptionTypeReset
31:0TABLEBABase address of the palette/gamma table buffer (24-bit entries in 32-bit containers, aligned on 32-bit boundary).RW0x0000 0000
NOTE: CLUT and BITMAP formats, and associated palette buffer, are not supported in this family of devices.
Table 13-198 DISPC_VID1_BA_j
Address Offset0x0000 00BC + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 10BC + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-199 DISPC_VID1_POSITION
Address Offset0x0000 00C4
Physical Address0x5800 10C4InstanceDISPC
DescriptionThe register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16POSYY position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0POSXX position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0.RW0x000
Table 13-200 DISPC_VID1_SIZE
Address Offset0x0000 00C8
Physical Address0x5800 10C8InstanceDISPC
DescriptionThe register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD, orEVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIZEYRESERVEDSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16SIZEYNumber of lines of the video 1 Encoded value (from 1 to 4096) to specify the number of lines of the video window 1. Program to value minus 1.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0SIZEXNumber of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1.RW0x000
Table 13-201 DISPC_VID1_ATTRIBUTES
Address Offset0x0000 00CC
Physical Address0x5800 10CCInstanceDISPC
DescriptionThe register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
CHANNELOUT2BURSTTYPEPREMULTIPHYALPHAZORDERZORDERENABLESELFREFRESHARBITRATIONDOUBLESTRIDEVERTICALTAPSFORCE1DTILEDMODEBUFPRELOADRESERVEDSELFREFRESHAUTOCHANNELOUTBURSTSIZEROTATIONFULLRANGEREPLICATIONENABLECOLORCONVENABLEFRAMEPACKINGMODEHRESIZECONFRESIZEENABLEFORMATENABLE
BitsField NameDescriptionTypeReset
31:30CHANNELOUT2It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero)
wr: immediate		RW0x0
0x0: Primary LCD output selected.
0x1: Secondary LCD output selected.
0x2: Third LCD output selected.
0x3: Write-back output to the memory selected.
29BURSTTYPEThe type of burst can be INCR (incremental) or BLCK (2D block).
The 2D block is required when the TILER is targeted by the DMA engine.		RW0
0x0: INC burst type is used.
0x1: 2D block burst type is used.
28PREMULTIPHYALPHAThe field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data.
Default setting is non premultiplied alpha data.		RW0
0x0: Non premultiplyalpha data color component
0x1: Premultiplyalpha data color component
27:26ZORDERZ-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value.
If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.		RW0x0
0x0: Z-order 0: layer above solid background color and below layer with higher Z-order values.
0x1: Z-order 1: layer above layer with z-order value of 0 and below layers with z-order values of 2 and 3
0x3: Z-order 3: layer above all the other layers
0x2: Z-order 2: layer above layers with z-order value of 0 and 1 and below layer with z-order value of 3
25ZORDERENABLEZ-order Enable. The bit field ZORDER is only used when the Z-order is enabled.RW0
0x0: Z-order disabled. The Z-order of the layer is 0.
0x1: Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).
24SELFREFRESHEnables the self refresh of the video window from its own DMA buffer only.RW0
0x0: The video pipeline accesses the interconnect to fetch data from the system memory.
0x1: The video pipeline does not need anymore to fetch data from memory. Only the DMA buffer associated with the video1 is used. It takes effect after the frame has been loaded in the DMA buffer.
23ARBITRATIONDetermines the priority of the video pipeline.
The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.		RW0
0x0: The video pipeline is one of the normal priority pipeline.
0x1: The video pipeline is one of the high priority pipeline.
22DOUBLESTRIDEDetermines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride.
It is only used in case of YUV4:2:0.		RW0
0x0: The CbCr stride value is equal to the Y stride.
0x1: The CbCr stride value is double to the Y stride.
21VERTICALTAPSVideo vertical resize tap number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration.
According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap.		RW0
0x0: 3 taps are used for the vertical filtering logic. The 2 other taps are not used.
The associated bit fields for the 2 other taps coefficients do not need to be initialized.
0x1: 5 taps are used for the vertical filtering logic.
20FORCE1DTILEDMODEForce TILED regions access to 1D or 2D.RW0
0x0: 2D accesses for tiled regions
0x1: 1D accesses for tiled regions
19BUFPRELOADVideo Preload ValueRW0
0x0: Hardware prefetches pixels up to the preload value defined in the preload register
0x1: Hardware prefetches pixels up to high threshold value
18RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
17SELFREFRESHAUTOAutomatic self-refresh modeRW0
0x0: The transition from SELFREFRESH disabled to enabled is controlled by SW.
0x1: The transition from SELFREFRESH disabled to enabled is controlled only by hardware.
16CHANNELOUTVideo channel out configuration: LCD, WB or TV.
wr: immediate		RW0
0x0: LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).
0x1: TV output selected
15:14BURSTSIZEVideo DMA burst sizeRW0x2
0x0: 2x128bit bursts
0x1: 4x128bit bursts
0x3: Reserved
0x2: 8x128bit bursts
13:12ROTATIONVideo rotation flagRW0x0
0x0: No rotation
0x1: Rotation by 90 degrees
0x3: Rotation by 270 degrees
0x2: Rotation by 180 degrees
11FULLRANGEColor space conversion full range setting.RW0
0x0: Limited range selected: 16 subtracted from Y before color space conversion
0x1: Full range selected: Y is not modified before the color space conversion
10REPLICATIONENABLEReplication enableRW1
0x0: Disable Video replication logic
0x1: Enable Video replication logic
9COLORCONVENABLEEnable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format.
The bit field shall be reset when the format is not YUV.		RW0
0x0: Disable Color Space Conversion YUV to RGB
0x1: Enable Color Space Conversion YUV to RGB
8FRAMEPACKINGMODEFrame packing mode control.RW0
0x0: Frame Packing mode is disabled
0x1: Frame Packing mode is enabled
7HRESIZECONFWrite 0s for future compatibility.
Reads return 0.		R0
6:5RESIZEENABLEVideo Resize EnableRW0x0
0x0: Disable both horizontal and vertical resize processing
0x1: Enable the horizontal resize processing
0x3: Enable both horizontal and vertical resize processing
0x2: Enable the vertical resize processing
4:1FORMATVideo Format.
It defines the pixel format when fetching the video 1 picture into memory.		RW0x0
0x6: RGB16-565
0x1: RGB12x-4444
0xA: YUV2 4:2:2 co-sited
0x7: ARGB16-1555
0xD: RGBA32-8888
0x0: NV12 4:2:0 2 buffers (Y + UV)
0x2: RGBA12-4444
0x8: xRGB24-8888 (32-bit container)
0x9: RGB24-888 (24-bit container)
0xB: UYVY 4:2:2 co-sited
0x5: ARGB16-4444
0xF: xRGB15-1555
0xC: ARGB32-8888
0x4: xRGB12-4444
0x3: BGRA32-8888
0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)
0ENABLEVideo EnableRW0
0x0: Video disabled (video pipeline inactive and window not present)
0x1: Video enabled (video pipeline active and window present on the screen)
Table 13-202 DISPC_VID1_BUF_THRESHOLD
Address Offset0x0000 00D0
Physical Address0x5800 10D0InstanceDISPC
DescriptionThe register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BUFHIGHTHRESHOLDBUFLOWTHRESHOLD
BitsField NameDescriptionTypeReset
31:16BUFHIGHTHRESHOLDVideo DMA buffer high threshold number of 128 bits defining the threshold valueRW0x07FF
15:0BUFLOWTHRESHOLDDMA buffer low threshold number of 128 bits defining the threshold valueRW0x07F8
Table 13-203 DISPC_VID1_BUF_SIZE_STATUS
Address Offset0x0000 00D4
Physical Address0x5800 10D4InstanceDISPC
DescriptionThe register defines the Video buffer size for the video pipeline 1.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBUFSIZE
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:0BUFSIZEVideo 1 DMA buffer size in number of 128-bitsR0x0800
Table 13-204 DISPC_VID1_ROW_INC
Address Offset0x0000 00D8
Physical Address0x5800 10D8InstanceDISPC
DescriptionThe register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
ROWINC
BitsField NameDescriptionTypeReset
31:0ROWINCNumber of bytes to increment at the end of the row Encoded signed value (from 2311 to 231) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1)* bpp means decrement of n pixels.RW0x0000 0001
Table 13-205 DISPC_VID1_PIXEL_INC
Address Offset0x0000 00DC
Physical Address0x5800 10DCInstanceDISPC
DescriptionThe register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD orEVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPIXELINC
BitsField NameDescriptionTypeReset
31:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x000000
7:0PIXELINCNumber of bytes to increment between two pixels.
Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer.
The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels.
For YUV4:2:0, maximum supported value is 128.		RW0x01
Table 13-206 DISPC_VID1_FIR
Address Offset0x0000 00E0
Physical Address0x5800 10E0InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-207 DISPC_VID1_PICTURE_SIZE
Address Offset0x0000 00E4
Physical Address0x5800 10E4InstanceDISPC
DescriptionThe register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD, EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMEMSIZEYRESERVEDMEMSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:16MEMSIZEYNumber of lines of the video picture. Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 211.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0MEMSIZEXNumber of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 211.RW0x000
Table 13-208 DISPC_VID1_ACCU_j
Address Offset0x0000 00E8 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 10E8 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accumulator value encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accumulator value encoded value (from –1024 to 1023).RW0x000
Table 13-209 DISPC_VID1_FIR_COEF_H_i
Address Offset0x0000 00F0 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 10F0 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-210 DISPC_VID1_FIR_COEF_HV_i
Address Offset0x0000 00F4 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 10F4 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-211 DISPC_VID1_CONV_COEF0
Address Offset0x0000 0130
Physical Address0x5800 1130InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRCRRESERVEDRY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16RCRRCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RYRY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-212 DISPC_VID1_CONV_COEF1
Address Offset0x0000 0134
Physical Address0x5800 1134InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGYRESERVEDRCB
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GYGY coefficient encoded signed value (from -1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RCBRCb coefficient encoded signed value (from -1024 to 1023).RW0x000
Table 13-213 DISPC_VID1_CONV_COEF2
Address Offset0x0000 0138
Physical Address0x5800 1138InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGCBRESERVEDGCR
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GCBGCb coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0GCRGCr coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-214 DISPC_VID1_CONV_COEF3
Address Offset0x0000 013C
Physical Address0x5800 113CInstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCRRESERVEDBY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16BCRBCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0BYBY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-215 DISPC_VID1_CONV_COEF4
Address Offset0x0000 0140
Physical Address0x5800 1140InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCB
BitsField NameDescriptionTypeReset
31:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x000000
10:0BCBBCb coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-216 DISPC_VID2_BA_j
Address Offset0x0000 014C + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 114C + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). In case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-217 DISPC_VID2_POSITION
Address Offset0x0000 0154
Physical Address0x5800 1154InstanceDISPC
DescriptionThe register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16POSYY position of the video window 2 encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0POSXX position of the video window 2 encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.RW0x000
Table 13-218 DISPC_VID2_SIZE
Address Offset0x0000 0158
Physical Address0x5800 1158InstanceDISPC
DescriptionThe register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIZEYRESERVEDSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16SIZEYNumber of lines of the video 2 encoded value (from 1 to 4096) to specify the number of lines of the video window 2. Program to value minus 1.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0SIZEXNumber of pixels of the video window 2 encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1.RW0x000
Table 13-219 DISPC_VID2_ATTRIBUTES
Address Offset0x0000 015C
Physical Address0x5800 115CInstanceDISPC
DescriptionThe register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
CHANNELOUT2BURSTTYPEPREMULTIPLYALPHAZORDERZORDERENABLESELFREFRESHARBITRATIONDOUBLESTRIDEVERTICALTAPSFORCE1DTILEDMODEBUFPRELOADRESERVEDSELFREFRESHAUTOCHANNELOUTBURSTSIZEROTATIONFULLRANGEREPLICATIONENABLECOLORCONVENABLEFRAMEPACKINGMODEHRESIZECONFRESIZEENABLEFORMATENABLE
BitsField NameDescriptionTypeReset
31:30CHANNELOUT2It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (must be set to zero)
wr: immediate		RW0x0
0x0: Primary LCD output selected.
0x1: Secondary LCD output selected.
0x2: Third LCD output selected.
0x3: Write-back output to the memory selected.
29BURSTTYPEThe type of burst can be INCR (incremental) or BLCK (2D block).
The 2D block is required when the TILER is targeted by the DMA engine.		RW0
0x0: INC burst type is used.
0x1: 2D block burst type is used.
28PREMULTIPLYALPHAThe field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data.
Default setting is non premultiplied alpha data.		RW0
0x0: Non premultiplyalpha data color component
0x1: Premultiplyalpha data color component
27:26ZORDERZ-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value.
If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.		RW0x0
0x0: Z-order 0: layer above solid background color and below layer with higher Z-order values.
0x1: Z-order 1: layer above layer with z-order value of 0 and below layers with z-order values of 2 and 3
0x3: Z-order 3: layer above all the other layers
0x2: Z-order 2: layer above layers with z-order value of 0 and 1 and below layer with z-order value of 3
25ZORDERENABLEZ-order Enable. The bit field ZORDER is only used when the Z-order is enabled.RW0
0x0: Z-order disabled. The Z-order of the layer is 0.
0x1: Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).
24SELFREFRESHEnables the self refresh of the video window from its own DMA buffer only.RW0
0x0: The video pipeline accesses the interconnect to fetch data from the system memory.
0x1: The video pipeline does not need anymore to fetch data from memory. Only the DMA buffer associated with the video2 is used. It takes effect after the frame has been loaded in the DMA buffer.
23ARBITRATIONDetermines the priority of the video pipeline.
The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.		RW0
0x0: The video pipeline is one of the normal priority pipeline.
0x1: The video pipeline is one of the high priority pipeline.
22DOUBLESTRIDEDetermines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride.
It is only used in case of YUV4:2:0.		RW0
0x0: The CbCr stride value is equal to the Y stride.
0x1: The CbCr stride value is double to the Y stride.
21VERTICALTAPSVideo Vertical Resize Tap NumberRW0
0x0: 3 taps are used for the vertical filtering logic. The 2 other taps are not used.
The associated bit fields for the 2 other taps coefficients do not need to be initialized.
0x1: 5 taps are used for the vertical filtering logic.
20FORCE1DTILEDMODEForce TILED regions access to 1D or 2D.RW0
0x0: 2D accesses for tiled regions
0x1: 1D accesses for tiled regions
19BUFPRELOADVideo Preload ValueRW0
0x0: Hardware prefetches pixels up to the preload value defined in the preload register
0x1: Hardware prefetches pixels up to high threshold value
18RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
17SELFREFRESHAUTOAutomatic self-refresh modeRW0
0x0: The transition from SELFREFRESH disabled to enabled is controlled by SW.
0x1: The transition from SELFREFRESH disabled to enabled is controlled only by hardware.
16CHANNELOUTVideo Channel Out configuration: LCD, WB or TV.
wr: immediate		RW0
0x0: LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).
0x1: TV output selected
15:14BURSTSIZEVideo DMA burst sizeRW0x2
0x0: 2 × 128-bit bursts
0x1: 4 × 128-bit bursts
0x3: Reserved
0x2: 8 × 128-bit bursts
13:12ROTATIONVideo Rotation FlagRW0x0
0x0: No rotation
0x1: Rotation by 90 degrees
0x3: Rotation by 270 degrees
0x2: Rotation by 180 degrees
11FULLRANGEColor space conversion full range setting.RW0
0x0: Limited range selected: 16 subtracted from Y before color space conversion
0x1: Full range selected: Y is not modified before the color space conversion
10REPLICATIONENABLEReplication EnableRW1
0x0: Disable Video replication logic
0x1: Enable Video replication logic
9COLORCONVENABLEEnable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format.
The bit field shall be reset when the format is not YUV.		RW0
0x0: Disable color space conversion YUV to RGB
0x1: Enable color space conversion YUV to RGB
8FRAMEPACKINGMODEFrame packing mode control.RW0
0x0: Frame Packing mode is disabled
0x1: Frame Packing mode is enabled
7HRESIZECONFWrite 0s for future compatibility.
Reads return 0.		R0
6:5RESIZEENABLEVideo Resize EnableRW0x0
0x0: Disable both horizontal and vertical resize processing
0x1: Enable the horizontal resize processing
0x3: Enable both horizontal and vertical resize processing
0x2: Enable the vertical resize processing
4:1FORMATVideo Format.
It defines the pixel format when fetching the video 2 picture into memory.		RW0x0
0x6: RGB16-565
0x1: RGB12x-4444
0xA: YUV2 4:2:2 co-sited
0x7: ARGB16-1555
0xD: RGBA32-8888
0x0: NV12 4:2:0 2 buffers (Y + UV)
0x2: RGBA12-4444
0x8: xRGB24-8888 (32-bit container)
0x9: RGB24-888 (24-bit container)
0xB: UYVY 4:2:2 co-sited
0x5: ARGB16-4444
0xF: xRGB15-1555
0xC: ARGB32-8888
0x4: xRGB12-4444
0x3: BGRA32-8888
0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)
0ENABLEVidEnableRW0
0x0: Video disabled (video pipeline inactive and window not present)
0x1: Video enabled (video pipeline active and window present on the screen)
Table 13-220 DISPC_VID2_BUF_THRESHOLD
Address Offset0x0000 0160
Physical Address0x5800 1160InstanceDISPC
DescriptionThe register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BUFHIGHTHRESHOLDBUFLOWTHRESHOLD
BitsField NameDescriptionTypeReset
31:16BUFHIGHTHRESHOLDDMA buffer high threshold number of 128 bits defining the threshold valueRW0x07FF
15:0BUFLOWTHRESHOLDDMA buffer low threshold number of 128 bits defining the threshold valueRW0x07F8
Table 13-221 DISPC_VID2_BUF_SIZE_STATUS
Address Offset0x0000 0164
Physical Address0x5800 1164InstanceDISPC
DescriptionThe register defines the DMA buffer size for the video pipeline 2.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBUFSIZE
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:0BUFSIZEDMA buffer size in number of 128 bitsR0x0800
Table 13-222 DISPC_VID2_ROW_INC
Address Offset0x0000 0168
Physical Address0x5800 1168InstanceDISPC
DescriptionThe register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
ROWINC
BitsField NameDescriptionTypeReset
31:0ROWINCNumber of bytes to increment at the end of the row Encoded signed value (from 2311 to 231) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels.RW0x0000 0001
Table 13-223 DISPC_VID2_PIXEL_INC
Address Offset0x0000 016C
Physical Address0x5800 116CInstanceDISPC
DescriptionThe register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPIXELINC
BitsField NameDescriptionTypeReset
31:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x000000
7:0PIXELINCNumber of bytes to increment between two pixels.
Encoded unsigned value (from 1 to 255) to specify the number of bytes between2 pixels in the video buffer.
The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels.
For YUV4:2:0, maximum supported value is 128.		RW0x01
Table 13-224 DISPC_VID2_FIR
Address Offset0x0000 0170
Physical Address0x5800 1170InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-225 DISPC_VID2_PICTURE_SIZE
Address Offset0x0000 0174
Physical Address0x5800 1174InstanceDISPC
DescriptionThe register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMEMSIZEYRESERVEDMEMSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16MEMSIZEYNumber of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the maximum size of the unpredecimated image size in memory is still bounded 211.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0MEMSIZEXNumber of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 211.RW0x000
Table 13-226 DISPC_VID2_ACCU_j
Address Offset0x0000 0178 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1178 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accumulator value encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accumulator value encoded value (from –1024 to 1023).RW0x000
Table 13-227 DISPC_VID2_FIR_COEF_H_i
Address Offset0x0000 0180 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1180 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-228 DISPC_VID2_FIR_COEF_HV_i
Address Offset0x0000 0184 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1184 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-229 DISPC_VID2_CONV_COEF0
Address Offset0x0000 01C0
Physical Address0x5800 11C0InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRCRRESERVEDRY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16RCRRCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RYRY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-230 DISPC_VID2_CONV_COEF1
Address Offset0x0000 01C4
Physical Address0x5800 11C4InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGYRESERVEDRCB
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GYGY coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RCBRCb coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-231 DISPC_VID2_CONV_COEF2
Address Offset0x0000 01C8
Physical Address0x5800 11C8InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGCBRESERVEDGCR
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GCBGCb coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0GCRGCr coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-232 DISPC_VID2_CONV_COEF3
Address Offset0x0000 01CC
Physical Address0x5800 11CCInstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCRRESERVEDBY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16BCRBCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0BYBY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-233 DISPC_VID2_CONV_COEF4
Address Offset0x0000 01D0
Physical Address0x5800 11D0InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCB
BitsField NameDescriptionTypeReset
31:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x000000
10:0BCBBCb coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-234 DISPC_DATA1_CYCLE1
Address Offset0x0000 01D4
Physical Address0x5800 11D4InstanceDISPC
DescriptionThe control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interface.RW0x0
23:21RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interface.RW0x0
7:5RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-235 DISPC_DATA1_CYCLE2
Address Offset0x0000 01D8
Physical Address0x5800 11D8InstanceDISPC
DescriptionThe control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interface.RW0x0
23:21RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interface.RW0x0
7:5RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-236 DISPC_DATA1_CYCLE3
Address Offset0x0000 01DC
Physical Address0x5800 11DCInstanceDISPC
DescriptionThe control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interface.RW0x0
23:21RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interface.RW0x0
7:5RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-237 DISPC_VID1_FIR_COEF_V_i
Address Offset0x0000 01E0 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 11E0 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-238 DISPC_VID2_FIR_COEF_V_i
Address Offset0x0000 0200 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 1200 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-239 DISPC_CPR1_COEF_R
Address Offset0x0000 0220
Physical Address0x5800 1220InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RRRESERVEDRGRESERVEDRB
BitsField NameDescriptionTypeReset
31:22RRRR coefficient encoded signed value (from –512 to 511)RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11RGRG coefficient encoded signed value (from –512 to 511)RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0RBRB coefficient encoded signed value (from –512 to 511)RW0x000
Table 13-240 DISPC_CPR1_COEF_G
Address Offset0x0000 0224
Physical Address0x5800 1224InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
GRRESERVEDGGRESERVEDGB
BitsField NameDescriptionTypeReset
31:22GRGR coefficient encoded signed value (from –512 to 511)RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11GGGG coefficient encoded signed value (from –512 to 511)RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0GBGB coefficient encoded signed value (from –512 to 511)RW0x000
Table 13-241 DISPC_CPR1_COEF_B
Address Offset0x0000 0228
Physical Address0x5800 1228InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
BRRESERVEDBGRESERVEDBB
BitsField NameDescriptionTypeReset
31:22BRBR coefficient encoded signed value (from –512 to 511)RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11BGBG coefficient encoded signed value (from –512 to 511RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0BBBB coefficient encoded signed value (from –512 to 511)RW0x000
Table 13-242 DISPC_GFX_PRELOAD
Address Offset0x0000 022C
Physical Address0x5800 122CInstanceDISPC
DescriptionThe register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPRELOAD
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0PRELOADDMA buffer preload value number of 128-bit words defining the preload value.RW0x100
Table 13-243 DISPC_VID1_PRELOAD
Address Offset0x0000 0230
Physical Address0x5800 1230InstanceDISPC
DescriptionThe register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPRELOAD
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0PRELOADDMA buffer preload value number of 128-bit words defining the preload value.RW0x100
Table 13-244 DISPC_VID2_PRELOAD
Address Offset0x0000 0234
Physical Address0x5800 1234InstanceDISPC
DescriptionThe register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPRELOAD
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0PRELOADDMA buffer preload value Number of 128-bit words defining the preload value.RW0x100
Table 13-245 DISPC_CONTROL2
Address Offset0x0000 0238
Physical Address0x5800 1238InstanceDISPC
DescriptionThe control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when DISPC_CONTROL2.GOWB is set to 1 by software and the current WB frame is complete (that is, has no more data in the write-back pipeline).
TypeRW
313029282726252423222120191817161514131211109876543210
SPATIALTEMPORALDITHERINGFRAMESRESERVEDTDMUNUSEDBITSTDMCYCLEFORMATTDMPARALLELMODETDMENABLERESERVEDTVOVERLAYOPTIMIZATIONOVERLAYOPTIMIZATIONSTALLMODERESERVEDTFTDATALINESSTDITHERENABLEGOWBGOLCDM8BSTNTFTMONOCOLORRESERVEDLCDENABLE
BitsField NameDescriptionTypeReset
31:30SPATIALTEMPORAL
DITHERINGFRAMES		Spatial/temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD outputRW0x0
0x0: Spatial only
0x1: Spatial and temporal over 2 frames
0x2: Spatial and temporal over 4 frames
0x3: Reserved
29:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
26:25TDMUNUSED
BITS		State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD outputRW0x0
0x0: Low level (0)
0x1: High level (1)
0x2: Unchanged from previous state
0x3: Reserved
24:23TDMCYCLE
FORMAT		Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD outputRW0x0
0x0: 1 cycle for 1 pixel
0x1: 2 cycles for 1 pixel
0x2: 3 cycles for 1 pixel
0x3: 3 cycles for 2 pixels
22:21TDMPARALLEL
MODE		Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD outputRW0x0
0x0: 8-bit parallel output interface selected
0x1: 9-bit parallel output interface selected
0x2: 12-bit parallel output interface selected
0x3: 16-bit parallel output interface selected
20TDMENABLEEnable the multiple cycle format for the secondary LCD output wr: VFP start period of secondary LCD outputRW0
0x0: TDM disabled
0x1: TDM enabled
19:14RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
13TVOVERLAY
OPTIMIZATION		Overlay optimization for the TV output wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memoryRW0
0x0: All the data for all the enabled pipelines are fetched from memory regardless of the overlay/alpha blending configuration.
0x1: The data not used by the overlay manager because of overlap between layers with no alpha blending between them shall not be fetched from memory in order to optimize the bandwidth.
12OVERLAY
OPTIMIZATION		Overlay optimization for the secondary LCD output wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memoryRW0
0x0: All the data for all the enabled pipelines are fetched from memory regardless of the overlay/alpha blending configuration.
0x1: The data not used by the overlay manager because of overlap between layers with no alpha blending between them shall not be fetched from memory in order to optimize the bandwidth.
11STALLMODESTALL mode for the secondary LCD output wr: VFP start period of secondary LCD outputRW0
0x0: Normal mode selected
0x1: STALL mode selected. The Display Controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. The S/W has to re-enable the LCD output in order to generate a new frame.
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:8TFTDATALINESNumber of lines of the secondary LCD interface wr: VFP start period of secondary LCD outputRW0x0
0x0: 12-bit output aligned on the LSB of the pixel data interface
0x1: 16-bit output aligned on the LSB of the pixel data interface
0x2: 18-bit output aligned on the LSB of the pixel data interface
0x3: 24-bit output aligned on the LSB of the pixel data interface
7STDITHER
ENABLE		Spatial temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD outputRW0
0x0: Spatial/Temporal dithering logic disabled
0x1: Spatial/Temporal dithering logic enabled
6GOWBGO command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediateRW0
0x0: The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the write-back pipeline using the user values. The hardware resets the bit when the update is completed.
0x1: The user has finished to program the shadow registers of the pipeline(s) associated with the write-back pipeline and the hardware can update the internal registers immediately
5GOLCDGO command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediateRW0
0x0: The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the LCD output using the user values. The hardware resets the bit when the update is completed.
0x1: The user has finished to program the shadow registers of the pipeline(s) associated with the LCD output and the hardware can update the internal registers at the VFP start period
4M8BMono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD outputRW0
0x0: Reserved
0x1: Reserved
3STNTFTLCD Display type of the secondary LCD wr: VFP start period of secondary LCD outputRW0
0x0: Reserved
0x1: Active or TFT display operation enabled. STN Dither logic and output FIFO bypassed.
2MONOCOLORMonochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD outputRW0
0x0: Reserved
0x1: Reserved
1RESERVEDWrite 0s for future compatibility. Reads return 0.R0
0LCDENABLEEnable the secondary LCD output wr:immediateRW0
0x0: LCD output disabled (at the end of the frame when the bit is reset)
0x1: LCD output enabled
Table 13-246 DISPC_GFX_POSITION2
Address Offset0x0000 0240
Physical Address0x5800 1240InstanceDISPC
DescriptionThe register configures the position of the 2nd graphics window in FramePacking mode.

Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2[6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
26:16POSYY position of the 2nd graphics window.
Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0.		RW0x000
15:11RESERVEDWrite 0's for future compatibility.

Reads return 0		R0x00
10:0POSXX position of the 2nd graphics window.
Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0.		RW0x000
Table 13-247 DISPC_VID1_POSITION2
Address Offset0x0000 0244
Physical Address0x5800 1244InstanceDISPC
DescriptionThe register configures the position of the 2nd video window #1 in FramePacking mode.

Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2[6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
26:16POSYY position of the 2nd video window #1
Encoded value (from 0 to 2047) to specify the Y position of the video window #1 .The line at the top has the Y-position 0.		RW0x000
15:11RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
10:0POSXX position of the 2nd video window #1
Encoded value (from 0 to 2047) to specify the X position of the video window #1. The first pixel on the left of the display screen has the X-position 0.		RW0x000
Table 13-248 DISPC_VID2_POSITION2
Address Offset0x0000 0248
Physical Address0x5800 1248InstanceDISPC
DescriptionThe register configures the position of the 2nd video window #2 in FramePacking mode.

Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2[6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
26:16POSYY position of the 2nd video window #2
Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0.		RW0x000
15:11RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
10:0POSXX position of the 2nd video window #2
Encoded value (from 0 to 2047) to specify the X position of the video window #2. The first pixel on the left of the display screen has the X-position 0.		RW0x000
Table 13-249 DISPC_VID3_POSITION2
Address Offset0x0000 024C
Physical Address0x5800 124CInstanceDISPC
DescriptionThe register configures the position of the 2nd video window #3 in FramePacking mode.

Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2[6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
26:16POSYY position of the 2nd video window #2
Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0.		RW0x000
15:11RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x00
10:0POSXX position of the 2nd video window #2
Encoded value (from 0 to 2047) to specify the X position of the video window #2. The first pixel on the left of the display screen has the X-position 0.		RW0x000
Table 13-250 DISPC_VID3_ACCU_j
Address Offset0x0000 0300 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1300 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accu value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accu value Encoded value (from –1024 to 1023).RW0x000
Table 13-251 DISPC_VID3_BA_j
Address Offset0x0000 0308 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1308 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-252 DISPC_VID3_FIR_COEF_H_i
Address Offset0x0000 0310 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1310 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-253 DISPC_VID3_FIR_COEF_HV_i
Address Offset0x0000 0314 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1314 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-254 DISPC_VID3_FIR_COEF_V_i
Address Offset0x0000 0350 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 1350 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-255 DISPC_VID3_ATTRIBUTES
Address Offset0x0000 0370
Physical Address0x5800 1370InstanceDISPC
DescriptionThe register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
CHANNELOUT2BURSTTYPEPREMULTIPLYALPHAZORDERZORDERENABLESELFREFRESHARBITRATIONDOUBLESTRIDEVERTICALTAPSFORCE1DTILEDMODEBUFPRELOADRESERVEDSELFREFRESHAUTOCHANNELOUTBURSTSIZEROTATIONFULLRANGEREPLICATIONENABLECOLORCONVENABLEFRAMEPACKINGMODEHRESIZECONFRESIZEENABLEFORMATENABLE
BitsField NameDescriptionTypeReset
31:30CHANNELOUT2It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero)
wr: immediate		RW0x0
0x0: Primary LCD output selected.
0x1: Secondary LCD output selected.
0x2: Third LCD output selected.
0x3: Write-back output to the memory selected.
29BURSTTYPEThe type of burst can be INCR (incremental) or BLCK (2D block).
The 2D block is required when the TILER is targeted by the DMA engine.		RW0
0x0: INC burst type is used.
0x1: 2D block burst type is used.
28PREMULTIPLYALPHAThe field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data.
Default setting is non premultiplied alpha data.		RW0
0x0: Non premultiplyalpha data color component
0x1: Premultiplyalpha data color component
27:26ZORDERZ-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value.
If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0.		RW0x0
0x0: Z-order 0: layer above solid background color and below layer with higher Z-order values.
0x1: Z-order 1: layer above layer with z-order value of 0 and below layers with z-order values of 2 and 3
0x3: Z-order 3: layer above all the other layers
0x2: Z-order 2: layer above layers with z-order value of 0 and 1 and below layer with z-order value of 3
25ZORDERENABLEZ-order Enable. The bit field ZORDER is used only when the Z-order is enabled.RW0
0x0: Z-order disabled. The Z-order of the layer is 0.
0x1: Z-order enabled. The Z-order is defined by the bit field ZORDER (bits 26 and 27).
24SELFREFRESHEnables the self refresh of the video window from its own DMA buffer only.RW0
0x0: The video pipeline accesses the interconnect to fetch data from the system memory.
0x1: The video pipeline does not need anymore to fetch data from memory. Only the DMA buffer associated with the video3 is used. It takes effect after the frame has been loaded in the DMA buffer.
23ARBITRATIONDetermines the priority of the video pipeline.
The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.		RW0
0x0: The video pipeline is one of the normal priority pipeline.
0x1: The video pipeline is one of the high priority pipeline.
22DOUBLESTRIDEDetermines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride.
It is only used in case of YUV4:2:0.		RW0
0x0: The CbCr stride value is equal to the Y stride.
0x1: The CbCr stride value is double to the Y stride.
21VERTICALTAPSVideo vertical resize tap numberRW0
0x0: 3 taps are used for the vertical filtering logic. The 2 other taps are not used.
The associated bit fields for the 2 other taps coefficients do not need to be initialized.
0x1: 5 taps are used for the vertical filtering logic.
20FORCE1DTILEDMODEForce TILED regions access to 1D or 2D.RW0
0x0: 2D accesses for tiled regions
0x1: 1D accesses for tiled regions
19BUFPRELOADVideo Preload ValueRW0
0x0: Hardware prefetches pixels up to the preload value defined in the preload register
0x1: Hardware prefetches pixels up to high threshold value
18RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
17SELFREFRESHAUTOAutomatic self-refresh modeRW0
0x0: The transition from SELFREFRESH disabled to enabled is controlled by SW.
0x1: The transition from SELFREFRESH disabled to enabled is controlled only by hardware.
16CHANNELOUTVideo channel out configuration: LCD, WB or TV.
wr: immediate		RW0
0x0: LCD output or WB to the memory selected. bit fields 31 and 30 defines the output associated (primary, secondary or write-back).
0x1: TV output selected
15:14BURSTSIZEVideo DMA burst sizeRW0x2
0x0: 2 × 128-bit bursts
0x1: 4 × 128-bit bursts
0x3: Reserved
0x2: 8 × 128-bit bursts
13:12ROTATIONVideo rotation flagRW0x0
0x0: No rotation
0x1: Rotation by 90 degrees
0x3: Rotation by 270 degrees
0x2: Rotation by 180 degrees
11FULLRANGEColor Space Conversion full range setting.RW0
0x0: Limited range selected: 16 subtracted from Y before color space conversion
0x1: Full range selected: Y is not modified before the color space conversion
10REPLICATIONENABLEReplication enableRW1
0x0: Disable Video replication logic
0x1: Enable Video replication logic
9COLORCONVENABLEEnable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format.
The bit field shall be reset when the format is not YUV.		RW0
0x0: Disable Color Space Conversion YUV to RGB
0x1: Enable Color Space Conversion YUV to RGB
8FRAMEPACKINGMODEFrame packing mode control.RW0
0x0: Frame Packing mode is disabled
0x1: Frame Packing mode is enabled
7HRESIZECONFWrite 0s for future compatibility.
Reads return 0.		R0
6:5RESIZEENABLEVideo resize enableRW0x0
0x0: Disable both horizontal and vertical resize processing
0x1: Enable the horizontal resize processing
0x3: Enable both horizontal and vertical resize processing
0x2: Enable the vertical resize processing
4:1FORMATVideo format.
It defines the pixel format when fetching the video 3 picture into memory.		RW0x0
0x6: RGB16-565
0x1: RGB12x-4444
0xA: YUV2 4:2:2 co-sited
0x7: ARGB16-1555
0xD: RGBA32-8888
0x0: NV12 4:2:0 2 buffers (Y + UV)
0x2: RGBA12-4444
0x8: RGB24-8888 (32-bit container)
0x9: RGB24-888 (24-bit container)
0xB: UYVY 4:2:2 co-sited
0x5: ARGB16-4444
0xF: xRGB15-1555
0xC: ARGB32-8888
0x4: xRGB12-4444
0x3: BGRA32-8888
0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)
0ENABLEVideo EnableRW0
0x0: Video disabled (video pipeline inactive and window not present)
0x1: Video enabled (video pipeline active and window present on the screen)
Table 13-256 DISPC_VID3_CONV_COEF0
Address Offset0x0000 0374
Physical Address0x5800 1374InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRCRRESERVEDRY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16RCRRCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RYRY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-257 DISPC_VID3_CONV_COEF1
Address Offset0x0000 0378
Physical Address0x5800 1378InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGYRESERVEDRCB
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GYGY coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0RCBRCb coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-258 DISPC_VID3_CONV_COEF2
Address Offset0x0000 037C
Physical Address0x5800 137CInstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGCBRESERVEDGCR
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16GCBGCb coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0GCRGCr coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-259 DISPC_VID3_CONV_COEF3
Address Offset0x0000 0380
Physical Address0x5800 1380InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCRRESERVEDBY
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16BCRBCr coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0BYBY coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-260 DISPC_VID3_CONV_COEF4
Address Offset0x0000 0384
Physical Address0x5800 1384InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBCB
BitsField NameDescriptionTypeReset
31:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x000000
10:0BCBBCb coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-261 DISPC_VID3_BUF_SIZE_STATUS
Address Offset0x0000 0388
Physical Address0x5800 1388InstanceDISPC
DescriptionThe register defines the DMA buffer size for the video pipeline 3.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBUFSIZE
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:0BUFSIZEDMA buffer Size in number of 128 bits.R0x0800
Table 13-262 DISPC_VID3_BUF_THRESHOLD
Address Offset0x0000 038C
Physical Address0x5800 138CInstanceDISPC
DescriptionThe register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BUFHIGHTHRESHOLDBUFLOWTHRESHOLD
BitsField NameDescriptionTypeReset
31:16BUFHIGHTHRESHOLDDMA buffer high threshold number of 128 bits defining the threshold valueRW0x07FF
15:0BUFLOWTHRESHOLDDMA buffer low threshold number of 128 bits defining the threshold valueRW0x07F8
Table 13-263 DISPC_VID3_FIR
Address Offset0x0000 0390
Physical Address0x5800 1390InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-264 DISPC_VID3_PICTURE_SIZE
Address Offset0x0000 0394
Physical Address0x5800 1394InstanceDISPC
DescriptionThe register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMEMSIZEYRESERVEDMEMSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:16MEMSIZEYNumber of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 211.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0MEMSIZEXNumber of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 211.RW0x000
Table 13-265 DISPC_VID3_PIXEL_INC
Address Offset0x0000 0398
Physical Address0x5800 1398InstanceDISPC
DescriptionThe register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPIXELINC
BitsField NameDescriptionTypeReset
31:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x000000
7:0PIXELINCNumber of bytes to increment between two pixels.
Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer.
The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels.
For YUV4:2:0, maximum supported value is 128.		RW0x01
Table 13-266 DISPC_VID3_POSITION
Address Offset0x0000 039C
Physical Address0x5800 139CInstanceDISPC
DescriptionThe register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPOSYRESERVEDPOSX
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16POSYY position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0POSXX position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0.RW0x000
Table 13-267 DISPC_VID3_PRELOAD
Address Offset0x0000 03A0
Physical Address0x5800 13A0InstanceDISPC
DescriptionThe register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPRELOAD
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:0PRELOADDMA buffer preload value Number of 128-bit words defining the preload value.RW0x100
Table 13-268 DISPC_VID3_ROW_INC
Address Offset0x0000 03A4
Physical Address0x5800 13A4InstanceDISPC
DescriptionThe register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
ROWINC
BitsField NameDescriptionTypeReset
31:0ROWINCNumber of bytes to increment at the end of the row Encoded signed value (from 2311 to 231) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels.RW0x0000 0001
Table 13-269 DISPC_VID3_SIZE
Address Offset0x0000 03A8
Physical Address0x5800 13A8InstanceDISPC
DescriptionThe register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIZEYRESERVEDSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:16SIZEYNumber of lines of the video 3 Encoded value (from 1 to 4096) to specify the number of lines of the video window 3. Program to value minus 1.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
10:0SIZEXNumber of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1.RW0x000
Table 13-270 DISPC_DEFAULT_COLOR2
Address Offset0x0000 03AC
Physical Address0x5800 13ACInstanceDISPC
DescriptionThe control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDEFAULTCOLOR
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0DEFAULTCOLOR24-bit RGB color value to specify the default solid color to display when there is no data from the overlays.RW0x000000
Table 13-271 DISPC_TRANS_COLOR2
Address Offset0x0000 03B0
Physical Address0x5800 13B0InstanceDISPC
DescriptionThe register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTRANSCOLORKEY
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:0TRANSCOLORKEYTransparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24RW0x000000
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
Table 13-272 DISPC_CPR2_COEF_B
Address Offset0x0000 03B4
Physical Address0x5800 13B4InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
BRRESERVEDBGRESERVEDBB
BitsField NameDescriptionTypeReset
31:22BRBR coefficient encoded signed value (from –512 to 511).RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11BGBG coefficient encoded signed value (from –512 to 511).RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0BBBB coefficient encoded signed value (from –512 to 511).RW0x000
Table 13-273 DISPC_CPR2_COEF_G
Address Offset0x0000 03B8
Physical Address0x5800 13B8InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
GRRESERVEDGGRESERVEDGB
BitsField NameDescriptionTypeReset
31:22GRGR coefficient encoded signed value (from –512 to 511).RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11GGGG coefficient encoded signed value (from –512 to 511).RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0GBGB coefficient encoded signed value (from –512 to 511).RW0x000
Table 13-274 DISPC_CPR2_COEF_R
Address Offset0x0000 03BC
Physical Address0x5800 13BCInstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RRRESERVEDRGRESERVEDRB
BitsField NameDescriptionTypeReset
31:22RRRR coefficient encoded signed value (from –512 to 511).RW0x000
21RESERVEDWrite 0s for future compatibility. Reads return 0.R0
20:11RGRG coefficient encoded signed value (from –512 to 511).RW0x000
10RESERVEDWrite 0s for future compatibility. Reads return 0.R0
9:0RBRB coefficient encoded signed value (from –512 to 511).RW0x000
Table 13-275 DISPC_DATA2_CYCLE1
Address Offset0x0000 03C0
Physical Address0x5800 13C0InstanceDISPC
DescriptionThe control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interfaceRW0x0
23:21RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interfaceRW0x0
7:5RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-276 DISPC_DATA2_CYCLE2
Address Offset0x0000 03C4
Physical Address0x5800 13C4InstanceDISPC
DescriptionThe control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interfaceRW0x0
23:21RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interfaceRW0x0
7:5RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-277 DISPC_DATA2_CYCLE3
Address Offset0x0000 03C8
Physical Address0x5800 13C8InstanceDISPC
DescriptionThe control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
27:24BITALIGNMENTPIXEL2Bit alignment. Alignment of the bits from pixel 2 on the output interfaceRW0x0
23:21RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
20:16NBBITSPIXEL2Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
15:12RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
11:8BITALIGNMENTPIXEL1Bit alignment. Alignment of the bits from pixel 1 on the output interfaceRW0x0
7:5RESERVEDWrite 0s for future compatibility Reads return 0.R0x0
4:0NBBITSPIXEL1Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.RW0x00
Table 13-278 DISPC_SIZE_LCD2
Address Offset0x0000 03CC
Physical Address0x5800 13CCInstanceDISPC
DescriptionThe register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLPPDELTA_LPPRESERVEDPPL
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16LPPLines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1).RW0x000
15:14DELTA_LPPIndicates the delta size value of the odd field compared to the even fieldRW0x0
0x0: same size
0x1: odd size = even size +1
0x2: Odd size = even size –1
13:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11:0PPLPixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid.RW0x000
Table 13-279 DISPC_TIMING_H2
Address Offset0x0000 0400
Physical Address0x5800 1400InstanceDISPC
DescriptionThe register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
HBPHFPHSW
BitsField NameDescriptionTypeReset
31:20HBPHorizontal back porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1).RW0x000
19:8HFPHorizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1).RW0x000
7:0HSWHorizontal synchronization pulse width. Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1).RW0x00
Table 13-280 DISPC_TIMING_V2
Address Offset0x0000 0404
Physical Address0x5800 1404InstanceDISPC
DescriptionThe register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
VBPVFPVSW
BitsField NameDescriptionTypeReset
31:20VBPVertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display.RW0x000
19:8VFPVertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame.RW0x000
7:0VSWVertical synchronization pulse width. In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode.RW0x00
Table 13-281 DISPC_POL_FREQ2
Address Offset0x0000 0408
Physical Address0x5800 1408InstanceDISPC
DescriptionThe register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDALIGNONOFFRFIEOIPCIHSIVSACBIACB
BitsField NameDescriptionTypeReset
31:19RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
18ALIGNDefines the alignment between HSYNC and VSYNC assertion.RW0
0x0: VSYNC and HSYNC are not aligned.
0x1: VSYNC and HSYNC assertions are aligned.
17ONOFFHSYNC/VSYNC Pixel clock Control On/OffRW0
0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data.
0x1: HSYNC and VSYNC are driven according to bit 16.
Note: Control module register CTRL_CORE_SMA_SW_1[23]DSS_CH1_ON_OFF must be set to match
16RFProgram HSYNC/VSYNC Rise or FallRW0
0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit 17 set to 1).
0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit 17 set to 1).
Note: Control module register CTRL_CORE_SMA_SW_1[17]DSS_CH1_RF must be set to match
15IEOInvert output enableRW0
0x0: Ac-bias is active high (active display mode).
0x1: Ac-bias is active low (active display mode).
14IPCInvert pixel clockRW0
0x0: Data is driven on the LCD data lines on the rising-edge of the pixel clock.
0x1: Data is driven on the LCD data lines on the falling-edge of the pixel clock.
Note: Control module register CTRL_CORE_SMA_SW_1[20]DSS_CH1_IPC must be set to match
13IHSInvert HSYNCRW0
0x0: Line clock pin is active high and inactive low.
0x1: Line clock pin is active low and inactive high.
12IVSInvert VSYNCRW0
0x0: Frame clock pin is active high and inactive low.
0x1: Frame clock pin is active low and inactive high.
11:8ACBIAC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitionsRW0x0
7:0ACBAC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display.RW0x00
Table 13-282 DISPC_DIVISOR2
Address Offset0x0000 040C
Physical Address0x5800 140CInstanceDISPC
DescriptionThe register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLCDRESERVEDPCD
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:16LCDDisplay controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid.RW0x04
15:8RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
7:0PCDPixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided by DISPC_DIVISOR2.LCD value. The value 0 is invalid.RW0x01
Table 13-283 DISPC_WB_ACCU_j
Address Offset0x0000 0500 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1500 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accumulator value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accumulator value encoded value (from –1024 to 1023).RW0x000
Table 13-284 DISPC_WB_BA_j
Address Offset0x0000 0508 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1508 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAWrite-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-285 DISPC_WB_FIR_COEF_H_i
Address Offset0x0000 0510 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1510 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-286 DISPC_WB_FIR_COEF_HV_i
Address Offset0x0000 0514 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1514 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-287 DISPC_WB_FIR_COEF_V_i
Address Offset0x0000 0550 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 1550 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-288 DISPC_WB_ATTRIBUTES
Address Offset0x0000 0570
Physical Address0x5800 1570InstanceDISPC
DescriptionThe register configures the attributes of the viwrite back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
IDLENUMBERIDLESIZECAPTUREMODEARBITRATIONDOUBLESTRIDEVERTICALTAPSFORCE1DTILEDMODEWRITEBACKMODECHANNELINBURSTSIZERESERVEDFULLRANGETRUNCATIONENABLECOLORCONVENABLEBURSTTYPEALPHAENABLERESIZEENABLEFORMATENABLE
BitsField NameDescriptionTypeReset
31:28IDLENUMBERDetermines the number of idles between requests on the L3_MAIN interconnect.
It is only used when the write-back pipeline does data transfer from memory to memory.
When the output of an overlay is stored in memory through the write-back pipeline in capture mode, the bit field IDLENUMBER is ignored since a timing generator is used to time the transfer.
The number of IDLE cycles is IDLENUMBER (from 0 to 15) if IDLESIZE = 0.
The number of IDLE cycles is IDLENUMBERx8 (from 0 to 120) if IDLESIZE = 1 and BURSTSIZE = 2.
The number of IDLE cycles is IDLENUMBERx4 (from 0 to 60) if IDLESIZE = 1 and BURSTSIZE = 1.
The number of IDLE cycles is IDLENUMBERx2 (from 0 to 30) if IDLESIZE = 1 and BURSTSIZE = 0.		RW0x0
27IDLESIZEDetermines if the IDLENUMBER corresponds to a number of bursts or singles.RW0
0x0: The number of idles between requests is defined by IDLENUMBER as number of cycles.
0x1: The number of idles between requests is defined by IDLENUMBER multiplied by burst size as number of cycles.
26:24CAPTUREMODEDefines the frame rate capture.RW0x0
0x6: Only one out of six frames is captured. The first one is captured then the second one is skipped and so on.
0x1: Only one frame is captured.
0x7: Only one out of seven frames is captured. The first one is captured then the second one is skipped and so on.
0x0: All frames are captures until the write-back channel is disabled or there is no more data generated by the overlay or the pipeline attached to the write-back channel.
0x2: Only one out of two frames is captured. The first one is captured, and then the second one is skipped, and so on.
0x4: Only one out of four frames is captured. The first one is captured, and then the second one is skipped, and so on.
0x5: Only one out of five frames is captured. The first one is captured, and then the second one is skipped, and so on.
0x3: Only one out of three frames is captured. The first one is captured, and then the second one is skipped, and so on.
23ARBITRATIONDetermines the priority of the write-back pipeline.
The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them.		RW0
0x0: The write-back pipeline is one of the normal priority pipeline.
0x1: The write-back pipeline is one of the high priority pipeline.
22DOUBLESTRIDEDetermines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride.
It is only used in case of YUV4:2:0.		RW0
0x0: The CbCr stride value is equal to the Y stride.
0x1: The CbCr stride value is double to the Y stride.
21VERTICALTAPSVideo Vertical Resize Tap NumberRW0
0x0: 3 taps are used for the vertical filtering logic. The 2 other taps are not used.
0x1: 5 taps are used for the vertical filtering logic.
20FORCE1DTILEDMODEForce TILED regions access to 1D or 2D.RW0x0
0x0: 2D accesses for tiled regions
0x1: 1D accesses for tiled regions
19WRITEBACKMODEWhen connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel.
0x0: Capture mode (default mode)
0x1: Memory-to-memory mode		RW0x0
18:16CHANNELINVideo Channel In configuration
WR: immediate		RW0x0
0x6: Video3 pipeline output
0x1: Secondary LCD output
0x0: Primary LCD overlay output
0x2: TV overlay output
0x4: Video1 pipeline output
0x5: Video2 pipeline output
0x3: Graphics pipeline output
0x7: Third LCD output
15:14BURSTSIZEWrite-back DMA Burst SizeRW0x2
0x0: 2 × 128-bit bursts
0x1: 4 × 128-bit bursts
0x3: Reserved
0x2: 8 × 128-bit bursts
13:12RESERVEDReservedRW0x0
11FULLRANGEColor Space Conversion full range setting.RW0
0x0: Limited range selected: 16 subtracted from Y before color space conversion
0x1: Full range selected: Y is not modified before the color space conversion
10TRUNCATIONENABLEIt applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored.RW0
0x0: Disable truncation logic
0x1: Enable truncation logic from ARGB32 to the pixel format defined in the field FORMAT.
9COLORCONVENABLEEnable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format.
The bit field shall be reset when the format is not YUV.		RW0
0x0: Disable Color Space Conversion RGB to YUV
0x1: Enable Color Space Conversion RGB to YUV
8BURSTTYPEThe type of burst can be INCR (incremental) or BLCK (2D block).
The 2D block is required when the TILER is targeted by the DMA engine.		RW0
0x0: INC burst type is used.
0x1: 2D block burst type is used.
7ALPHAENABLEPremultiplied alpha enable
Read 0x1: Enabled
Read 0x0: Disabled.
This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe.
When the WB is configured to copy back one of the output channels (output of overlay), the following configurations are available:
0x1: The WB pipe copies back to memory the premultiplied alpha calculated through the overlay.
0x0: The alpha value is not written back.		RW0
6:5RESIZEENABLEResize EnableRW0x0
0x0: Disable the resize processing
0x1: Enable the horizontal resize processing
0x3: Enable both horizontal and vertical resize processing
0x2: Enable the vertical resize processing
4:1FORMATWrite-back format.
It defines the pixel format when storing the write-back picture into memory.		RW0x0
0x6: RGB16-565
0x1: RGB12x-4444
0xA: YUV2 4:2:2 co-sited
0x7: ARGB16-1555
0xD: RGBA32-8888
0x0: NV12 4:2:0 2 buffers (Y + UV)
0x2: RGBA12-4444
0x8: xRGB24-8888 (32-bit container)
0x9: RGB24-888 (24-bit container)
0xB: UYVY 4:2:2 co-sited
0x5: ARGB16-4444
0xF: xRGB15-1555
0xC: ARGB32-8888
0x4: xRGB12-4444
0x3: BGRA32-8888
0xE: RGBx24-8888 (24-bit RGB aligned on MSB of the 32-bit container)
0ENABLEWrite-back enable.
wr: immediate		RW0
0x0: Write-back disabled
0x1: Write-back enabled
Table 13-289 DISPC_WB_CONV_COEF0
Address Offset0x0000 0574
Physical Address0x5800 1574InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24). Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDYGRESERVEDYR
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16YGYG coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0YRYR coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-290 DISPC_WB_CONV_COEF1
Address Offset0x0000 0578
Physical Address0x5800 1578InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCRRRESERVEDYB
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16CRRCrR coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0YBYB coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-291 DISPC_WB_CONV_COEF2
Address Offset0x0000 057C
Physical Address0x5800 157CInstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCRBRESERVEDCRG
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16CRBCrB coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0CRGCrG coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-292 DISPC_WB_CONV_COEF3
Address Offset0x0000 0580
Physical Address0x5800 1580InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCBGRESERVEDCBR
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16CBGCbG coefficient encoded signed value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0CBRCbR coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-293 DISPC_WB_CONV_COEF4
Address Offset0x0000 0584
Physical Address0x5800 1584InstanceDISPC
DescriptionThe register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCBB
BitsField NameDescriptionTypeReset
31:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x000000
10:0CBBCbB coefficient encoded signed value (from –1024 to 1023).RW0x000
Table 13-294 DISPC_WB_BUF_SIZE_STATUS
Address Offset0x0000 0588
Physical Address0x5800 1588InstanceDISPC
DescriptionThe register defines the DMA buffer size for the write back pipeline.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBUFSIZE
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:0BUFSIZEDMA buffer Size in number of 128 bitsR0x0800
Table 13-295 DISPC_WB_BUF_THRESHOLD
Address Offset0x0000 058C
Physical Address0x5800 158CInstanceDISPC
DescriptionThe register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
BUFHIGHTHRESHOLDBUFLOWTHRESHOLD
BitsField NameDescriptionTypeReset
31:16BUFHIGHTHRESHOLDDMA buffer high threshold number of 128 bits defining the threshold valueRW0x07FF
15:0BUFLOWTHRESHOLDDMA buffer low threshold number of 128 bits defining the threshold valueRW0x07F8
Table 13-296 DISPC_WB_FIR
Address Offset0x0000 0590
Physical Address0x5800 1590InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-297 DISPC_WB_PICTURE_SIZE
Address Offset0x0000 0594
Physical Address0x5800 1594InstanceDISPC
DescriptionThe register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMEMSIZEYRESERVEDMEMSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16MEMSIZEYNumber of lines of the wb picture in memory. Encoded value (from 1 to 4096) to specify the number of lines of the picture in memory (program to value minus 1).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0MEMSIZEXNumber of pixels of the wb picture in memory. Encoded value (from 1 to 2048) to specify the number of pixels of the picture in memory (program to value minus 1).RW0x000
Table 13-298 DISPC_WB_PIXEL_INC
Address Offset0x0000 0598
Physical Address0x5800 1598InstanceDISPC
DescriptionThe register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPIXELINC
BitsField NameDescriptionTypeReset
31:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x000000
7:0PIXELINCValues other than 1 are invalidRW0x01
Table 13-299 DISPC_WB_ROW_INC
Address Offset0x0000 05A4
Physical Address0x5800 15A4InstanceDISPC
DescriptionThe register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
ROWINC
BitsField NameDescriptionTypeReset
31:0ROWINCNumber of bytes to increment at the end of the row Encoded signed value (from 2311 to 231) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n *bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels.RW0x0000 0001
Table 13-300 DISPC_WB_SIZE
Address Offset0x0000 05A8
Physical Address0x5800 15A8InstanceDISPC
DescriptionThe register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, the size of the frame is defined in the DISPC_SIZE_LCD1, DISPC_SIZE_LCD2, and DISPC_SIZE_TV respectively. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIZEYRESERVEDSIZEX
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
27:16SIZEYNumber of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline. Program to value minus 1.RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0SIZEXNumber of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture from overlay or pipeline. Program to value minus 1.RW0x000
Table 13-301 DISPC_VID1_BA_UV_j
Address Offset0x0000 0600 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1600 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-302 DISPC_VID2_BA_UV_j
Address Offset0x0000 0608 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1608 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-303 DISPC_VID3_BA_UV_j
Address Offset0x0000 0610 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1610 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-304 DISPC_WB_BA_UV_j
Address Offset0x0000 0618 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1618 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
BA
BitsField NameDescriptionTypeReset
31:0BAVideo base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM.RW0x0000 0000
Table 13-305 DISPC_CONFIG2
Address Offset0x0000 0620
Physical Address0x5800 1620InstanceDISPC
DescriptionThe control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or VFP start period of the third LCD or EVSYNC
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSLCDINTERLEAVEFULLRANGECOLORCONVENABLEFIDFIRSTOUTPUTMODEENABLEBT1120ENABLEBT656ENABLERESERVEDBUFFERHANDCHECKCPRRESERVEDTCKLCDSELECTIONTCKLCDENABLERESERVEDACBIASGATEDVSYNCGATEDHSYNCGATEDPIXELCLOCKGATEDPIXELDATAGATEDRESERVEDPIXELGATED
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
27:26SLCDINTERLEAVEsLCD Interleave PatternRW0x0
25FULLRANGEColor space conversion full range setting.RW0
0x0: Limited range selected.
0x1: Full range selected.
24COLORCONV
ENABLE		Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1.RW0
0x0: Disable color space conversion RGB to YUV
0x1: Enable color space conversion RGB to YUV
23FIDFIRSTSelects the first field to output in case of interlace mode. In case of progressive mode, the value is not used.RW0
0x0: First field is even.
0x1: Odd field is first.
22OUTPUTMODE
ENABLE		Selects between progressive and interlace mode for the secondary LCD output.RW0
0x0: Progressive mode selected.
0x1: Interlace mode selected.
21BT1120ENABLESelects BT.1120 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCDRW0
0x0: BT.1120 is disabled
0x1: BT.1120 is enabled.
20BT656ENABLESelects BT.656 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCDRW0
0x0: BT.656 is disabled.
0x1: BT.656 is enabled.
19:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
15CPRColor Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD outputRW0
0x0: Color phase rotation disabled
0x1: Color phase rotation enabled
14:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
11TCKLCD
SELECTION		Transparency color key selection (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: Destination transparency color key selected
0x1: Source transparency color key selected
10TCKLCDENABLETransparency color key enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: Disable the transparency color key for the LCD
0x1: Enable the transparency color key for the LCD
9RESERVEDWrite 0s for future compatibility. Reads return 0.R0
8ACBIASGATEDACBias gated enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: AcBias gated disabled
0x1: AcBias gated enabled
7VSYNCGATEDVSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: VSYNC gated disabled
0x1: VSYNC gated enabled
6HSYNCGATEDHSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: HSYNC gated disabled
0x1: HSYNC gated enabled
5PIXELCLOCK
GATED		Pixel clock gated enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: Pixel clock gated disabled
0x1: Pixel clock gated enabled
4PIXELDATA
GATED		Pixel data gated enabled (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: Pixel data gated disabled
0x1: Pixel data gated enabled
3:1RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
0PIXELGATEDPixel gated enable (only for active matrix) (secondary LCD output) wr: VFP start period of secondary LCD outputRW0
0x0: Pixel clock always toggles (only in active matrix mode).
0x1: Pixel clock only toggles when there is valid data to display (only in active matrix mode).
Table 13-306 DISPC_VID1_ATTRIBUTES2
Address Offset0x0000 0624
Physical Address0x5800 1624InstanceDISPC
DescriptionThe register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSUBSAMPLINGPATTERNYUVCHROMARESAMPLINGRESERVEDVC1_RANGE_CBCRVC1_RANGE_YVC1ENABLE
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:9SUBSAMPLINGPATTERNSubsampling pattern setting.RW0x0
8YUVCHROMARE
SAMPLING		The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.RW0
0x0: When input is 4:2:2, the missing chrominance samples are calculated by averaging the adjacent samples if DISPC_VID1_ATTRIBUTES. ROTATION=0 only. Other rotation configurations are not supported.
0x1: For 4:2:2 (or 4:2:0), the missing chrominance samples are calculated by filtering the adjacent samples (5-tap polyphase filter). See Figure 13-49, Configuration 2: Video Pipeline. All rotation configurations are supported.
7RESERVEDWrite 0s for future compatibility. Reads return 0.R0
6:4VC1_RANGE_
CBCR		Defines the VC-1 range value for the CbCr component from 0 to 7.RW0x0
3:1VC1_RANGE_YDefines the VC-1 range value for the Y component from 0 to 7.RW0x0
0VC1ENABLEEnable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.RW0
0x0: VC-1 range mapping disabled
0x1: VC-1 range mapping enabled
Table 13-307 DISPC_VID2_ATTRIBUTES2
Address Offset0x0000 0628
Physical Address0x5800 1628InstanceDISPC
DescriptionThe register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSUBSAMPLINGPATTERNYUVCHROMARESAMPLINGRESERVEDVC1_RANGE_CBCRVC1_RANGE_YVC1ENABLE
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:9SUBSAMPLINGPATTERNSubsampling pattern setting.RW0x0
8YUVCHROMARE
SAMPLING		The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.RW0
0x0: When input is in 4:2:2, the missing chrominance samples are calculated by averaging the adjacent samples if DISPC_VID1_ATTRIBUTES. ROTATION=0 only. Other rotation configurations are not supported.
0x1: For 4:2:2 (or 4:2:0), the missing chrominance samples are calculated by filtering the adjacent samples (5-tap polyphase filter). See Figure 13-49, Configuration 2: Video Pipeline. All rotation configurations are supported.
7RESERVEDWrite 0s for future compatibility. Reads return 0.R0
6:4VC1_RANGE_
CBCR		Defines the VC-1 range value for the CbCr component from 0 to 7.RW0x0
3:1VC1_RANGE_YDefines the VC-1 range value for the Y component from 0 to 7.RW0x0
0VC1ENABLEEnable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.RW0
0x0: VC-1 range mapping disabled
0x1: VC-1 range mapping enabled
Table 13-308 DISPC_VID3_ATTRIBUTES2
Address Offset0x0000 062C
Physical Address0x5800 162CInstanceDISPC
DescriptionThe register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSUBSAMPLINGPATTERNYUVCHROMARESAMPLINGRESERVEDVC1_RANGE_CBCRVC1_RANGE_YVC1ENABLE
BitsField NameDescriptionTypeReset
31:12RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00000
11:9SUBSAMPLINGPATTERNSubsampling pattern setting.RW0x0
8YUVCHROMARE
SAMPLING		The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe.RW0
0x0: When input is in 4:2:2, the missing chrominance samples are calculated by averaging the adjacent samples if DISPC_VID1_ATTRIBUTES. ROTATION=0 only. Other rotation configurations are not supported.
0x1: For 4:2:2 (or 4:2:0), the missing chrominance samples are calculated by filtering the adjacent samples (5-tap polyphase filter). See Figure 13-49, Configuration 2: Video Pipeline. All rotation configurations are supported.
7RESERVEDWrite 0s for future compatibility. Reads return 0.R0
6:4VC1_RANGE_
CBCR		Defines the VC-1 range value for the CbCr component from 0 to 7.RW0x0
3:1VC1_RANGE_YDefines the VC-1 range value for the Y component from 0 to 7.RW0x0
0VC1ENABLEEnable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats.RW0
0x0: VC-1 range mapping disabled
0x1: VC-1 range mapping enabled
Table 13-309 DISPC_GAMMA_TABLE0
Address Offset0x0000 0630
Physical Address0x5800 1630InstanceDISPC
DescriptionThe register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output.
NOTE: CLUT and BITMAP formats are not supported in this family of devices.
TypeW
313029282726252423222120191817161514131211109876543210
INDEXVALUE_RVALUE_GVALUE_B
BitsField NameDescriptionTypeReset
31:24INDEXDefines the location in the table where the bit field VALUE is stored.W0x00
23:16VALUE_R8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
15:8VALUE_G8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
7:0VALUE_B8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
Table 13-310 DISPC_GAMMA_TABLE1
Address Offset0x0000 0634
Physical Address0x5800 1634InstanceDISPC
DescriptionThe register configures the gamma table on the secondary LCD output.
TypeW
313029282726252423222120191817161514131211109876543210
INDEXVALUE_RVALUE_GVALUE_B
BitsField NameDescriptionTypeReset
31:24INDEXDefines the location in the table where the bit field VALUE is stored.W0x00
23:16VALUE_R8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
15:8VALUE_G8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
7:0VALUE_B8-bit value used to defined the value to store at the location in the table defined by the bit field INDEXW0x00
Table 13-311 DISPC_GAMMA_TABLE2
Address Offset0x0000 0638
Physical Address0x5800 1638InstanceDISPC
DescriptionThe register configures the gamma table on the TV output.
TypeW
313029282726252423222120191817161514131211109876543210
INDEXRESERVEDVALUE_RVALUE_GVALUE_B
BitsField NameDescriptionTypeReset
31INDEXSetting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory.W0
30RESERVEDW0
29:20VALUE_R10-bit color component value to store in the tableW0x000
19:10VALUE_G10-bit color component value to store in the tableW0x000
9:0VALUE_B10-bit color component value to store in the tableW0x000
Table 13-312 DISPC_VID1_FIR2
Address Offset0x0000 063C
Physical Address0x5800 163CInstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-313 DISPC_VID1_ACCU2_j
Address Offset0x0000 0640 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1640 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accu value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accu value Encoded value (from –1024 to 1023).RW0x000
Table 13-314 DISPC_VID1_FIR_COEF_H2_i
Address Offset0x0000 0648 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1648 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-315 DISPC_VID1_FIR_COEF_HV2_i
Address Offset0x0000 064C + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 164C + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-316 DISPC_VID1_FIR_COEF_V2_i
Address Offset0x0000 0688 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 1688 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-317 DISPC_VID2_FIR2
Address Offset0x0000 06A8
Physical Address0x5800 16A8InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-318 DISPC_VID2_ACCU2_j
Address Offset0x0000 06AC + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 16AC + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accu value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accu value Encoded value (from –1024 to 1023).RW0x000
Table 13-319 DISPC_VID2_FIR_COEF_H2_i
Address Offset0x0000 06B4 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 16B4 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-320 DISPC_VID2_FIR_COEF_HV2_i
Address Offset0x0000 06B8 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 16B8 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-321 DISPC_VID2_FIR_COEF_V2_i
Address Offset0x0000 06F4 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 16F4 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-322 DISPC_VID3_FIR2
Address Offset0x0000 0724
Physical Address0x5800 1724InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-323 DISPC_VID3_ACCU2_j
Address Offset0x0000 0728 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1728 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accu value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accu value Encoded value (from –1024 to 1023).RW0x000
Table 13-324 DISPC_VID3_FIR_COEF_H2_i
Address Offset0x0000 0730 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1730 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-325 DISPC_VID3_FIR_COEF_HV2_i
Address Offset0x0000 0734 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 1734 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-326 DISPC_VID3_FIR_COEF_V2_i
Address Offset0x0000 0770 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 1770 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-327 DISPC_WB_FIR2
Address Offset0x0000 0790
Physical Address0x5800 1790InstanceDISPC
DescriptionThe register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVINCRESERVEDFIRHINC
BitsField NameDescriptionTypeReset
31:29RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
28:16FIRVINCVertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
15:13RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0
12:0FIRHINCHorizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid.RW0x0400
Table 13-328 DISPC_WB_ACCU2_j
Address Offset0x0000 0794 + (0x4 * j)Indexj = 0 to 1
Physical Address0x5800 1794 + (0x4 * j)InstanceDISPC
DescriptionThe register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVERTICALACCURESERVEDHORIZONTALACCU
BitsField NameDescriptionTypeReset
31:27RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
26:16VERTICALACCUVertical initialization accu value Encoded value (from –1024 to 1023).RW0x000
15:11RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
10:0HORIZONTALACCUHorizontal initialization accu value Encoded value (from –1024 to 1023).RW0x000
Table 13-329 DISPC_WB_FIR_COEF_H2_i
Address Offset0x0000 07A0 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 17A0 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
FIRHC3FIRHC2FIRHC1FIRHC0
BitsField NameDescriptionTypeReset
31:24FIRHC3Signed coefficient C3 for the horizontal up/down-scaling with the phase nRW0x00
23:16FIRHC2Unsigned coefficient C2 for the horizontal up/down-scaling with the phase nRW0x00
15:8FIRHC1Signed coefficient C1 for the horizontal up/down-scaling with the phase nRW0x00
7:0FIRHC0Signed coefficient C0 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-330 DISPC_WB_FIR_COEF_HV2_i
Address Offset0x0000 07A4 + (0x8 * i)Indexi = 0 to 7
Physical Address0x5800 17A4 + (0x8 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
FIRVC2FIRVC1FIRVC0FIRHC4
BitsField NameDescriptionTypeReset
31:24FIRVC2Signed coefficient C2 for the vertical up/down-scaling with the phase nRW0x00
23:16FIRVC1Unsigned coefficient C1 for the vertical up/down-scaling with the phase nRW0x00
15:8FIRVC0Signed coefficient C0 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRHC4Signed coefficient C4 for the horizontal up/down-scaling with the phase nRW0x00
Table 13-331 DISPC_WB_FIR_COEF_V2_i
Address Offset0x0000 07E0 + (0x4 * i)Indexi = 0 to 7
Physical Address0x5800 17E0 + (0x4 * i)InstanceDISPC
DescriptionThe bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFIRVC22FIRVC00
BitsField NameDescriptionTypeReset
31:16RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
15:8FIRVC22Signed coefficient C22 for the vertical up/down-scaling with the phase nRW0x00
7:0FIRVC00Signed coefficient C00 for the vertical up/down-scaling with the phase nRW0x00
Table 13-332 DISPC_GLOBAL_BUFFER
Address Offset0x0000 0800
Physical Address0x5800 1800InstanceDISPC
DescriptionThe register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back).
Both TOP and BOTTOM must be allocated to the same pipeline.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWB_BUFFERVID3_BUFFERVID2_BUFFERVID1_BUFFERGFX_BUFFER
BitsField NameDescriptionTypeReset
31:30RESERVEDWrite 0's for future compatibility.
Reads return 0		R0x0
29:24WB_BUFFERWrite-back DMA buffer allocation to one of the pipelines. By default to write-back pipeline.RW0x24
0x24: DMA buffer allocated to the write-back pipeline.
0x0: DMA buffer allocated to the graphics pipeline.
0x9: DMA buffer allocated to the video1 pipeline.
0x12: DMA buffer allocated to the vdieo2 pipeline.
0x1B: DMA buffer allocated to the vdieo3 pipeline.
23:18VID3_BUFFERVideo3 DMA buffer allocation to one of the pipelines. By default to video3 pipeline.RW0x1B
0x24: DMA buffer allocated to the write-back pipeline.
0x0: DMA buffer allocated to the graphics pipeline.
0x9: DMA buffer allocated to the video1 pipeline.
0x12: DMA buffer allocated to the vdieo2 pipeline.
0x1B: DMA buffer allocated to the vdieo3 pipeline.
17:12VID2_BUFFERVideo2 DMA buffer allocation to one of the pipelines. By default to video2 pipeline.RW0x12
0x24: DMA buffer allocated to the write-back pipeline.
0x0: DMA buffer allocated to the graphics pipeline.
0x9: DMA buffer allocated to the video1 pipeline.
0x12: DMA buffer allocated to the vdieo2 pipeline.
0x1B: DMA buffer allocated to the vdieo3 pipeline.
11:6VID1_BUFFERVideo1 DMA buffer allocation to one of the pipelines. By default to video 1 pipeline.RW0x09
0x24: DMA buffer allocated to the write-back pipeline.
0x0: DMA buffer allocated to the graphics pipeline.
0x9: DMA buffer allocated to the video1 pipeline.
0x12: DMA buffer allocated to the vdieo2 pipeline.
0x1B: DMA buffer allocated to the vdieo3 pipeline.
5:0GFX_BUFFERGraphics DMA buffer allocation to one of the pipelines. By default to graphics pipeline.RW0x00
0x24: DMA buffer allocated to the write-back pipeline.
0x0: DMA buffer allocated to the graphics pipeline.
0x9: DMA buffer allocated to the video1 pipeline.
0x12: DMA buffer allocated to the vdieo2 pipeline.
0x1B: DMA buffer allocated to the vdieo3 pipeline.
Table 13-333 DISPC_DIVISOR
Address Offset0x0000 0804
Physical Address0x5800 1804InstanceDISPC
DescriptionThe register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use DISPC_DIVISOR1.LCD value instead of DISPC_DIVISOR.LCD bit field for generating the core functional clock.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLCDRESERVEDENABLE
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility. Reads return 0.R0x00
23:16LCDDisplay Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid.RW0x4
15:1RESERVEDWrite 0s for future compatibility. Reads return 0.R0x0000
0ENABLEWhen the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the value DISPC_DIVISOR1.LCD is used instead.RW0
0x0: DISPC_DIVISOR1.LCD bit field is used
0x1: DISPC_DIVISOR.LCD bit field is used
Table 13-334 DISPC_WB_ATTRIBUTES2
Address Offset0x0000 0810
Physical Address0x5800 1810InstanceDISPC
DescriptionThe register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode.
Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWBDELAYCOUNT
BitsField NameDescriptionTypeReset
31:8RESERVEDR0x000000
7:0WBDELAYCOUNTDelays the WB pipe flush after the end of the frame.
Delay = n (number of lines), where n = 0:255.
If n = 0, the WB is re-initialized just at the end of the last line of a frame at the beginning of the VFP signal.
If n = 1:255, the write buffers DMA are flushed n lines later.		RW0x00
Table 13-335 DISPC_DEFAULT_COLOR3
Address Offset0x0000 0814
Physical Address0x5800 1814InstanceDISPC
DescriptionThe control register allows to configure the default solid background color for the third LCD.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDEFAULTCOLOR
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x00
23:0DEFAULTCOLOR24-bit RGB color value to specify the default solid color to display when there is no data from the overlaysRW0x00 0000
Table 13-336 DISPC_TRANS_COLOR3
Address Offset0x0000 0818
Physical Address0x5800 1818InstanceDISPC
DescriptionThe register sets the transparency color value for the video/graphics overlays for the third LCD output.

Shadow register, updated on VFP start period of the third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTRANSCOLORKEY
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x00
23:0TRANSCOLORKEYTransparency color key value in RGB format
[0] BITMAP 1 (CLUT), [23,1] set to 0s
[1:0] BITMAP 2 (CLUT), [23,2] set to 0s
[3:0] BITMAP 4 (CLUT), [23,4] set to 0s
[7:0] BITMAP 8 (CLUT), [23,8] set to 0s
[11:0] RGB 12, [23,12] set to 0s
[15:0] RGB 16, [23,16] set to 0s
[23:0] RGB 24
NOTE: CLUT and BITMAP formats are not supported in this family of devices.		RW0x00 0000
Table 13-337 DISPC_CPR3_COEF_B
Address Offset0x0000 081C
Physical Address0x5800 181CInstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the blue component. It is used for the secondary LCD output.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
BRRESERVEDBGRESERVEDBB
BitsField NameDescriptionTypeReset
31:22BRBR coefficient
Encoded signed value (from –512 to 511)		RW0x000
21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
20:11BGBG coefficient
Encoded signed value (from –512 to 511)		RW0x000
10RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
9:0BBBB coefficient
Encoded signed value (from –512 to 511)		RW0x000
Table 13-338 DISPC_CPR3_COEF_G
Address Offset0x0000 0820
Physical Address0x5800 1820InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the green component. It is used for the secondary LCD output.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
GRRESERVEDGGRESERVEDGB
BitsField NameDescriptionTypeReset
31:22GRGRcoefficient
Encoded signed value (from –512 to 511)		RW0x000
21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
20:11GGGG coefficient
Encoded signed value (from –512 to 511)		RW0x000
10RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
9:0GBGB coefficient
Encoded signed value (from –512 to 511)		RW0x000
Table 13-339 DISPC_CPR3_COEF_R
Address Offset0x0000 0824
Physical Address0x5800 1824InstanceDISPC
DescriptionThe register configures the color phase rotation matrix coefficients for the red component.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RRRESERVEDRGRESERVEDRB
BitsField NameDescriptionTypeReset
31:22RRRR coefficient
Encoded signed value (from –512 to 511)		RW0x000
21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
20:11RGRG coefficient
Encoded signed value (from –512 to 511)		RW0x000
10RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
9:0RBRB coefficient
Encoded signed value (from –512 to 511)		RW0x000
Table 13-340 DISPC_DATA3_CYCLE1
Address Offset0x0000 0828
Physical Address0x5800 1828InstanceDISPC
DescriptionThe control register configures the output data format for the first cycle.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
27:24BITALIGNMENTPIXEL2Bit alignment
Alignment of the bits from pixel 2 on the output interface		RW0x0
23:21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
20:16NBBITSPIXEL2Number of bits
Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
15:12RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
11:8BITALIGNMENTPIXEL1Bit alignment
Alignment of the bits from pixel 1 on the output interface		RW0x0
7:5RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
4:0NBBITSPIXEL1Number of bits
Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
Table 13-341 DISPC_DATA3_CYCLE2
Address Offset0x0000 082C
Physical Address0x5800 182CInstanceDISPC
DescriptionThe control register configures the output data format for the second cycle.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
27:24BITALIGNMENTPIXEL2Bit alignment
Alignment of the bits from pixel 2 on the output interface		RW0x0
23:21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
20:16NBBITSPIXEL2Number of bits
Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
15:12RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
11:8BITALIGNMENTPIXEL1Bit alignment
Alignment of the bits from pixel 1 on the output interface		RW0x0
7:5RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
4:0NBBITSPIXEL1Number of bits
Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
Table 13-342 DISPC_DATA3_CYCLE3
Address Offset0x0000 0830
Physical Address0x5800 1830InstanceDISPC
DescriptionThe control register configures the output data format for the third cycle.

Shadow register, updated on VFP start period of third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDBITALIGNMENTPIXEL2RESERVEDNBBITSPIXEL2RESERVEDBITALIGNMENTPIXEL1RESERVEDNBBITSPIXEL1
BitsField NameDescriptionTypeReset
31:28RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
27:24BITALIGNMENTPIXEL2Bit alignment
Alignment of the bits from pixel 2 on the output interface		RW0x0
23:21RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
20:16NBBITSPIXEL2Number of bits
Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
15:12RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
11:8BITALIGNMENTPIXEL1Bit alignment
Alignment of the bits from pixel 1 on the output interface		RW0x0
7:5RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
4:0NBBITSPIXEL1Number of bits
Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid.		RW0x00
Table 13-343 DISPC_SIZE_LCD3
Address Offset0x0000 0834
Physical Address0x5800 1834InstanceDISPC
DescriptionThe register configures the panel size (horizontal and vertical). It is used for the third LCD output.

Shadow register, updated on VFP start period of the third LCD.
A delta value is used to indicate if the odd field is the same vertical size as the even field or ± one line.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLPPDELTA_LPPRESERVEDPPL
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27:16LPPLines per panel
Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1).		RW0x000
15:14DELTA_LPPIndicates the delta size value of the odd field compared to the even fieldRW0x0
0x0: Same size
0x1: Odd size = even size +1
0x2: Odd size = even size –1
13:12RESERVEDR0x0
11:0PPLPixels per line
Encoded value (from 1 to 4096) to specify the number of pixels contained within each line on the display
(program to value minus 1).
In STALL mode, any value is valid.
In non-STALL mode, only values of multiples of 8 pixels are valiid.		RW0x000
Table 13-344 DISPC_DIVISOR3
Address Offset0x0000 0838
Physical Address0x5800 1838InstanceDISPC
DescriptionThe register configures the divisors. It is used for the third LCD output.

Shadow register, updated on VFP start period of the third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLCDRESERVEDPCD
BitsField NameDescriptionTypeReset
31:24RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x00
23:16LCDDisplay controller logic clock divisor
Value (from 1 to 255) to specify the intermediate pixel clock frequency based on LCD2_CLK. The value 0 is invalid.		RW0x04
15:8RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x00
7:0PCDPixel clock divisor
Value (from 1 to 255) to specify the frequency of the pixel clock based on LCD2_CLK divided by the value of DISPC_DIVISOR2.LCD. The value 0 is invalid.		RW0x01
Table 13-345 DISPC_POL_FREQ3
Address Offset0x0000 083C
Physical Address0x5800 183CInstanceDISPC
DescriptionThe register configures the signal configuration. It is used for the third LCD output.

Shadow register, updated on VFP start period of the third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDALIGNONOFFRFIEOIPCIHSIVSACBIACB
BitsField NameDescriptionTypeReset
31:19RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0000
18ALIGNDefines the alignment betwwen HSYNC and VSYNC assertionRW0
0x0: VSYNC and HSYNC are not aligned.
0x1: VSYNC and HSYNC assertions are aligned.
17ONOFFHSYNC/VSYNC pixel clock control on/offRW0
0x0: HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.
0x1: HSYNC and VSYNC are driven according to bit 16.
Note: Control module register CTRL_CORE_SMA_SW_1[24] DSS_CH2_ON_OFF must be set to match
16RFProgram HSYNC/VSYNC rise or fallRW0
0x0: HSYNC and VSYNC are driven on the falling edge of the pixel clock (if bit 17 is set to 1).
0x1: HSYNC and VSYNC are driven onthe rising edge of the pixel clock (if bit 17 is set to 1).
Note: Control module register CTRL_CORE_SMA_SW_1[18] DSS_CH2_RF must be set to match
15IEOInvert output enableRW0
0x0: Ac-bias is active high (active display mode).
0x1: Ac-bias is active low (active display mode).
14IPCInvert pixel clockRW0
0x0: Data is driven on the LCD data lines on the
rising edge of the pixel clock.
0x1: Data is driven on the LCD data lines on the
falling edge of the pixel clock.
Note: Control module register CTRL_CORE_SMA_SW_1[21] DSS_CH2_IPC must be set to match
13IHSInvert HSYNCRW0
0x0: Line clock pin is active high and inactive low.
0x1: Line clock pin is active low and inactive high.
12IVSInvert VSYNCRW0
0x0: Frame clock pin is active high and inactive low.
0x1: Frame clock pin is active low and inactive high.
11:8ACBIAC bias pin transitions per interrupt
Value (from 0 to 15) used to specify the number of AC bias pin transitions		RW0x0
7:0ACBAC bias pin frequency
Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge buildup within the display.		RW0x00
Table 13-346 DISPC_TIMING_H3
Address Offset0x0000 0840
Physical Address0x5800 1840InstanceDISPC
DescriptionThe register configures the timing logic for the HSYNC signal. It is used for the third LCD output.
Shadow register, updated on VFP start period of the third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
HBPHFPHSW
BitsField NameDescriptionTypeReset
31:20HBPHorizontal back porch.
Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1).		RW0x000
19:8HFPHorizontal front porch.
Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before the line clock is asserted (program to value minus 1).		RW0x000
7:0HSWHorizontal synchronization pulse width.
Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1).		RW0x00
Table 13-347 DISPC_TIMING_V3
Address Offset0x0000 0844
Physical Address0x5800 1844InstanceDISPC
DescriptionThe register configures the timing logic for the VSYNC signal. It is used for the third LCD output.
Shadow register, updated on VFP start period of the third LCD
TypeRW
313029282726252423222120191817161514131211109876543210
VBPVFPVSW
BitsField NameDescriptionTypeReset
31:20VBPVertical back porch.
Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display		RW0x000
19:8VFPVertical front porch.
Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame		RW0x000
7:0VSWVertical synchronization pulse width.
In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode.		RW0x00
Table 13-348 DISPC_CONTROL3
Address Offset0x0000 0848
Physical Address0x5800 1848InstanceDISPC
DescriptionThe control register configures the display controller module for the third LCD output.
TypeRW
313029282726252423222120191817161514131211109876543210
SPATIALTEMPORALDITHERINGFRAMESRESERVEDTDMUNUSEDBITSTDMCYCLEFORMATTDMPARALLELMODETDMENABLERESERVEDRESERVEDOVERLAYOPTIMIZATIONSTALLMODERESERVEDTFTDATALINESSTDITHERENABLERESERVEDGOLCDM8BSTNTFTMONOCOLORRESERVEDLCDENABLE
BitsField NameDescriptionTypeReset
31:30SPATIALTEMPORALDITHERINGFRAMESSpatial/temporal dithering number of frames for the third LCD output
wr: VFP start period of the third LCD output		RW0x0
0x0: Spatial only
0x1: Spatial and temporal over two frames
0x3: Reserved
0x2: Spatial and temporal over four frames
29:27RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
26:25TDMUNUSEDBITSState of unused bits (TDM mode only) for the third LCD output
wr: VFP start period of the third LCD output		RW0x0
0x0: Low level (0)
0x1: High level (1)
0x3: Reserved
0x2: Unchanged from previous state
24:23TDMCYCLEFORMATCycle format (TDM mode only) for the third LCD output
wr: VFP start period of third LCD output		RW0x0
0x0: One cycle for 1 pixel
0x1: Two cycles for 1 pixel
0x3:Three cycles for 2 pixels
0x2: Three cycles for 1 pixel
22:21TDMPARALLELMODEOutput interface width (TDM mode only) for the third LCD output
wr: VFP start period of the third LCD output		RW0x0
0x0: 8-bit parallel output interface selected
0x1: 9-bit parallel output interface selected
0x3: 16-bit parallel output interface selected
0x2: 12-bit parallel output interface selected
20TDMENABLEEnable the multiple cycle format for the third LCD output
wr: VFP start period of third LCD output		RW0
0x0: TDM disabled
0x1: TDM enabled
19:14RESERVEDWrite 0s for future compatibility.
Reads return 0.		RW0x00
13RESERVEDReservedR0
12OVERLAYOPTIMIZATIONOverlay optimization for the third LCD output
wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output, or write-back to the memory.		RW0
0x0: All the data for all the enabled pipelines are fetched from memory regardless of the overlay/alpha blending configuration.
0x1: The data not used by the overlay manager because of overlap between layers with no alpha blending between them must not be fetched from memory to optimize the bandwidth.
11STALLMODESTALL mode for the third LCD output
wr: VFP start period of the third LCD output		RW0
0x0: Normal mode selected
0x1: STALL mode selected. The display controller sends the data without considering the VSYNC/HSYNC. The LCD output is disabled at the end of the transfer of the frame. Software must reenable the LCD output to generate a new frame.
10RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
9:8TFTDATALINESNumber of lines of the third LCD interface
wr: VFP start period of the third LCD output		RW0x0
0x0: 12-bit output aligned on the LSB of the pixel data interface
0x1: 16-bit output aligned on the LSB of the pixel data interface
0x3: 24-bit output aligned on the LSB of the pixel data interface
0x2: 18-bit output aligned on the LSB of the pixel data interface
7STDITHERENABLESpatial temporal dithering enable for the third LCD output
wr: VFP start period of the third LCD output		RW0
0x0: Spatial/temporal dithering logic disabled
0x1: Spatial/temporal dithering logic enabled
6RESERVEDReservedR0
5GOLCDGO command for the third LCD output. It is used to synchronized the pipelines (graphics and/or video) associated with the third LCD output.
wr: Immediate		RW0
0x0: The hardware has finished updating the internal shadow registers of the pipeline(s) connected to the LCD output using the user values. The hardware resets the bit when the update is complete.
0x1: The user has finished programming the shadow registers of the pipeline(s) associated with the LCD output, and the hardware can update the internal registers at the VFP start period.
4M8BMono 8-bit mode of the third LCD
wr: VFP start period of the third LCD output		RW0
0x0: Reserved
0x1: Reserved
3STNTFTLCD Display type of the third LCD
wr: VFP start period of the third LCD output		RW0
0x0: Reserved
0x1: Active matrix display operation enabled
2MONOCOLORMonochrome/color selection for the third LCD
wr: VFP start period of the third LCD output		RW0
0x0: Reserved
0x1: Reserved
1RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
0LCDENABLEEnable the third LCD output
wr: Immediate		RW0
0x0: LCD output disabled (at the end of the frame when the bit is reset)
0x1: LCD output enabled
Table 13-349 DISPC_CONFIG3
Address Offset0x0000 084C
Physical Address0x5800 184CInstanceDISPC
DescriptionThe control register configures the display controller module for the third LCD output.
Shadow register, updated on VFP start period of the third LCD or EVSYNC
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTLCDINTERLEAVEFULLRANGECOLORCONVENABLEFIDFIRSTOUTPUTMODEENABLEBT1120ENABLEBT656ENABLERESERVEDCPRRESERVEDTCKLCDSELECTIONTCKLCDENABLERESERVEDACBIASGATEDVSYNCGATEDHSYNCGATEDPIXELCLOCKGATEDPIXELDATAGATEDRESERVEDPIXELGATED
BitsField NameDescriptionTypeReset
31:28RESERVEDReservedR0x0
27:26TLCDINTERLEAVEtLCD interleave PatternRW0x0
25FULLRANGEColor space conversion full range settingRW0
0x0: Limited range selected
0x1: Full range selected
24COLORCONVENABLEEnable the color space conversion. It must be reset when the CPR bit field is set to 0x1.RW0
0x0: Disable color space conversion RGB to YUV.
0x1: Enable color space conversion RGB to YUV.
23FIDFIRSTSelects the first field to output in case of interlace mode. In case of progressive mode, the value is not used.RW0
0x0: First field is even.
0x1: Odd field is first.
22OUTPUTMODEENABLESelects between progressive and interlace mode for the third LCD outputRW0
0x0: Progressive mode selected
0x1: Interlace mode selected
21BT1120ENABLESelects BT.1120 format on the third LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time on the same LCD output.RW0
0x0: BT.1120 is disabled.
0x1: BT.1120 is enabled.
20BT656ENABLESelects BT.656 format on the third LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time on the same LCD output.RW0
0x0: BT.656 is disabled.
0x1: BT.656 is enabled.
19:16RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
15CPRColor phase rotation control ( third LCD output). It must be reset when the ColorConvEnable bit field is set to 1.
wr: VFP start period of the third LCD output		RW0
0x0: Color phase rotation disabled
0x1: Color phase rotation enabled
14:12RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
11TCKLCDSELECTIONTransparency color key selection (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: Destination transparency color key selected
0x1: Source transparency color key selected
10TCKLCDENABLETransparency color key enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: Disable the transparency color key for the LCD
0x1: Enable the transparency color key for the LCD
9RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0
8ACBIASGATEDACBias gated enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: AcBias gated disabled
0x1: AcBias gated enabled
7VSYNCGATEDVSYNC gated enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: VSYNC gated disabled
0x1: VSYNC gated enabled
6HSYNCGATEDHSYNC gated enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: HSYNC gated disabled
0x1: HSYNC gated enabled
5PIXELCLOCKGATEDPixel clock gated enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: Pixel clock gated disabled
0x1: Pixel clock gated enabled
4PIXELDATAGATEDPixel data gated enabled (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: Pixel data gated disabled
0x1: Pixel data gated enabled
3:1RESERVEDWrite 0s for future compatibility.
Reads return 0.		R0x0
0PIXELGATEDPixel gated enable (only for TFT) (third LCD output)
wr: VFP start period of the third LCD output		RW0
0x0: Pixel clock always toggles (only in TFT mode).
0x1: Pixel clock toggles only when there is valid data to display (only in TFT mode).
Table 13-350 DISPC_GAMMA_TABLE3
Address Offset0x0000 0850
Physical Address0x5800 1850InstanceDISPC
DescriptionThe register configures the gamma table on the third LCD output.
TypeW
313029282726252423222120191817161514131211109876543210
INDEXVALUE_RVALUE_GVALUE_B
BitsField NameDescriptionTypeReset
31:24INDEXDefines the location in the table where the VALUE bit field is stored.W0x00
23:16VALUE_R8-bit value used to define the value to store at the location in the table defined by the INDEX bit fieldW0x00
15:8VALUE_G8-bit value used to define the value to store at the location in the table defined by the INDEX bit fieldW0x00
7:0VALUE_B8-bit value used to define the value to store at the location in the table defined by the INDEX bit fieldW0x00
Table 13-351 DISPC_BA0_FLIPIMMEDIATE_EN
Address Offset0x0000 0854
Physical Address0x5800 1854InstanceDISPC
DescriptionThis register enables the flip immediate.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVID3VID2VID1GFX
BitsField NameDescriptionTypeReset
31:4RESERVEDReserved.R0x000 0000
3VID3Enable flip immediate for video3 pipelineRW0x0
2VID2Enable flip immediate for video2 pipelineRW0x0
1VID1Enable flip immediate for video1 pipelineRW0x0
0GFXEnable flip immediate for gfx pipelineRW0x0
Table 13-352 DISABLE_MSTANDBY_ENHANCEMENT
Address Offset0x0000 0858
Physical Address0x5800 1858InstanceDISPC
DescriptionThis register disables the DISPC DMA Mstandby behavior enhancement.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDISABLE_MSTANDBY_ENHANCEMENT
BitsField NameDescriptionTypeReset
31:1RESERVEDReserved.R0x0
0DISABLE_MSTANDBY_ENHANCEMENT0: DISPC DMA Mstandby behavior enhancement is enabled.
1: Disable DISPC DMA Mstandby behavior enhancement. This is the recommended setting.		RW0x0
Table 13-353 DISPC_GLOBAL_MFLAG_ATTRIBUTE
Address Offset0x0000 085C
Physical Address0x5800 185CInstanceDISPC
DescriptionGlobal MFLAG atrribute control register.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMFLAG_STARTMFLAG_CTRL
BitsField NameDescriptionTypeReset
31:3RESERVEDReserved.R0x0000 0000
2MFLAG_STARTMFLAG StartRW0x0
0x0: When the DMA buffer is empty at the beginning of the frame, MFLAG signal of each pipeline is kept at 0 until PRELOAD is reached, then based on MFLAG_CTRL bitfield MFLAG is generated and internal logic is arbitrating between pipeline requests
0x1: Even at the beginning of the frame when the DMA buffer is empty, MFLAG_CTRL bitfield is used to determine how MFLAG signal for each pipeline shall be driven.
1:0MFLAG_CTRLMFLAG controlRW0x0
0x0: MFLAG mechanism is disabled: MFLAG out of band signal is set to 0
0x1: MFLAG mechanism is enabled: MFLAG out of band signal is always set to 1 (force mode for debug)
0x2: MFLAG mechanism is enabled and MFLAG out of band signal is dynamically set and reset depending on MFLAG rules.
Table 13-354 DISPC_GFX_MFLAG_THRESHOLD
Address Offset0x0000 0860
Physical Address0x5800 1860InstanceDISPC
DescriptionMFLAG thresholds for graphics pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
HT_MFLAGLT_MFLAG
BitsField NameDescriptionTypeReset
31:16HT_MFLAGHigh Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0RW0x0000
15:0LT_MFLAGLow Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1RW0x0000
Table 13-355 DISPC_VID1_MFLAG_THRESHOLD
Address Offset0x0000 0864
Physical Address0x5800 1864InstanceDISPC
DescriptionMFLAG thresholds for video1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
HT_MFLAGLT_MFLAG
BitsField NameDescriptionTypeReset
31:16HT_MFLAGHigh Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0RW0x0000
15:0LT_MFLAGLow Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1RW0x0000
Table 13-356 DISPC_VID2_MFLAG_THRESHOLD
Address Offset0x0000 0868
Physical Address0x5800 1868InstanceDISPC
DescriptionMFLAG thresholds for video2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
HT_MFLAGLT_MFLAG
BitsField NameDescriptionTypeReset
31:16HT_MFLAGHigh Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0RW0x0000
15:0LT_MFLAGLow Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1RW0x0000
Table 13-357 DISPC_VID3_MFLAG_THRESHOLD
Address Offset0x0000 086C
Physical Address0x5800 186CInstanceDISPC
DescriptionMFLAG thresholds for video3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory.
TypeRW
313029282726252423222120191817161514131211109876543210
HT_MFLAGLT_MFLAG
BitsField NameDescriptionTypeReset
31:16HT_MFLAGHigh Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0RW0x0000
15:0LT_MFLAGLow Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1RW0x0000
Table 13-358 DISPC_WB_MFLAG_THRESHOLD
Address Offset0x0000 0870
Physical Address0x5800 1870InstanceDISPC
DescriptionMFLAG thresholds for write-back pipeline. Shadow register, updated when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the DISPC_WB_ATTRIBUTES2.WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both DISPC_CONTROL2.GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used.
TypeRW
313029282726252423222120191817161514131211109876543210
HT_MFLAGLT_MFLAG
BitsField NameDescriptionTypeReset
31:16HT_MFLAGHigh Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0RW0x0000
15:0LT_MFLAGLow Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1RW0x0000