SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4A00 8000 | Instance | CM_CORE__OCP_SOCKET |
Description | This register contains the IP revision code for the CM_CORE part of the PRCM | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | IP Revision number | R | 0x-(1) |
PRCM Register Manual |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4A00 8040 | Instance | CM_CORE__OCP_SOCKET |
Description | This register manages the CM_CORE_PROFILING clocks. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEST | RESERVED | MODULEMODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:18 | RESERVED | R | 0x0 | |
17:16 | IDLEST | Module idle status | R | 0x3 |
0x0: Module is fully functional | ||||
0x1: Module is performing transition: wakeup, or sleep, or sleep abortion | ||||
0x2: Module is in Idle | ||||
0x3: Module is disabled | ||||
15:2 | RESERVED | R | 0x0 | |
1:0 | MODULEMODE | Control the way mandatory clocks are managed. | RW | 0x1 |
0x0: Module is disabled by SW. OCP configuration port is not accessible. | ||||
0x1: Module is managed automatically by HW along with L3INSTR domain. | ||||
0x2: Reserved | ||||
0x3: Reserved |
PRCM Register Manual |
Address Offset | 0x0000 00F0 | ||
Physical Address | 0x4A00 80F0 | Instance | CM_CORE__OCP_SOCKET |
Description | This register is used to configure the CM_CORE's 32-bit debug output. There is one 8-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL3 | SEL2 | SEL1 | SEL0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | SEL3 | Internal signal block select for debug word byte-3 | RW | 0x3 |
23:16 | SEL2 | Internal signal block select for debug word byte-2 | RW | 0x2 |
15:8 | SEL1 | Internal signal block select for debug word byte-1 | RW | 0x1 |
7:0 | SEL0 | Internal signal block select for debug word byte-0 | RW | 0x0 |
PRCM Register Manual |