SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4A00 9E18 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3MAIN1_CLKSTCTRL. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3MAIN1_CLKSTCTRL register. | RW | 0x0 |
PRCM Register Manual |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4A00 9E20 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L4CFG_CLKSTCTRL. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L4CFG_CLKSTCTRLregister. | RW | 0x0 |
PRCM Register Manual |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4A00 9E28 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L4PER_CLKSTCTRL. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L4PER_CLKSTCTRL register. | RW | 0x0 |
PRCM Register Manual |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4A00 9E2C | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3INIT_CLKSTCTRL. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3INIT_CLKSTCTRL register. | RW | 0x0 |
PRCM Register Manual |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4A00 9E30 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3INSTR_L3_MAIN_2_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3INSTR_L3_MAIN_3_CLKCTRL register. | RW | 0x30001 |
Clock Management Functional Description |
PRCM Register Manual |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4A00 9E34 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3INSTR_L3_INSTR_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3INSTR_L3_INSTR_CLKCTRL register. | RW | 0x30001 |
Clock Management Functional Description |
PRCM Register Manual |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4A00 9E38 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3INSTR_OCP_WP_NOC_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3INSTR_OCP_WP_NOC_CLKCTRL register. | RW | 0x30001 |
Clock Management Functional Description |
PRCM Register Manual |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4A00 9E3C | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_CM_CORE_PROFILING_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive] | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_CM_CORE_PROFILING_CLKCTRL register. | RW | 0x30001 |
PRCM Register Manual |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4A00 9E48 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L3MAIN1_DYNAMICDEP. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L3MAIN1_DYNAMICDEP register. | RW | 0x4001058 |
PRCM Register Manual |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4A00 9E58 | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L4CFG_DYNAMICDEP. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L4CFG_DYNAMICDEP register. | RW | 0x40789f2 |
PRCM Register Manual |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4A00 9E5C | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_L4PER_DYNAMICDEP. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_L4PER_DYNAMICDEP register. | RW | 0x4004180 |
PRCM Register Manual |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4A00 9E6C | Instance | CM_CORE__RESTORE |
Description | Second address map for register CM_DMA_STATICDEP. Used only by automatic restore upon wakeup from device OFF mode. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESTORE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESTORE | See CM_DMA_STATICDEP register. | RW | 0xb0f0 |
PRCM Register Manual |