SPRUJ07 august   2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x and F28P65x
    1. 1.1 F2837x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP and 100-Pin PZP Package
    2. 2.2 Use of Existing 176-Pin F2837x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins with Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 100-Pin PZP New PCB Design
    5. 2.5 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1 Lock-step Compare Module (LCM)
      2. 3.1.2 Expanded Analog Channels
      3. 3.1.3 Firmware Update (FWU)
      4. 3.1.4 Flexible GPIO and Digital Input Pins
      5. 3.1.5 ADC Hardware Redundancy Safety Checker
      6. 3.1.6 Flexible Memory Sharing between CPU Subsystems
      7. 3.1.7 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2837x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2837x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2837x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2837x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5EABI Support
    1. 5.1 NoINIT Struct Fix (Linker Command)
    2. 5.2 Pre-Compiled Libraries
  9.   References

3.5.2 Bootrom

For bootrom similarities and differences between F2837x and F28P65x see Table 3-6 and Table 3-9.

Table 3-6 Bootrom Comparison Table
F2837x F28P65x
Initiate Boot Process CPU1: Device Reset; CPU2: CPU1 Application
GPIO Boot Mode Selection Supported only in CPU1
IPC Boot Mode selection Supported in CPU2 Supported in CPU2
Boot Modes Flash Supported in CPU1,CPU2 Supported in CPU1, CPU2
Secure Flash Supported in CPU1,CPU2 Supported in CPU1, CPU2
RAM Supported in CPU1,CPU2 Supported in CPU1, CPU2
OTP Supported in CPU2 Supported in CPU2
Copy from IPC message RAM to local RAM CPU1: No

CPU2: CPU1TOCPU2MSGRAM1

CM: CPU1TOCMMSGRAM1

 CPU1: No

CPU2: CPU1TOCPU2MSGRAM1
Boot Loader Support CPU1: I2C,CAN,SPI,SCI,Parallel,USB CPU1: I2C,CAN,MCAN,SPI,SCI,Parallel, USB, and FWU
ROM Contents AES tables and Motor Control Library is included AES tables and Motor Control Library are excluded
PLL Option No option to switch PLL during CPU1 boot Option to switch PLL during CPU1 boot
Lockstep Initialization Lockstep not available Lockstep initialization performed in CPU2 boot code
MPOST Can execute at 110MHz, 80MHz and 60MHz PLL output clock Can execute at 150MHz, 75MHz PLL output clock as well as INTOSC clock
Table 3-7 Boot Options Legend
Color Description
Options common for both devices but BOOTDEFx values may differ
Options applicable only for F2837x
Options applicable only for F28P65x
Table 3-8 Bootloaders and GPIO Assignment Comparison
Bootloader Option BOOTDEFx F2837x F28P65x
Parallel 0 0x00 D0-D7=89,90,58-62,88; DSP=91; Host=92 D0-D7=0 to 7; DSP=10; Host=11
1 0x20 n/a D0-D7=89,90,58-62,88; DSP=91; Host=92
SCIA 0 0x01 TX=29; RX=28 TX=12; RX=13
1 0x21 TX=84; RX=85 TX=84; RX=85
2 0x41 TX=36; RX=35 TX=36; RX=35
3 0x61 TX=42; RX=43 TX=42; RX=43
4 0x81 TX=65; RX=64 TX=65; RX=64
5 0xA1 TX=135; RX=136 TX=29; RX=28
6 0xC1 TX=8; RX=9 TX=8; RX=9
CAN 0 0x02 TX=37; RX=36 TX=4; RX=5
1 0x22 TX=71; RX=70 TX=19; RX=18
2 0x42 TX=63; RX=62 TX=31; RX=30
3 0x62 TX=19; RX=18 TX=37; RX=36
4 0x82 TX=4; RX=5 TX=63; RX=62
5 0xA2 TX=31; RX=30 TX=71; RX=70
MCAN 0 0x08 n/a TX=4; RX=5
1 0x18 n/a TX=8; RX=10
2 0x28 n/a TX=19; RX=18
3 0x38 n/a TX=71; RX=70
4 0x48 n/a TX=74; RX=75
SPI 0 0x06 SIMO=58; SOMI=59; CLK=60; STE=61 PICO=58; POCI=55; CLK=56; PTE=57
1 0x26 SIMO=16; SOMI=17; CLK=18; STE=19 PICO=202; POCI=203; CLK=204; PTE=205
2 0x46 SIMO=32; SOMI=33; CLK=34; STE=35 PICO=16; POCI=17; CLK=18; PTE=19
3 0x66 SIMO=16; SOMI=17; CLK=56; STE=57 PICO=58; POCI=59; CLK=34; PTE=35
4 0x86 SIMO=54; SOMI=55; CLK=56; STE=57 n/a
I2C 0 0x07 SDA=91; SCL=92 SDA=0; SCL=1
1 0x27 SDA=32; SCL=33 SDA=42; SCL=43
2 0x47 SDA=42; SCL=43 SDA=91; SCL=92
3 0x67 SDA=0; SCL=1 SDA=104; SCL=105
4 0x87 SDA=104; SCL=105 n/a
USB 0 0x09 DM=42; DP=43 DM=42; DP=43
Table 3-9 Boot Modes Comparison
Boot Mode Option BOOTDEFx F2837x F28P65x
Flash 0 0x03 CPU1: Entry=0x00080000;
 CPU1/CPU2: Entry=0x00080000;
1 0x23 CPU1: Entry=0x00088000;
CPU1/CPU2: Entry=0x0009FFF0;
2 0x43 CPU1: Entry=0x000A8000;
CPU1/CPU2: Entry=0x000A0000;
3 0x63 CPU1: Entry=0x000BE000;
CPU1/CPU2: Entry=0x000C0000;
4 0x83 - CPU1/CPU2: Entry=0x000E0000;
5 0xA3 - CPU1/CPU2: Entry=0x00100000;
6 0xC3 - CPU1/CPU2: Entry=0x0011FFF0;
Secure Flash 0 0x0A CPU1: Entry=0x00080000;
CPU1/CPU2: Entry=0x00080000;
1 0x2A CPU1: Entry=0x00088000; Bank/Sector=0/4 -
2 0x4A CPU1: Entry=0x000A8000;
CPU1/CPU2: Entry=0x000A0000;
3 0x6A CPU1: Entry=0x000BE000;
CPU1/CPU2: Entry=0x000C0000;
4 0x8A - CPU1/CPU2: Entry=0x000E0000;
5 0xAA - CPU1/CPU2: Entry=0x00100000;
CPU1 FWU Flash 0 0x0B - Entry=0x00080000; Bank=0
Entry=0x000A0000; Bank=1
Entry=0x000C0000 Bank=2
Entry=0x000E0000 Bank=3
Entry=0x00100000 Bank=4
1 0x2B - Entry=0x0008FFF0; Bank=0
Entry=0x000AFFF0; Bank=1
Entry=0x000CFFF0 Bank=2
Entry=0x000EFFF0 Bank=3
Entry=0x0010FFF0 Bank=4
2 0x4B - Entry=0x00090000; Bank=0
Entry=0x000B0000; Bank=1
Entry=0x000D0000 Bank=2
Entry=0x00F0000 Bank=3
Entry=0x00110000 Bank=4
3 0x6B - Entry=0x0009FFF0; Bank=0
Entry=0x000BFFF0; Bank=1
Entry=0x000DFFF0 Bank=2
Entry=0x000FFFF0 Bank=3
Entry=0x0011FFF0 Bank=4
CPU2 FWU Flash 0 0x06 - Entry=0x00080000; Bank=0
Entry=0x000A0000; Bank=1
Entry=0x000C0000 Bank=2
Entry=0x000E0000 Bank=3
Entry=0x00100000 Bank=4
1 0x26 - Entry=0x0008FFF0; Bank=0
Entry=0x000AFFF0; Bank=1
Entry=0x000CFFF0 Bank=2
Entry=0x000EFFF0 Bank=3
Entry=0x0010FFF0 Bank=4
2 0x46 - Entry=0x00090000; Bank=0
Entry=0x000B0000; Bank=1
Entry=0x000D0000 Bank=2
Entry=0x00F0000 Bank=3
Entry=0x00110000 Bank=4
3 0x66 - Entry=0x0009FFF0; Bank=0
Entry=0x000BFFF0; Bank=1
Entry=0x000DFFF0 Bank=2
Entry=0x000FFFF0 Bank=3
Entry=0x0011FFF0 Bank=4
Wait 0 0x04 Watchdog enabled Watchdog enabled
1 0x24 Watchdog disabled Watchdog disabled
RAM 0 0x05 Entry=0x00000000 Entry=0x00000000