SPRUJ07 august   2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x and F28P65x
    1. 1.1 F2837x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP and 100-Pin PZP Package
    2. 2.2 Use of Existing 176-Pin F2837x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins with Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 100-Pin PZP New PCB Design
    5. 2.5 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1 Lock-step Compare Module (LCM)
      2. 3.1.2 Expanded Analog Channels
      3. 3.1.3 Firmware Update (FWU)
      4. 3.1.4 Flexible GPIO and Digital Input Pins
      5. 3.1.5 ADC Hardware Redundancy Safety Checker
      6. 3.1.6 Flexible Memory Sharing between CPU Subsystems
      7. 3.1.7 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2837x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2837x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2837x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2837x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5EABI Support
    1. 5.1 NoINIT Struct Fix (Linker Command)
    2. 5.2 Pre-Compiled Libraries
  9.   References

3.3 Control Module Changes

There are changes in the control modules between the F2837x and F28P65x devices. The biggest changes come from the EPWM and ECAP on the F28P65x device. Table 3-2 shows the module instances differences which should be considered when migrating applications between F2837x and F28P65x.

Table 3-2 Control Module Differences
Module Category F2837x F28P65x Notes
SDFM Number 8 - SD1_D1C1..D4C4, SD2_D1C1..D4C4 16 - SD1_D1C1..D4C4, SD2_D1C1..D4C4, SD3_D1C1..D4C4,SD4_D1C1..D4C4
Registers SDIFLG.MIF MIF description updated to "Main" Interrupt Flag on F28P65x
SDIFLGCLR.MIF MIF description updated to "Main" Interrupt Flag on F28P65x
SDCTL.MIE MIE description updated to "Main" SDy_ERR Interrupt enable on F28P65x
SDMFILEN.MFE SDMFILEN description updated to SD "Main" Filter Enable on F28P65x. MFE description updated to "Main" Filter Enable on F28P65x
eQEP Number 3 - EQEP1..3 6 - EQEP1..6
Registers REV.MINOR=1 REV.MINOR=2
QEPSRCSEL More input options on F28P65x
eCAP Number 6- ECAP1..6 7 - ECAP1..7
Registers ECCTL0.INPUTSEL[0..6] ECCTL0.INPUTSEL[0..7]
- ECCTL0.QUALPRD Qualification period for noise filtering
- ECCTL0.SOCEVTSEL ADC SOC event select
ECCTL2.DMAEVTSEL APWM mode triggering added on F28P65x
- ECEINT.MUNIT_1..2_ERROR_EVT1..2 Monitoring unit error event interrupt enable
- ECFLG.MUNIT_1..2_ERROR_EVT1..2 Monitoring unit error event interrupt flag
- ECCLR.MUNIT_1..2_ERROR_EVT1..2 Monitoring unit error event interrupt flag clear
- ECFRC.MUNIT_1..2_ERROR_EVT1..2 Monitoring unit error event interrupt flag force
ECAPSYNCINSEL More input options on F28P65x
Other - Additional signal monitoring functionality with new registers : ECAP_SIGNAL_MONITORING
HRCAP Number 2 - HRCAP5, HRCAP6 2 - HRCAP6, HRCAP7
ePWM Number 12 - EPWM1..12 18 - EPWM1..18
Registers EPWMSYNCINSEL More EPWMxSYNCI options on F28P65x
- CMPCTL.LINKDUTYHR CMPAHR, CMPBHR Register Linking
GLDCTL.GLDMODE Extra options on F28P65x=> 1000:Load on Counter=CMPCU, 1001:Load on Counter=CMPCD, 1010:Load on Counter=CMPDU, 1011:Load on Counter=CMPDD
EPWMXLINK 4-bit fields on F2837x to corresponding 5-bit fields on F28P65x
- TZEINT.CAPEVT Capture Event Interrupt Enable
- TZFLG.CAPEVT Capture Event Flag
- TZCBCFLG.CAPEVT Cycle-By-Cycle Capture Event Flag
- TZOSTFLG.CAPEVT One-Shot Capture Event Flag
- TZCLR.CAPEVT Capture Event Clear
- TZCBCCLR.CAPEVT Cycle-By-Cycle Capture Event Clear
- TZOSTCLR.CAPEVT One-Shot Capture Event Clear
- TZFRC.CAPEVT Force Capture Event
ETSEL.INTSEL Value 011 is ETINTMIX on F28P65x and TBCTR=0|PRD on F2837x
ETSEL.SOCASEL Value 011 is ETSOCAMIX on F28P65x and TBCTR=0|PRD on F2837x
ETSEL.SOCBSEL Value 011 is ETSOCBMIX on F28P65x and TBCTR=0|PRD on F2837x
DCFCTL.PULSESEL Value 11 is BLANKPULSEMIX on F28P65x
- HRCNFG.HRLOAD Value 11 is CMPA_EQ on F28P65x
- HRCNFG.HRLOADB Value 11 is CMPB_EQ on F28P65x
EPWM_REGS.HRPWR OTTOCAL_REGS.HRPWR HRPWM Power Register
EPWM_REGS.HRMSTEP OTTOCAL_REGS.HRMSTEP HRPWM MEP Step Register
- EPWMXLINK2 EPWMx Link 2 Register
- TZSEL2 Trip Zone Select Register 2
- TZTRIPOUTSEL Trip Out Select Register
- ETINTMIXEN Event-Trigger Mixed INT Selection Register
- ETSOCAMIXEN Event-Trigger Mixed SOCA Selection Register
- ETSOCBMIXEN Event-Trigger Mixed SOCB Selection Register
- BLANKPULSEMIXSEL Blanking Window Trigger Pulse Selec Register
- DCCAPMIXSEL Capture Event Pulse Select Register
- CAPCTL Event Capture Control Register
- CAPGATETRIPSEL Event Capture Gate Trip Input Select Register
- CAPINTRIPSEL Event Catpure Trip Input Select Register
- CAPTRIPSEL Event Capture Signal Select Register
- EPWM_XCMP_REGS XCMP Registers
- DE_REGS Diode Emulation Registers
- MINDB_LUT_REGS Minimum Dead Band and Look-Up Table Registers
HRPWM Number 8 - HRPWM1..8 18 - HRPWM1..18
Clock Source EPWM1CLK Respective EPWM