SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
There is no retention logic for cryptography registers. The clocks can be enabled or gated by the following PRCM registers:
The cryptography module is enabled and disabled by the SECDMAHWOPT.CRYPTO_EN bit.
To save power, the application can disable the clock to the AES module when not in use. The AES is clock-gated in sleep mode by setting the SECDMACLKGS register CRYPTO_CLK_EN bit. The AES can also be clock-gated in run mode by setting the SECDMACLKGR register CRYPTO_CLK_EN bit.