SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

20.8.2 AUX_AIODIO Registers

Table 20-54 lists the memory-mapped registers for the AUX_AIODIO registers. All register offset addresses not listed in Table 20-54 should be considered as reserved locations and the register contents should not be modified.

Table 20-54 AUX_AIODIO Registers
OffsetAcronymRegister NameSection
0hIOMODEInput Output ModeIOMODE Register (Offset = 0h) [Reset = 00000000h]
4hGPIODIEGeneral Purpose Input Output Digital Input EnableGPIODIE Register (Offset = 4h) [Reset = 00000000h]
8hIOPOEInput Output Peripheral Output EnableIOPOE Register (Offset = 8h) [Reset = 00000000h]
ChGPIODOUTGeneral Purpose Input Output Data OutGPIODOUT Register (Offset = Ch) [Reset = 00000000h]
10hGPIODINGeneral Purpose Input Output Data InGPIODIN Register (Offset = 10h) [Reset = 00000000h]
14hGPIODOUTSETGeneral Purpose Input Output Data Out SetGPIODOUTSET Register (Offset = 14h) [Reset = 00000000h]
18hGPIODOUTCLRGeneral Purpose Input Output Data Out ClearGPIODOUTCLR Register (Offset = 18h) [Reset = 00000000h]
1ChGPIODOUTTGLGeneral Purpose Input Output Data Out ToggleGPIODOUTTGL Register (Offset = 1Ch) [Reset = 00000000h]
20hIO0PSELInput Output 0 Peripheral SelectIO0PSEL Register (Offset = 20h) [Reset = 00000000h]
24hIO1PSELInput Output 1 Peripheral SelectIO1PSEL Register (Offset = 24h) [Reset = 00000000h]
28hIO2PSELInput Output 2 Peripheral SelectIO2PSEL Register (Offset = 28h) [Reset = 00000000h]
2ChIO3PSELInput Output 3 Peripheral SelectIO3PSEL Register (Offset = 2Ch) [Reset = 00000000h]
30hIO4PSELInput Output 4 Peripheral SelectIO4PSEL Register (Offset = 30h) [Reset = 00000000h]
34hIO5PSELInput Output 5 Peripheral SelectIO5PSEL Register (Offset = 34h) [Reset = 00000000h]
38hIO6PSELInput Output 6 Peripheral SelectIO6PSEL Register (Offset = 38h) [Reset = 00000000h]
3ChIO7PSELInput Output 7 Peripheral SelectIO7PSEL Register (Offset = 3Ch) [Reset = 00000000h]
40hIOMODELInput Output Mode LowIOMODEL Register (Offset = 40h) [Reset = 00000000h]
44hIOMODEHInput Output Mode HighIOMODEH Register (Offset = 44h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 20-55 shows the codes that are used for access types in this section.

Table 20-55 AUX_AIODIO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

20.8.2.1 IOMODE Register (Offset = 0h) [Reset = 00000000h]

IOMODE is shown in Figure 20-48 and described in Table 20-56.

Return to the Summary Table.

Input Output Mode
This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-48 IOMODE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
IO7IO6IO5IO4IO3IO2IO1IO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-56 IOMODE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14IO7R/W0hSelects mode for AUXIO[8i+7].
0h = Output Mode:
When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7].
When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7].
1h = Input Mode:
When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer.
When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 7 is 0:
- If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high.
When IOPOE bit 7 is 1:
- If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high.
13-12IO6R/W0hSelects mode for AUXIO[8i+6].
0h = Output Mode:
When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6].
When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6].
1h = Input Mode:
When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer.
When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 6 is 0:
- If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high.
When IOPOE bit 6 is 1:
- If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high.
11-10IO5R/W0hSelects mode for AUXIO[8i+5].
0h = Output Mode:
When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5].
When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5].
1h = Input Mode:
When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer.
When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 5 is 0:
- If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high.
When IOPOE bit 5 is 1:
- If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high.
9-8IO4R/W0hSelects mode for AUXIO[8i+4].
0h = Output Mode:
When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4].
When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4].
1h = Input Mode:
When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer.
When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 4 is 0:
- If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high.
When IOPOE bit 4 is 1:
- If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high.
7-6IO3R/W0hSelects mode for AUXIO[8i+3].
0h = Output Mode:
When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3].
When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3].
1h = Input Mode:
When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer.
When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 3 is 0:
- If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high.
When IOPOE bit 3 is 1:
- If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high.
5-4IO2R/W0hSelect mode for AUXIO[8i+2].
0h = Output Mode:
When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2].
When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2].
1h = Input Mode:
When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer.
When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 2 is 0:
- If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high.
When IOPOE bit 2 is 1:
- If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high.
3-2IO1R/W0hSelect mode for AUXIO[8i+1].
0h = Output Mode:
When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1].
When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1].
1h = Input Mode:
When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer.
When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 1 is 0:
- If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high.
When IOPOE bit 1 is 1:
- If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high.
1-0IO0R/W0hSelect mode for AUXIO[8i+0].
0h = Output Mode:
When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0].
When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0].
1h = Input Mode:
When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer.
When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input.
2h = Open-Drain Mode:
When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
3h = Open-Source Mode:
When IOPOE bit 0 is 0:
- If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high.
When IOPOE bit 0 is 1:
- If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
- If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high.

20.8.2.2 GPIODIE Register (Offset = 4h) [Reset = 00000000h]

GPIODIE is shown in Figure 20-49 and described in Table 20-57.

Return to the Summary Table.

General Purpose Input Output Digital Input Enable
This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-49 GPIODIE Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-57 GPIODIE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n].
Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n].
You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN.
You must disable the digital input buffer for analog input or pins that float to avoid current leakage.

20.8.2.3 IOPOE Register (Offset = 8h) [Reset = 00000000h]

IOPOE is shown in Figure 20-50 and described in Table 20-58.

Return to the Summary Table.

Input Output Peripheral Output Enable
This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-50 IOPOE Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-58 IOPOE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].
Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT.

20.8.2.4 GPIODOUT Register (Offset = Ch) [Reset = 00000000h]

GPIODOUT is shown in Figure 20-51 and described in Table 20-59.

Return to the Summary Table.

General Purpose Input Output Data Out
The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-51 GPIODOUT Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-59 GPIODOUT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to set AUXIO[8i+n].
Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].
You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n].

20.8.2.5 GPIODIN Register (Offset = 10h) [Reset = 00000000h]

GPIODIN is shown in Figure 20-52 and described in Table 20-60.

Return to the Summary Table.

General Purpose Input Output Data In
This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth

Figure 20-52 GPIODIN Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR-0h
Table 20-60 GPIODIN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R0hBit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0.

20.8.2.6 GPIODOUTSET Register (Offset = 14h) [Reset = 00000000h]

GPIODOUTSET is shown in Figure 20-53 and described in Table 20-61.

Return to the Summary Table.

General Purpose Input Output Data Out Set
Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-53 GPIODOUTSET Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-61 GPIODOUTSET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to set GPIODOUT bit n.
Read value is 0.

20.8.2.7 GPIODOUTCLR Register (Offset = 18h) [Reset = 00000000h]

GPIODOUTCLR is shown in Figure 20-54 and described in Table 20-62.

Return to the Summary Table.

General Purpose Input Output Data Out Clear
Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-54 GPIODOUTCLR Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-62 GPIODOUTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to clear GPIODOUT bit n.
Read value is 0.

20.8.2.8 GPIODOUTTGL Register (Offset = 1Ch) [Reset = 00000000h]

GPIODOUTTGL is shown in Figure 20-55 and described in Table 20-63.

Return to the Summary Table.

General Purpose Input Output Data Out Toggle
Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-55 GPIODOUTTGL Register
313029282726252423222120191817161514131211109876543210
RESERVEDIO7_0
R-0hR/W-0h
Table 20-63 GPIODOUTTGL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0IO7_0R/W0hWrite 1 to bit index n in this bit vector to toggle GPIODOUT bit n.
Read value is 0.

20.8.2.9 IO0PSEL Register (Offset = 20h) [Reset = 00000000h]

IO0PSEL is shown in Figure 20-56 and described in Table 20-64.

Return to the Summary Table.

Input Output 0 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1.
To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-56 IO0PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-64 IO0PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.10 IO1PSEL Register (Offset = 24h) [Reset = 00000000h]

IO1PSEL is shown in Figure 20-57 and described in Table 20-65.

Return to the Summary Table.

Input Output 1 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1.
To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-57 IO1PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-65 IO1PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.11 IO2PSEL Register (Offset = 28h) [Reset = 00000000h]

IO2PSEL is shown in Figure 20-58 and described in Table 20-66.

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Input Output 2 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1.
To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-58 IO2PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-66 IO2PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.12 IO3PSEL Register (Offset = 2Ch) [Reset = 00000000h]

IO3PSEL is shown in Figure 20-59 and described in Table 20-67.

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Input Output 3 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1.
To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-59 IO3PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-67 IO3PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.13 IO4PSEL Register (Offset = 30h) [Reset = 00000000h]

IO4PSEL is shown in Figure 20-60 and described in Table 20-68.

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Input Output 4 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1.
To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-60 IO4PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-68 IO4PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.14 IO5PSEL Register (Offset = 34h) [Reset = 00000000h]

IO5PSEL is shown in Figure 20-61 and described in Table 20-69.

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Input Output 5 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1.
To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-61 IO5PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-69 IO5PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.15 IO6PSEL Register (Offset = 38h) [Reset = 00000000h]

IO6PSEL is shown in Figure 20-62 and described in Table 20-70.

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Input Output 6 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1.
To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-62 IO6PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-70 IO6PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.16 IO7PSEL Register (Offset = 3Ch) [Reset = 00000000h]

IO7PSEL is shown in Figure 20-63 and described in Table 20-71.

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Input Output 7 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1.
To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.

Figure 20-63 IO7PSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-71 IO7PSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG
1h = Peripheral output mux selects AUX_SPIM SCLK.
2h = Peripheral output mux selects AUX_SPIM MOSI.
3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.

20.8.2.17 IOMODEL Register (Offset = 40h) [Reset = 00000000h]

IOMODEL is shown in Figure 20-64 and described in Table 20-72.

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Input Output Mode Low
This is an alias register for IOMODE.IO0 thru IOMODE.IO3.

Figure 20-64 IOMODEL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDIO3IO2IO1IO0
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-72 IOMODEL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6IO3R/W0hSee IOMODE.IO3.
5-4IO2R/W0hSee IOMODE.IO2.
3-2IO1R/W0hSee IOMODE.IO1.
1-0IO0R/W0hSee IOMODE.IO0.

20.8.2.18 IOMODEH Register (Offset = 44h) [Reset = 00000000h]

IOMODEH is shown in Figure 20-65 and described in Table 20-73.

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Input Output Mode High
This is an alias register for IOMODE.IO4 thru IOMODE.IO7.

Figure 20-65 IOMODEH Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDIO7IO6IO5IO4
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-73 IOMODEH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-6IO7R/W0hSee IOMODE.IO7.
5-4IO6R/W0hSee IOMODE.IO6.
3-2IO5R/W0hSee IOMODE.IO5.
1-0IO4R/W0hSee IOMODE.IO4.