SWCU185G January   2018  – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  3. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  4. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  5. 4 Memory Map
    1. 4.1 Memory Map
  6. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  7. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  8. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  9. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  10. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  11. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  12. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  13. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  14. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  15. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  17. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  18. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  19. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  20. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  24. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

6.7.2 EVENT Registers

Table 6-14 lists the memory-mapped registers for the EVENT registers. All register offset addresses not listed in Table 6-14 should be considered as reserved locations and the register contents should not be modified.

Table 6-14 EVENT Registers
OffsetAcronymRegister NameSection
0hCPUIRQSEL0Output Selection for CPU Interrupt 0CPUIRQSEL0 Register (Offset = 0h) [Reset = 00000004h]
4hCPUIRQSEL1Output Selection for CPU Interrupt 1CPUIRQSEL1 Register (Offset = 4h) [Reset = 00000009h]
8hCPUIRQSEL2Output Selection for CPU Interrupt 2CPUIRQSEL2 Register (Offset = 8h) [Reset = 0000001Eh]
ChCPUIRQSEL3Output Selection for CPU Interrupt 3CPUIRQSEL3 Register (Offset = Ch) [Reset = 0000001Fh]
10hCPUIRQSEL4Output Selection for CPU Interrupt 4CPUIRQSEL4 Register (Offset = 10h) [Reset = 00000007h]
14hCPUIRQSEL5Output Selection for CPU Interrupt 5CPUIRQSEL5 Register (Offset = 14h) [Reset = 00000024h]
18hCPUIRQSEL6Output Selection for CPU Interrupt 6CPUIRQSEL6 Register (Offset = 18h) [Reset = 0000001Ch]
1ChCPUIRQSEL7Output Selection for CPU Interrupt 7CPUIRQSEL7 Register (Offset = 1Ch) [Reset = 00000022h]
20hCPUIRQSEL8Output Selection for CPU Interrupt 8CPUIRQSEL8 Register (Offset = 20h) [Reset = 00000023h]
24hCPUIRQSEL9Output Selection for CPU Interrupt 9CPUIRQSEL9 Register (Offset = 24h) [Reset = 0000001Bh]
28hCPUIRQSEL10Output Selection for CPU Interrupt 10CPUIRQSEL10 Register (Offset = 28h) [Reset = 0000001Ah]
2ChCPUIRQSEL11Output Selection for CPU Interrupt 11CPUIRQSEL11 Register (Offset = 2Ch) [Reset = 00000019h]
30hCPUIRQSEL12Output Selection for CPU Interrupt 12CPUIRQSEL12 Register (Offset = 30h) [Reset = 00000008h]
34hCPUIRQSEL13Output Selection for CPU Interrupt 13CPUIRQSEL13 Register (Offset = 34h) [Reset = 0000001Dh]
38hCPUIRQSEL14Output Selection for CPU Interrupt 14CPUIRQSEL14 Register (Offset = 38h) [Reset = 00000018h]
3ChCPUIRQSEL15Output Selection for CPU Interrupt 15CPUIRQSEL15 Register (Offset = 3Ch) [Reset = 00000010h]
40hCPUIRQSEL16Output Selection for CPU Interrupt 16CPUIRQSEL16 Register (Offset = 40h) [Reset = 00000011h]
44hCPUIRQSEL17Output Selection for CPU Interrupt 17CPUIRQSEL17 Register (Offset = 44h) [Reset = 00000012h]
48hCPUIRQSEL18Output Selection for CPU Interrupt 18CPUIRQSEL18 Register (Offset = 48h) [Reset = 00000013h]
4ChCPUIRQSEL19Output Selection for CPU Interrupt 19CPUIRQSEL19 Register (Offset = 4Ch) [Reset = 0000000Ch]
50hCPUIRQSEL20Output Selection for CPU Interrupt 20CPUIRQSEL20 Register (Offset = 50h) [Reset = 0000000Dh]
54hCPUIRQSEL21Output Selection for CPU Interrupt 21CPUIRQSEL21 Register (Offset = 54h) [Reset = 0000000Eh]
58hCPUIRQSEL22Output Selection for CPU Interrupt 22CPUIRQSEL22 Register (Offset = 58h) [Reset = 0000000Fh]
5ChCPUIRQSEL23Output Selection for CPU Interrupt 23CPUIRQSEL23 Register (Offset = 5Ch) [Reset = 0000005Dh]
60hCPUIRQSEL24Output Selection for CPU Interrupt 24CPUIRQSEL24 Register (Offset = 60h) [Reset = 00000027h]
64hCPUIRQSEL25Output Selection for CPU Interrupt 25CPUIRQSEL25 Register (Offset = 64h) [Reset = 00000026h]
68hCPUIRQSEL26Output Selection for CPU Interrupt 26CPUIRQSEL26 Register (Offset = 68h) [Reset = 00000015h]
6ChCPUIRQSEL27Output Selection for CPU Interrupt 27CPUIRQSEL27 Register (Offset = 6Ch) [Reset = 00000064h]
70hCPUIRQSEL28Output Selection for CPU Interrupt 28CPUIRQSEL28 Register (Offset = 70h) [Reset = 0000000Bh]
74hCPUIRQSEL29Output Selection for CPU Interrupt 29CPUIRQSEL29 Register (Offset = 74h) [Reset = 00000001h]
78hCPUIRQSEL30Output Selection for CPU Interrupt 30CPUIRQSEL30 Register (Offset = 78h) [Reset = 00000000h]
7ChCPUIRQSEL31Output Selection for CPU Interrupt 31CPUIRQSEL31 Register (Offset = 7Ch) [Reset = 0000006Ah]
80hCPUIRQSEL32Output Selection for CPU Interrupt 32CPUIRQSEL32 Register (Offset = 80h) [Reset = 00000073h]
84hCPUIRQSEL33Output Selection for CPU Interrupt 33CPUIRQSEL33 Register (Offset = 84h) [Reset = 00000068h]
88hCPUIRQSEL34Output Selection for CPU Interrupt 34CPUIRQSEL34 Register (Offset = 88h) [Reset = 00000006h]
8ChCPUIRQSEL35Output Selection for CPU Interrupt 35CPUIRQSEL35 Register (Offset = 8Ch) [Reset = 00000038h]
90hCPUIRQSEL36Output Selection for CPU Interrupt 36CPUIRQSEL36 Register (Offset = 90h) [Reset = 00000025h]
94hCPUIRQSEL37Output Selection for CPU Interrupt 37CPUIRQSEL37 Register (Offset = 94h) [Reset = 00000005h]
100hRFCSEL0Output Selection for RFC Event 0RFCSEL0 Register (Offset = 100h) [Reset = 0000003Dh]
104hRFCSEL1Output Selection for RFC Event 1RFCSEL1 Register (Offset = 104h) [Reset = 0000003Eh]
108hRFCSEL2Output Selection for RFC Event 2RFCSEL2 Register (Offset = 108h) [Reset = 0000003Fh]
10ChRFCSEL3Output Selection for RFC Event 3RFCSEL3 Register (Offset = 10Ch) [Reset = 00000040h]
110hRFCSEL4Output Selection for RFC Event 4RFCSEL4 Register (Offset = 110h) [Reset = 00000041h]
114hRFCSEL5Output Selection for RFC Event 5RFCSEL5 Register (Offset = 114h) [Reset = 00000042h]
118hRFCSEL6Output Selection for RFC Event 6RFCSEL6 Register (Offset = 118h) [Reset = 00000043h]
11ChRFCSEL7Output Selection for RFC Event 7RFCSEL7 Register (Offset = 11Ch) [Reset = 00000044h]
120hRFCSEL8Output Selection for RFC Event 8RFCSEL8 Register (Offset = 120h) [Reset = 00000077h]
124hRFCSEL9Output Selection for RFC Event 9RFCSEL9 Register (Offset = 124h) [Reset = 00000002h]
200hGPT0ACAPTSELOutput Selection for GPT0 0GPT0ACAPTSEL Register (Offset = 200h) [Reset = 00000055h]
204hGPT0BCAPTSELOutput Selection for GPT0 1GPT0BCAPTSEL Register (Offset = 204h) [Reset = 00000056h]
300hGPT1ACAPTSELOutput Selection for GPT1 0GPT1ACAPTSEL Register (Offset = 300h) [Reset = 00000057h]
304hGPT1BCAPTSELOutput Selection for GPT1 1GPT1BCAPTSEL Register (Offset = 304h) [Reset = 00000058h]
400hGPT2ACAPTSELOutput Selection for GPT2 0GPT2ACAPTSEL Register (Offset = 400h) [Reset = 00000059h]
404hGPT2BCAPTSELOutput Selection for GPT2 1GPT2BCAPTSEL Register (Offset = 404h) [Reset = 0000005Ah]
508hUDMACH1SSELOutput Selection for DMA Channel 1 SREQUDMACH1SSEL Register (Offset = 508h) [Reset = 00000031h]
50ChUDMACH1BSELOutput Selection for DMA Channel 1 REQUDMACH1BSEL Register (Offset = 50Ch) [Reset = 00000030h]
510hUDMACH2SSELOutput Selection for DMA Channel 2 SREQUDMACH2SSEL Register (Offset = 510h) [Reset = 00000033h]
514hUDMACH2BSELOutput Selection for DMA Channel 2 REQUDMACH2BSEL Register (Offset = 514h) [Reset = 00000032h]
518hUDMACH3SSELOutput Selection for DMA Channel 3 SREQUDMACH3SSEL Register (Offset = 518h) [Reset = 00000029h]
51ChUDMACH3BSELOutput Selection for DMA Channel 3 REQUDMACH3BSEL Register (Offset = 51Ch) [Reset = 00000028h]
520hUDMACH4SSELOutput Selection for DMA Channel 4 SREQUDMACH4SSEL Register (Offset = 520h) [Reset = 0000002Bh]
524hUDMACH4BSELOutput Selection for DMA Channel 4 REQUDMACH4BSEL Register (Offset = 524h) [Reset = 0000002Ah]
528hUDMACH5SSELOutput Selection for DMA Channel 5 SREQUDMACH5SSEL Register (Offset = 528h) [Reset = 00000035h]
52ChUDMACH5BSELOutput Selection for DMA Channel 5 REQUDMACH5BSEL Register (Offset = 52Ch) [Reset = 00000034h]
530hUDMACH6SSELOutput Selection for DMA Channel 6 SREQUDMACH6SSEL Register (Offset = 530h) [Reset = 00000037h]
534hUDMACH6BSELOutput Selection for DMA Channel 6 REQUDMACH6BSEL Register (Offset = 534h) [Reset = 00000036h]
538hUDMACH7SSELOutput Selection for DMA Channel 7 SREQUDMACH7SSEL Register (Offset = 538h) [Reset = 00000075h]
53ChUDMACH7BSELOutput Selection for DMA Channel 7 REQUDMACH7BSEL Register (Offset = 53Ch) [Reset = 00000076h]
540hUDMACH8SSELOutput Selection for DMA Channel 8 SREQUDMACH8SSEL Register (Offset = 540h) [Reset = 00000074h]
544hUDMACH8BSELOutput Selection for DMA Channel 8 REQUDMACH8BSEL Register (Offset = 544h) [Reset = 00000074h]
548hUDMACH9SSELOutput Selection for DMA Channel 9 SREQUDMACH9SSEL Register (Offset = 548h) [Reset = 00000045h]
54ChUDMACH9BSELOutput Selection for DMA Channel 9 REQUDMACH9BSEL Register (Offset = 54Ch) [Reset = 0000004Dh]
550hUDMACH10SSELOutput Selection for DMA Channel 10 SREQUDMACH10SSEL Register (Offset = 550h) [Reset = 00000046h]
554hUDMACH10BSELOutput Selection for DMA Channel 10 REQUDMACH10BSEL Register (Offset = 554h) [Reset = 0000004Eh]
558hUDMACH11SSELOutput Selection for DMA Channel 11 SREQUDMACH11SSEL Register (Offset = 558h) [Reset = 00000047h]
55ChUDMACH11BSELOutput Selection for DMA Channel 11 REQUDMACH11BSEL Register (Offset = 55Ch) [Reset = 0000004Fh]
560hUDMACH12SSELOutput Selection for DMA Channel 12 SREQUDMACH12SSEL Register (Offset = 560h) [Reset = 00000048h]
564hUDMACH12BSELOutput Selection for DMA Channel 12 REQUDMACH12BSEL Register (Offset = 564h) [Reset = 00000050h]
56ChUDMACH13BSELOutput Selection for DMA Channel 13 REQUDMACH13BSEL Register (Offset = 56Ch) [Reset = 00000003h]
574hUDMACH14BSELOutput Selection for DMA Channel 14 REQUDMACH14BSEL Register (Offset = 574h) [Reset = 00000001h]
57ChUDMACH15BSELOutput Selection for DMA Channel 15 REQUDMACH15BSEL Register (Offset = 57Ch) [Reset = 00000007h]
580hUDMACH16SSELOutput Selection for DMA Channel 16 SREQUDMACH16SSEL Register (Offset = 580h) [Reset = 0000002Dh]
584hUDMACH16BSELOutput Selection for DMA Channel 16 REQUDMACH16BSEL Register (Offset = 584h) [Reset = 0000002Ch]
588hUDMACH17SSELOutput Selection for DMA Channel 17 SREQUDMACH17SSEL Register (Offset = 588h) [Reset = 0000002Fh]
58ChUDMACH17BSELOutput Selection for DMA Channel 17 REQUDMACH17BSEL Register (Offset = 58Ch) [Reset = 0000002Eh]
5A8hUDMACH21SSELOutput Selection for DMA Channel 21 SREQUDMACH21SSEL Register (Offset = 5A8h) [Reset = 00000064h]
5AChUDMACH21BSELOutput Selection for DMA Channel 21 REQUDMACH21BSEL Register (Offset = 5ACh) [Reset = 00000064h]
5B0hUDMACH22SSELOutput Selection for DMA Channel 22 SREQUDMACH22SSEL Register (Offset = 5B0h) [Reset = 00000065h]
5B4hUDMACH22BSELOutput Selection for DMA Channel 22 REQUDMACH22BSEL Register (Offset = 5B4h) [Reset = 00000065h]
5B8hUDMACH23SSELOutput Selection for DMA Channel 23 SREQUDMACH23SSEL Register (Offset = 5B8h) [Reset = 00000066h]
5BChUDMACH23BSELOutput Selection for DMA Channel 23 REQUDMACH23BSEL Register (Offset = 5BCh) [Reset = 00000066h]
5C0hUDMACH24SSELOutput Selection for DMA Channel 24 SREQUDMACH24SSEL Register (Offset = 5C0h) [Reset = 00000067h]
5C4hUDMACH24BSELOutput Selection for DMA Channel 24 REQUDMACH24BSEL Register (Offset = 5C4h) [Reset = 00000067h]
600hGPT3ACAPTSELOutput Selection for GPT3 0GPT3ACAPTSEL Register (Offset = 600h) [Reset = 0000005Bh]
604hGPT3BCAPTSELOutput Selection for GPT3 1GPT3BCAPTSEL Register (Offset = 604h) [Reset = 0000005Ch]
700hAUXSEL0Output Selection for AUX Subscriber 0AUXSEL0 Register (Offset = 700h) [Reset = 00000010h]
800hCM3NMISEL0Output Selection for NMI Subscriber 0CM3NMISEL0 Register (Offset = 800h) [Reset = 00000063h]
900hI2SSTMPSEL0Output Selection for I2S Subscriber 0I2SSTMPSEL0 Register (Offset = 900h) [Reset = 0000005Fh]
A00hFRZSEL0Output Selection for FRZ SubscriberFRZSEL0 Register (Offset = A00h) [Reset = 00000078h]
F00hSWEVSet or Clear Software EventsSWEV Register (Offset = F00h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 6-15 shows the codes that are used for access types in this section.

Table 6-15 EVENT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.7.2.1 CPUIRQSEL0 Register (Offset = 0h) [Reset = 00000004h]

CPUIRQSEL0 is shown in Figure 6-10 and described in Table 6-16.

Return to the Summary Table.

Output Selection for CPU Interrupt 0

Figure 6-10 CPUIRQSEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-4h
Table 6-16 CPUIRQSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR4hRead only selection value
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings

6.7.2.2 CPUIRQSEL1 Register (Offset = 4h) [Reset = 00000009h]

CPUIRQSEL1 is shown in Figure 6-11 and described in Table 6-17.

Return to the Summary Table.

Output Selection for CPU Interrupt 1

Figure 6-11 CPUIRQSEL1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-9h
Table 6-17 CPUIRQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR9hRead only selection value
9h = Interrupt event from I2C

6.7.2.3 CPUIRQSEL2 Register (Offset = 8h) [Reset = 0000001Eh]

CPUIRQSEL2 is shown in Figure 6-12 and described in Table 6-18.

Return to the Summary Table.

Output Selection for CPU Interrupt 2

Figure 6-12 CPUIRQSEL2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Eh
Table 6-18 CPUIRQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1EhRead only selection value
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event

6.7.2.4 CPUIRQSEL3 Register (Offset = Ch) [Reset = 0000001Fh]

CPUIRQSEL3 is shown in Figure 6-13 and described in Table 6-19.

Return to the Summary Table.

Output Selection for CPU Interrupt 3

Figure 6-13 CPUIRQSEL3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Fh
Table 6-19 CPUIRQSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1FhRead only selection value
1Fh = PKA Interrupt event

6.7.2.5 CPUIRQSEL4 Register (Offset = 10h) [Reset = 00000007h]

CPUIRQSEL4 is shown in Figure 6-14 and described in Table 6-20.

Return to the Summary Table.

Output Selection for CPU Interrupt 4

Figure 6-14 CPUIRQSEL4 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-7h
Table 6-20 CPUIRQSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR7hRead only selection value
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting

6.7.2.6 CPUIRQSEL5 Register (Offset = 14h) [Reset = 00000024h]

CPUIRQSEL5 is shown in Figure 6-15 and described in Table 6-21.

Return to the Summary Table.

Output Selection for CPU Interrupt 5

Figure 6-15 CPUIRQSEL5 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-24h
Table 6-21 CPUIRQSEL5 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR24hRead only selection value
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS

6.7.2.7 CPUIRQSEL6 Register (Offset = 18h) [Reset = 0000001Ch]

CPUIRQSEL6 is shown in Figure 6-16 and described in Table 6-22.

Return to the Summary Table.

Output Selection for CPU Interrupt 6

Figure 6-16 CPUIRQSEL6 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Ch
Table 6-22 CPUIRQSEL6 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1ChRead only selection value
1Ch = AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL

6.7.2.8 CPUIRQSEL7 Register (Offset = 1Ch) [Reset = 00000022h]

CPUIRQSEL7 is shown in Figure 6-17 and described in Table 6-23.

Return to the Summary Table.

Output Selection for CPU Interrupt 7

Figure 6-17 CPUIRQSEL7 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-22h
Table 6-23 CPUIRQSEL7 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR22hRead only selection value
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS

6.7.2.9 CPUIRQSEL8 Register (Offset = 20h) [Reset = 00000023h]

CPUIRQSEL8 is shown in Figure 6-18 and described in Table 6-24.

Return to the Summary Table.

Output Selection for CPU Interrupt 8

Figure 6-18 CPUIRQSEL8 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-23h
Table 6-24 CPUIRQSEL8 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR23hRead only selection value
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS

6.7.2.10 CPUIRQSEL9 Register (Offset = 24h) [Reset = 0000001Bh]

CPUIRQSEL9 is shown in Figure 6-19 and described in Table 6-25.

Return to the Summary Table.

Output Selection for CPU Interrupt 9

Figure 6-19 CPUIRQSEL9 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Bh
Table 6-25 CPUIRQSEL9 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1BhRead only selection value
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event

6.7.2.11 CPUIRQSEL10 Register (Offset = 28h) [Reset = 0000001Ah]

CPUIRQSEL10 is shown in Figure 6-20 and described in Table 6-26.

Return to the Summary Table.

Output Selection for CPU Interrupt 10

Figure 6-20 CPUIRQSEL10 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Ah
Table 6-26 CPUIRQSEL10 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1AhRead only selection value
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG

6.7.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [Reset = 00000019h]

CPUIRQSEL11 is shown in Figure 6-21 and described in Table 6-27.

Return to the Summary Table.

Output Selection for CPU Interrupt 11

Figure 6-21 CPUIRQSEL11 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-19h
Table 6-27 CPUIRQSEL11 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR19hRead only selection value
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG

6.7.2.13 CPUIRQSEL12 Register (Offset = 30h) [Reset = 00000008h]

CPUIRQSEL12 is shown in Figure 6-22 and described in Table 6-28.

Return to the Summary Table.

Output Selection for CPU Interrupt 12

Figure 6-22 CPUIRQSEL12 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-8h
Table 6-28 CPUIRQSEL12 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR8hRead only selection value
8h = Interrupt event from I2S

6.7.2.14 CPUIRQSEL13 Register (Offset = 34h) [Reset = 0000001Dh]

CPUIRQSEL13 is shown in Figure 6-23 and described in Table 6-29.

Return to the Summary Table.

Output Selection for CPU Interrupt 13

Figure 6-23 CPUIRQSEL13 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1Dh
Table 6-29 CPUIRQSEL13 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1DhRead only selection value
1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL

6.7.2.15 CPUIRQSEL14 Register (Offset = 38h) [Reset = 00000018h]

CPUIRQSEL14 is shown in Figure 6-24 and described in Table 6-30.

Return to the Summary Table.

Output Selection for CPU Interrupt 14

Figure 6-24 CPUIRQSEL14 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-18h
Table 6-30 CPUIRQSEL14 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR18hRead only selection value
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN

6.7.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [Reset = 00000010h]

CPUIRQSEL15 is shown in Figure 6-25 and described in Table 6-31.

Return to the Summary Table.

Output Selection for CPU Interrupt 15

Figure 6-25 CPUIRQSEL15 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-10h
Table 6-31 CPUIRQSEL15 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR10hRead only selection value
10h = GPT0A interrupt event, controlled by GPT0:TAMR

6.7.2.17 CPUIRQSEL16 Register (Offset = 40h) [Reset = 00000011h]

CPUIRQSEL16 is shown in Figure 6-26 and described in Table 6-32.

Return to the Summary Table.

Output Selection for CPU Interrupt 16

Figure 6-26 CPUIRQSEL16 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-11h
Table 6-32 CPUIRQSEL16 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR11hRead only selection value
11h = GPT0B interrupt event, controlled by GPT0:TBMR

6.7.2.18 CPUIRQSEL17 Register (Offset = 44h) [Reset = 00000012h]

CPUIRQSEL17 is shown in Figure 6-27 and described in Table 6-33.

Return to the Summary Table.

Output Selection for CPU Interrupt 17

Figure 6-27 CPUIRQSEL17 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-12h
Table 6-33 CPUIRQSEL17 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR12hRead only selection value
12h = GPT1A interrupt event, controlled by GPT1:TAMR

6.7.2.19 CPUIRQSEL18 Register (Offset = 48h) [Reset = 00000013h]

CPUIRQSEL18 is shown in Figure 6-28 and described in Table 6-34.

Return to the Summary Table.

Output Selection for CPU Interrupt 18

Figure 6-28 CPUIRQSEL18 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-13h
Table 6-34 CPUIRQSEL18 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR13hRead only selection value
13h = GPT1B interrupt event, controlled by GPT1:TBMR

6.7.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [Reset = 0000000Ch]

CPUIRQSEL19 is shown in Figure 6-29 and described in Table 6-35.

Return to the Summary Table.

Output Selection for CPU Interrupt 19

Figure 6-29 CPUIRQSEL19 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-Ch
Table 6-35 CPUIRQSEL19 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVRChRead only selection value
Ch = GPT2A interrupt event, controlled by GPT2:TAMR

6.7.2.21 CPUIRQSEL20 Register (Offset = 50h) [Reset = 0000000Dh]

CPUIRQSEL20 is shown in Figure 6-30 and described in Table 6-36.

Return to the Summary Table.

Output Selection for CPU Interrupt 20

Figure 6-30 CPUIRQSEL20 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-Dh
Table 6-36 CPUIRQSEL20 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVRDhRead only selection value
Dh = GPT2B interrupt event, controlled by GPT2:TBMR

6.7.2.22 CPUIRQSEL21 Register (Offset = 54h) [Reset = 0000000Eh]

CPUIRQSEL21 is shown in Figure 6-31 and described in Table 6-37.

Return to the Summary Table.

Output Selection for CPU Interrupt 21

Figure 6-31 CPUIRQSEL21 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-Eh
Table 6-37 CPUIRQSEL21 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVREhRead only selection value
Eh = GPT3A interrupt event, controlled by GPT3:TAMR

6.7.2.23 CPUIRQSEL22 Register (Offset = 58h) [Reset = 0000000Fh]

CPUIRQSEL22 is shown in Figure 6-32 and described in Table 6-38.

Return to the Summary Table.

Output Selection for CPU Interrupt 22

Figure 6-32 CPUIRQSEL22 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-Fh
Table 6-38 CPUIRQSEL22 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVRFhRead only selection value
Fh = GPT3B interrupt event, controlled by GPT3:TBMR

6.7.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [Reset = 0000005Dh]

CPUIRQSEL23 is shown in Figure 6-33 and described in Table 6-39.

Return to the Summary Table.

Output Selection for CPU Interrupt 23

Figure 6-33 CPUIRQSEL23 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-5Dh
Table 6-39 CPUIRQSEL23 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR5DhRead only selection value
5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL

6.7.2.25 CPUIRQSEL24 Register (Offset = 60h) [Reset = 00000027h]

CPUIRQSEL24 is shown in Figure 6-34 and described in Table 6-40.

Return to the Summary Table.

Output Selection for CPU Interrupt 24

Figure 6-34 CPUIRQSEL24 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-27h
Table 6-40 CPUIRQSEL24 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR27hRead only selection value
27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE

6.7.2.26 CPUIRQSEL25 Register (Offset = 64h) [Reset = 00000026h]

CPUIRQSEL25 is shown in Figure 6-35 and described in Table 6-41.

Return to the Summary Table.

Output Selection for CPU Interrupt 25

Figure 6-35 CPUIRQSEL25 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-26h
Table 6-41 CPUIRQSEL25 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR26hRead only selection value
26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS

6.7.2.27 CPUIRQSEL26 Register (Offset = 68h) [Reset = 00000015h]

CPUIRQSEL26 is shown in Figure 6-36 and described in Table 6-42.

Return to the Summary Table.

Output Selection for CPU Interrupt 26

Figure 6-36 CPUIRQSEL26 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-15h
Table 6-42 CPUIRQSEL26 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR15hRead only selection value
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT

6.7.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [Reset = 00000064h]

CPUIRQSEL27 is shown in Figure 6-37 and described in Table 6-43.

Return to the Summary Table.

Output Selection for CPU Interrupt 27

Figure 6-37 CPUIRQSEL27 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-64h
Table 6-43 CPUIRQSEL27 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR64hRead only selection value
64h = Software event 0, triggered by SWEV.SWEV0

6.7.2.29 CPUIRQSEL28 Register (Offset = 70h) [Reset = 0000000Bh]

CPUIRQSEL28 is shown in Figure 6-38 and described in Table 6-44.

Return to the Summary Table.

Output Selection for CPU Interrupt 28

Figure 6-38 CPUIRQSEL28 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-Bh
Table 6-44 CPUIRQSEL28 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVRBhRead only selection value
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS

6.7.2.30 CPUIRQSEL29 Register (Offset = 74h) [Reset = 00000001h]

CPUIRQSEL29 is shown in Figure 6-39 and described in Table 6-45.

Return to the Summary Table.

Output Selection for CPU Interrupt 29

Figure 6-39 CPUIRQSEL29 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-1h
Table 6-45 CPUIRQSEL29 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR1hRead only selection value
1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV

6.7.2.31 CPUIRQSEL30 Register (Offset = 78h) [Reset = 00000000h]

CPUIRQSEL30 is shown in Figure 6-40 and described in Table 6-46.

Return to the Summary Table.

Output Selection for CPU Interrupt 30

Figure 6-40 CPUIRQSEL30 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-0h
Table 6-46 CPUIRQSEL30 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W0hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
8h = Interrupt event from I2S
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
14h = DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ
16h = DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
5Eh = CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [Reset = 0000006Ah]

CPUIRQSEL31 is shown in Figure 6-41 and described in Table 6-47.

Return to the Summary Table.

Output Selection for CPU Interrupt 31

Figure 6-41 CPUIRQSEL31 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-6Ah
Table 6-47 CPUIRQSEL31 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR6AhRead only selection value
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA

6.7.2.33 CPUIRQSEL32 Register (Offset = 80h) [Reset = 00000073h]

CPUIRQSEL32 is shown in Figure 6-42 and described in Table 6-48.

Return to the Summary Table.

Output Selection for CPU Interrupt 32

Figure 6-42 CPUIRQSEL32 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-73h
Table 6-48 CPUIRQSEL32 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR73hRead only selection value
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS

6.7.2.34 CPUIRQSEL33 Register (Offset = 84h) [Reset = 00000068h]

CPUIRQSEL33 is shown in Figure 6-43 and described in Table 6-49.

Return to the Summary Table.

Output Selection for CPU Interrupt 33

Figure 6-43 CPUIRQSEL33 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-68h
Table 6-49 CPUIRQSEL33 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR68hRead only selection value
68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN

6.7.2.35 CPUIRQSEL34 Register (Offset = 88h) [Reset = 00000006h]

CPUIRQSEL34 is shown in Figure 6-44 and described in Table 6-50.

Return to the Summary Table.

Output Selection for CPU Interrupt 34

Figure 6-44 CPUIRQSEL34 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-6h
Table 6-50 CPUIRQSEL34 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR6hRead only selection value
6h = Combined event from Oscillator control

6.7.2.36 CPUIRQSEL35 Register (Offset = 8Ch) [Reset = 00000038h]

CPUIRQSEL35 is shown in Figure 6-45 and described in Table 6-51.

Return to the Summary Table.

Output Selection for CPU Interrupt 35

Figure 6-45 CPUIRQSEL35 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-38h
Table 6-51 CPUIRQSEL35 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR38hRead only selection value
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0

6.7.2.37 CPUIRQSEL36 Register (Offset = 90h) [Reset = 00000025h]

CPUIRQSEL36 is shown in Figure 6-46 and described in Table 6-52.

Return to the Summary Table.

Output Selection for CPU Interrupt 36

Figure 6-46 CPUIRQSEL36 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-25h
Table 6-52 CPUIRQSEL36 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR25hRead only selection value
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS

6.7.2.38 CPUIRQSEL37 Register (Offset = 94h) [Reset = 00000005h]

CPUIRQSEL37 is shown in Figure 6-47 and described in Table 6-53.

Return to the Summary Table.

Output Selection for CPU Interrupt 37

Figure 6-47 CPUIRQSEL37 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-5h
Table 6-53 CPUIRQSEL37 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR5hRead only selection value
5h = Combined event from battery monitor

6.7.2.39 RFCSEL0 Register (Offset = 100h) [Reset = 0000003Dh]

RFCSEL0 is shown in Figure 6-48 and described in Table 6-54.

Return to the Summary Table.

Output Selection for RFC Event 0

Figure 6-48 RFCSEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-3Dh
Table 6-54 RFCSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR3DhRead only selection value
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT

6.7.2.40 RFCSEL1 Register (Offset = 104h) [Reset = 0000003Eh]

RFCSEL1 is shown in Figure 6-49 and described in Table 6-55.

Return to the Summary Table.

Output Selection for RFC Event 1

Figure 6-49 RFCSEL1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-3Eh
Table 6-55 RFCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR3EhRead only selection value
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT

6.7.2.41 RFCSEL2 Register (Offset = 108h) [Reset = 0000003Fh]

RFCSEL2 is shown in Figure 6-50 and described in Table 6-56.

Return to the Summary Table.

Output Selection for RFC Event 2

Figure 6-50 RFCSEL2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-3Fh
Table 6-56 RFCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR3FhRead only selection value
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT

6.7.2.42 RFCSEL3 Register (Offset = 10Ch) [Reset = 00000040h]

RFCSEL3 is shown in Figure 6-51 and described in Table 6-57.

Return to the Summary Table.

Output Selection for RFC Event 3

Figure 6-51 RFCSEL3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-40h
Table 6-57 RFCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR40hRead only selection value
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT

6.7.2.43 RFCSEL4 Register (Offset = 110h) [Reset = 00000041h]

RFCSEL4 is shown in Figure 6-52 and described in Table 6-58.

Return to the Summary Table.

Output Selection for RFC Event 4

Figure 6-52 RFCSEL4 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-41h
Table 6-58 RFCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR41hRead only selection value
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT

6.7.2.44 RFCSEL5 Register (Offset = 114h) [Reset = 00000042h]

RFCSEL5 is shown in Figure 6-53 and described in Table 6-59.

Return to the Summary Table.

Output Selection for RFC Event 5

Figure 6-53 RFCSEL5 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-42h
Table 6-59 RFCSEL5 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR42hRead only selection value
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT

6.7.2.45 RFCSEL6 Register (Offset = 118h) [Reset = 00000043h]

RFCSEL6 is shown in Figure 6-54 and described in Table 6-60.

Return to the Summary Table.

Output Selection for RFC Event 6

Figure 6-54 RFCSEL6 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-43h
Table 6-60 RFCSEL6 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR43hRead only selection value
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT

6.7.2.46 RFCSEL7 Register (Offset = 11Ch) [Reset = 00000044h]

RFCSEL7 is shown in Figure 6-55 and described in Table 6-61.

Return to the Summary Table.

Output Selection for RFC Event 7

Figure 6-55 RFCSEL7 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-44h
Table 6-61 RFCSEL7 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR44hRead only selection value
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT

6.7.2.47 RFCSEL8 Register (Offset = 120h) [Reset = 00000077h]

RFCSEL8 is shown in Figure 6-56 and described in Table 6-62.

Return to the Summary Table.

Output Selection for RFC Event 8

Figure 6-56 RFCSEL8 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-77h
Table 6-62 RFCSEL8 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR77hRead only selection value
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN

6.7.2.48 RFCSEL9 Register (Offset = 124h) [Reset = 00000002h]

RFCSEL9 is shown in Figure 6-57 and described in Table 6-63.

Return to the Summary Table.

Output Selection for RFC Event 9

Figure 6-57 RFCSEL9 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-2h
Table 6-63 RFCSEL9 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W2hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
8h = Interrupt event from I2S
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL
64h = Software event 0, triggered by SWEV.SWEV0
65h = Software event 1, triggered by SWEV.SWEV1
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
79h = Always asserted

6.7.2.49 GPT0ACAPTSEL Register (Offset = 200h) [Reset = 00000055h]

GPT0ACAPTSEL is shown in Figure 6-58 and described in Table 6-64.

Return to the Summary Table.

Output Selection for GPT0 0

Figure 6-58 GPT0ACAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-55h
Table 6-64 GPT0ACAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W55hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.50 GPT0BCAPTSEL Register (Offset = 204h) [Reset = 00000056h]

GPT0BCAPTSEL is shown in Figure 6-59 and described in Table 6-65.

Return to the Summary Table.

Output Selection for GPT0 1

Figure 6-59 GPT0BCAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-56h
Table 6-65 GPT0BCAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W56hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.51 GPT1ACAPTSEL Register (Offset = 300h) [Reset = 00000057h]

GPT1ACAPTSEL is shown in Figure 6-60 and described in Table 6-66.

Return to the Summary Table.

Output Selection for GPT1 0

Figure 6-60 GPT1ACAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-57h
Table 6-66 GPT1ACAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W57hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.52 GPT1BCAPTSEL Register (Offset = 304h) [Reset = 00000058h]

GPT1BCAPTSEL is shown in Figure 6-61 and described in Table 6-67.

Return to the Summary Table.

Output Selection for GPT1 1

Figure 6-61 GPT1BCAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-58h
Table 6-67 GPT1BCAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W58hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.53 GPT2ACAPTSEL Register (Offset = 400h) [Reset = 00000059h]

GPT2ACAPTSEL is shown in Figure 6-62 and described in Table 6-68.

Return to the Summary Table.

Output Selection for GPT2 0

Figure 6-62 GPT2ACAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-59h
Table 6-68 GPT2ACAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W59hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.54 GPT2BCAPTSEL Register (Offset = 404h) [Reset = 0000005Ah]

GPT2BCAPTSEL is shown in Figure 6-63 and described in Table 6-69.

Return to the Summary Table.

Output Selection for GPT2 1

Figure 6-63 GPT2BCAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-5Ah
Table 6-69 GPT2BCAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W5AhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.55 UDMACH1SSEL Register (Offset = 508h) [Reset = 00000031h]

UDMACH1SSEL is shown in Figure 6-64 and described in Table 6-70.

Return to the Summary Table.

Output Selection for DMA Channel 1 SREQ

Figure 6-64 UDMACH1SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-31h
Table 6-70 UDMACH1SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR31hRead only selection value
31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE

6.7.2.56 UDMACH1BSEL Register (Offset = 50Ch) [Reset = 00000030h]

UDMACH1BSEL is shown in Figure 6-65 and described in Table 6-71.

Return to the Summary Table.

Output Selection for DMA Channel 1 REQ

Figure 6-65 UDMACH1BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-30h
Table 6-71 UDMACH1BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR30hRead only selection value
30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE

6.7.2.57 UDMACH2SSEL Register (Offset = 510h) [Reset = 00000033h]

UDMACH2SSEL is shown in Figure 6-66 and described in Table 6-72.

Return to the Summary Table.

Output Selection for DMA Channel 2 SREQ

Figure 6-66 UDMACH2SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-33h
Table 6-72 UDMACH2SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR33hRead only selection value
33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE

6.7.2.58 UDMACH2BSEL Register (Offset = 514h) [Reset = 00000032h]

UDMACH2BSEL is shown in Figure 6-67 and described in Table 6-73.

Return to the Summary Table.

Output Selection for DMA Channel 2 REQ

Figure 6-67 UDMACH2BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-32h
Table 6-73 UDMACH2BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR32hRead only selection value
32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE

6.7.2.59 UDMACH3SSEL Register (Offset = 518h) [Reset = 00000029h]

UDMACH3SSEL is shown in Figure 6-68 and described in Table 6-74.

Return to the Summary Table.

Output Selection for DMA Channel 3 SREQ

Figure 6-68 UDMACH3SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-29h
Table 6-74 UDMACH3SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR29hRead only selection value
29h = SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE

6.7.2.60 UDMACH3BSEL Register (Offset = 51Ch) [Reset = 00000028h]

UDMACH3BSEL is shown in Figure 6-69 and described in Table 6-75.

Return to the Summary Table.

Output Selection for DMA Channel 3 REQ

Figure 6-69 UDMACH3BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-28h
Table 6-75 UDMACH3BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR28hRead only selection value
28h = SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE

6.7.2.61 UDMACH4SSEL Register (Offset = 520h) [Reset = 0000002Bh]

UDMACH4SSEL is shown in Figure 6-70 and described in Table 6-76.

Return to the Summary Table.

Output Selection for DMA Channel 4 SREQ

Figure 6-70 UDMACH4SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Bh
Table 6-76 UDMACH4SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2BhRead only selection value
2Bh = SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE

6.7.2.62 UDMACH4BSEL Register (Offset = 524h) [Reset = 0000002Ah]

UDMACH4BSEL is shown in Figure 6-71 and described in Table 6-77.

Return to the Summary Table.

Output Selection for DMA Channel 4 REQ

Figure 6-71 UDMACH4BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Ah
Table 6-77 UDMACH4BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2AhRead only selection value
2Ah = SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE

6.7.2.63 UDMACH5SSEL Register (Offset = 528h) [Reset = 00000035h]

UDMACH5SSEL is shown in Figure 6-72 and described in Table 6-78.

Return to the Summary Table.

Output Selection for DMA Channel 5 SREQ

Figure 6-72 UDMACH5SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-35h
Table 6-78 UDMACH5SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR35hRead only selection value
35h = UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE

6.7.2.64 UDMACH5BSEL Register (Offset = 52Ch) [Reset = 00000034h]

UDMACH5BSEL is shown in Figure 6-73 and described in Table 6-79.

Return to the Summary Table.

Output Selection for DMA Channel 5 REQ

Figure 6-73 UDMACH5BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-34h
Table 6-79 UDMACH5BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR34hRead only selection value
34h = UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE

6.7.2.65 UDMACH6SSEL Register (Offset = 530h) [Reset = 00000037h]

UDMACH6SSEL is shown in Figure 6-74 and described in Table 6-80.

Return to the Summary Table.

Output Selection for DMA Channel 6 SREQ

Figure 6-74 UDMACH6SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-37h
Table 6-80 UDMACH6SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR37hRead only selection value
37h = UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE

6.7.2.66 UDMACH6BSEL Register (Offset = 534h) [Reset = 00000036h]

UDMACH6BSEL is shown in Figure 6-75 and described in Table 6-81.

Return to the Summary Table.

Output Selection for DMA Channel 6 REQ

Figure 6-75 UDMACH6BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-36h
Table 6-81 UDMACH6BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR36hRead only selection value
36h = UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE

6.7.2.67 UDMACH7SSEL Register (Offset = 538h) [Reset = 00000075h]

UDMACH7SSEL is shown in Figure 6-76 and described in Table 6-82.

Return to the Summary Table.

Output Selection for DMA Channel 7 SREQ

Figure 6-76 UDMACH7SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-75h
Table 6-82 UDMACH7SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR75hRead only selection value
75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL

6.7.2.68 UDMACH7BSEL Register (Offset = 53Ch) [Reset = 00000076h]

UDMACH7BSEL is shown in Figure 6-77 and described in Table 6-83.

Return to the Summary Table.

Output Selection for DMA Channel 7 REQ

Figure 6-77 UDMACH7BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-76h
Table 6-83 UDMACH7BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR76hRead only selection value
76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL

6.7.2.69 UDMACH8SSEL Register (Offset = 540h) [Reset = 00000074h]

UDMACH8SSEL is shown in Figure 6-78 and described in Table 6-84.

Return to the Summary Table.

Output Selection for DMA Channel 8 SREQ
Single request is ignored for this channel

Figure 6-78 UDMACH8SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-74h
Table 6-84 UDMACH8SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR74hRead only selection value
74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START

6.7.2.70 UDMACH8BSEL Register (Offset = 544h) [Reset = 00000074h]

UDMACH8BSEL is shown in Figure 6-79 and described in Table 6-85.

Return to the Summary Table.

Output Selection for DMA Channel 8 REQ

Figure 6-79 UDMACH8BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-74h
Table 6-85 UDMACH8BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR74hRead only selection value
74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START

6.7.2.71 UDMACH9SSEL Register (Offset = 548h) [Reset = 00000045h]

UDMACH9SSEL is shown in Figure 6-80 and described in Table 6-86.

Return to the Summary Table.

Output Selection for DMA Channel 9 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS

Figure 6-80 UDMACH9SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-45h
Table 6-86 UDMACH9SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W45hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
45h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.72 UDMACH9BSEL Register (Offset = 54Ch) [Reset = 0000004Dh]

UDMACH9BSEL is shown in Figure 6-81 and described in Table 6-87.

Return to the Summary Table.

Output Selection for DMA Channel 9 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS

Figure 6-81 UDMACH9BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-4Dh
Table 6-87 UDMACH9BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W4DhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.73 UDMACH10SSEL Register (Offset = 550h) [Reset = 00000046h]

UDMACH10SSEL is shown in Figure 6-82 and described in Table 6-88.

Return to the Summary Table.

Output Selection for DMA Channel 10 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS

Figure 6-82 UDMACH10SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-46h
Table 6-88 UDMACH10SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W46hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
46h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.74 UDMACH10BSEL Register (Offset = 554h) [Reset = 0000004Eh]

UDMACH10BSEL is shown in Figure 6-83 and described in Table 6-89.

Return to the Summary Table.

Output Selection for DMA Channel 10 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS

Figure 6-83 UDMACH10BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-4Eh
Table 6-89 UDMACH10BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W4EhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.75 UDMACH11SSEL Register (Offset = 558h) [Reset = 00000047h]

UDMACH11SSEL is shown in Figure 6-84 and described in Table 6-90.

Return to the Summary Table.

Output Selection for DMA Channel 11 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS

Figure 6-84 UDMACH11SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-47h
Table 6-90 UDMACH11SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W47hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
47h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.76 UDMACH11BSEL Register (Offset = 55Ch) [Reset = 0000004Fh]

UDMACH11BSEL is shown in Figure 6-85 and described in Table 6-91.

Return to the Summary Table.

Output Selection for DMA Channel 11 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS

Figure 6-85 UDMACH11BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-4Fh
Table 6-91 UDMACH11BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W4FhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.77 UDMACH12SSEL Register (Offset = 560h) [Reset = 00000048h]

UDMACH12SSEL is shown in Figure 6-86 and described in Table 6-92.

Return to the Summary Table.

Output Selection for DMA Channel 12 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS

Figure 6-86 UDMACH12SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-48h
Table 6-92 UDMACH12SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W48hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
48h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.78 UDMACH12BSEL Register (Offset = 564h) [Reset = 00000050h]

UDMACH12BSEL is shown in Figure 6-87 and described in Table 6-93.

Return to the Summary Table.

Output Selection for DMA Channel 12 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS

Figure 6-87 UDMACH12BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-50h
Table 6-93 UDMACH12BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W50hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted

6.7.2.79 UDMACH13BSEL Register (Offset = 56Ch) [Reset = 00000003h]

UDMACH13BSEL is shown in Figure 6-88 and described in Table 6-94.

Return to the Summary Table.

Output Selection for DMA Channel 13 REQ

Figure 6-88 UDMACH13BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-3h
Table 6-94 UDMACH13BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR3hRead only selection value
3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV

6.7.2.80 UDMACH14BSEL Register (Offset = 574h) [Reset = 00000001h]

UDMACH14BSEL is shown in Figure 6-89 and described in Table 6-95.

Return to the Summary Table.

Output Selection for DMA Channel 14 REQ

Figure 6-89 UDMACH14BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-1h
Table 6-95 UDMACH14BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W1hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
8h = Interrupt event from I2S
9h = Interrupt event from I2C
Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
Ch = GPT2A interrupt event, controlled by GPT2:TAMR
Dh = GPT2B interrupt event, controlled by GPT2:TBMR
Eh = GPT3A interrupt event, controlled by GPT3:TAMR
Fh = GPT3B interrupt event, controlled by GPT3:TBMR
10h = GPT0A interrupt event, controlled by GPT0:TAMR
11h = GPT0B interrupt event, controlled by GPT0:TBMR
12h = GPT1A interrupt event, controlled by GPT1:TAMR
13h = GPT1B interrupt event, controlled by GPT1:TBMR
14h = DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
16h = DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event.
MCU domain wakeup control AON_EVENT:MCUWUSEL
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
1Fh = PKA Interrupt event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS
27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE
28h = SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
29h = SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
2Ah = SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
2Bh = SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
2Ch = SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE
2Dh = SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE
2Eh = SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE
2Fh = SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE
30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE
31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE
32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE
33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE
34h = UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE
35h = UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE
36h = UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE
37h = UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here.
56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here.
57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here.
58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here.
59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here.
5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL
5Eh = CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE
63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE
64h = Software event 0, triggered by SWEV.SWEV0
65h = Software event 1, triggered by SWEV.SWEV1
66h = Software event 2, triggered by SWEV.SWEV2
67h = Software event 3, triggered by SWEV.SWEV3
68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START
75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL
76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
78h = CPU halted
79h = Always asserted

6.7.2.81 UDMACH15BSEL Register (Offset = 57Ch) [Reset = 00000007h]

UDMACH15BSEL is shown in Figure 6-90 and described in Table 6-96.

Return to the Summary Table.

Output Selection for DMA Channel 15 REQ

Figure 6-90 UDMACH15BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-7h
Table 6-96 UDMACH15BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR7hRead only selection value
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting

6.7.2.82 UDMACH16SSEL Register (Offset = 580h) [Reset = 0000002Dh]

UDMACH16SSEL is shown in Figure 6-91 and described in Table 6-97.

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Output Selection for DMA Channel 16 SREQ

Figure 6-91 UDMACH16SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Dh
Table 6-97 UDMACH16SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2DhRead only selection value
2Dh = SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE

6.7.2.83 UDMACH16BSEL Register (Offset = 584h) [Reset = 0000002Ch]

UDMACH16BSEL is shown in Figure 6-92 and described in Table 6-98.

Return to the Summary Table.

Output Selection for DMA Channel 16 REQ

Figure 6-92 UDMACH16BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Ch
Table 6-98 UDMACH16BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2ChRead only selection value
2Ch = SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE

6.7.2.84 UDMACH17SSEL Register (Offset = 588h) [Reset = 0000002Fh]

UDMACH17SSEL is shown in Figure 6-93 and described in Table 6-99.

Return to the Summary Table.

Output Selection for DMA Channel 17 SREQ

Figure 6-93 UDMACH17SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Fh
Table 6-99 UDMACH17SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2FhRead only selection value
2Fh = SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE

6.7.2.85 UDMACH17BSEL Register (Offset = 58Ch) [Reset = 0000002Eh]

UDMACH17BSEL is shown in Figure 6-94 and described in Table 6-100.

Return to the Summary Table.

Output Selection for DMA Channel 17 REQ

Figure 6-94 UDMACH17BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-2Eh
Table 6-100 UDMACH17BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR2EhRead only selection value
2Eh = SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE

6.7.2.86 UDMACH21SSEL Register (Offset = 5A8h) [Reset = 00000064h]

UDMACH21SSEL is shown in Figure 6-95 and described in Table 6-101.

Return to the Summary Table.

Output Selection for DMA Channel 21 SREQ

Figure 6-95 UDMACH21SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-64h
Table 6-101 UDMACH21SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR64hRead only selection value
64h = Software event 0, triggered by SWEV.SWEV0

6.7.2.87 UDMACH21BSEL Register (Offset = 5ACh) [Reset = 00000064h]

UDMACH21BSEL is shown in Figure 6-96 and described in Table 6-102.

Return to the Summary Table.

Output Selection for DMA Channel 21 REQ

Figure 6-96 UDMACH21BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-64h
Table 6-102 UDMACH21BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR64hRead only selection value
64h = Software event 0, triggered by SWEV.SWEV0

6.7.2.88 UDMACH22SSEL Register (Offset = 5B0h) [Reset = 00000065h]

UDMACH22SSEL is shown in Figure 6-97 and described in Table 6-103.

Return to the Summary Table.

Output Selection for DMA Channel 22 SREQ

Figure 6-97 UDMACH22SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-65h
Table 6-103 UDMACH22SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR65hRead only selection value
65h = Software event 1, triggered by SWEV.SWEV1

6.7.2.89 UDMACH22BSEL Register (Offset = 5B4h) [Reset = 00000065h]

UDMACH22BSEL is shown in Figure 6-98 and described in Table 6-104.

Return to the Summary Table.

Output Selection for DMA Channel 22 REQ

Figure 6-98 UDMACH22BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-65h
Table 6-104 UDMACH22BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR65hRead only selection value
65h = Software event 1, triggered by SWEV.SWEV1

6.7.2.90 UDMACH23SSEL Register (Offset = 5B8h) [Reset = 00000066h]

UDMACH23SSEL is shown in Figure 6-99 and described in Table 6-105.

Return to the Summary Table.

Output Selection for DMA Channel 23 SREQ

Figure 6-99 UDMACH23SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-66h
Table 6-105 UDMACH23SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR66hRead only selection value
66h = Software event 2, triggered by SWEV.SWEV2

6.7.2.91 UDMACH23BSEL Register (Offset = 5BCh) [Reset = 00000066h]

UDMACH23BSEL is shown in Figure 6-100 and described in Table 6-106.

Return to the Summary Table.

Output Selection for DMA Channel 23 REQ

Figure 6-100 UDMACH23BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-66h
Table 6-106 UDMACH23BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR66hRead only selection value
66h = Software event 2, triggered by SWEV.SWEV2

6.7.2.92 UDMACH24SSEL Register (Offset = 5C0h) [Reset = 00000067h]

UDMACH24SSEL is shown in Figure 6-101 and described in Table 6-107.

Return to the Summary Table.

Output Selection for DMA Channel 24 SREQ

Figure 6-101 UDMACH24SSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-67h
Table 6-107 UDMACH24SSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR67hRead only selection value
67h = Software event 3, triggered by SWEV.SWEV3

6.7.2.93 UDMACH24BSEL Register (Offset = 5C4h) [Reset = 00000067h]

UDMACH24BSEL is shown in Figure 6-102 and described in Table 6-108.

Return to the Summary Table.

Output Selection for DMA Channel 24 REQ

Figure 6-102 UDMACH24BSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-67h
Table 6-108 UDMACH24BSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR67hRead only selection value
67h = Software event 3, triggered by SWEV.SWEV3

6.7.2.94 GPT3ACAPTSEL Register (Offset = 600h) [Reset = 0000005Bh]

GPT3ACAPTSEL is shown in Figure 6-103 and described in Table 6-109.

Return to the Summary Table.

Output Selection for GPT3 0

Figure 6-103 GPT3ACAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-5Bh
Table 6-109 GPT3ACAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W5BhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.95 GPT3BCAPTSEL Register (Offset = 604h) [Reset = 0000005Ch]

GPT3BCAPTSEL is shown in Figure 6-104 and described in Table 6-110.

Return to the Summary Table.

Output Selection for GPT3 1

Figure 6-104 GPT3BCAPTSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-5Ch
Table 6-110 GPT3BCAPTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W5ChRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings
5h = Combined event from battery monitor
6h = Combined event from Oscillator control
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting
9h = Interrupt event from I2C
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event
22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS
23h = SSI1 combined interrupt, interrupt flags are found here SSI1:MIS
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here.
5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here.
69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE
6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE
70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN
79h = Always asserted

6.7.2.96 AUXSEL0 Register (Offset = 700h) [Reset = 00000010h]

AUXSEL0 is shown in Figure 6-105 and described in Table 6-111.

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Output Selection for AUX Subscriber 0

Figure 6-105 AUXSEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-10h
Table 6-111 AUXSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W10hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ch = GPT2A interrupt event, controlled by GPT2:TAMR
Dh = GPT2B interrupt event, controlled by GPT2:TBMR
Eh = GPT3A interrupt event, controlled by GPT3:TAMR
Fh = GPT3B interrupt event, controlled by GPT3:TBMR
10h = GPT0A interrupt event, controlled by GPT0:TAMR
11h = GPT0B interrupt event, controlled by GPT0:TBMR
12h = GPT1A interrupt event, controlled by GPT1:TAMR
13h = GPT1B interrupt event, controlled by GPT1:TBMR
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT
79h = Always asserted

6.7.2.97 CM3NMISEL0 Register (Offset = 800h) [Reset = 00000063h]

CM3NMISEL0 is shown in Figure 6-106 and described in Table 6-112.

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Output Selection for NMI Subscriber 0

Figure 6-106 CM3NMISEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR-63h
Table 6-112 CM3NMISEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR63hRead only selection value
63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE

6.7.2.98 I2SSTMPSEL0 Register (Offset = 900h) [Reset = 0000005Fh]

I2SSTMPSEL0 is shown in Figure 6-107 and described in Table 6-113.

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Output Selection for I2S Subscriber 0

Figure 6-107 I2SSTMPSEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-5Fh
Table 6-113 I2SSTMPSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W5FhRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
79h = Always asserted

6.7.2.99 FRZSEL0 Register (Offset = A00h) [Reset = 00000078h]

FRZSEL0 is shown in Figure 6-108 and described in Table 6-114.

Return to the Summary Table.

Output Selection for FRZ Subscriber
The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.

Figure 6-108 FRZSEL0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDEV
R-0hR/W-78h
Table 6-114 FRZSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0EVR/W78hRead/write selection value
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
78h = CPU halted
79h = Always asserted

6.7.2.100 SWEV Register (Offset = F00h) [Reset = 00000000h]

SWEV is shown in Figure 6-109 and described in Table 6-115.

Return to the Summary Table.

Set or Clear Software Events

Figure 6-109 SWEV Register
3130292827262524
RESERVEDSWEV3
R-0hR/W-0h
2322212019181716
RESERVEDSWEV2
R-0hR/W-0h
15141312111098
RESERVEDSWEV1
R-0hR/W-0h
76543210
RESERVEDSWEV0
R-0hR/W-0h
Table 6-115 SWEV Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24SWEV3R/W0hWriting "1" to this bit when the value is "0" triggers the Software 3 event.
23-17RESERVEDR0hReserved
16SWEV2R/W0hWriting "1" to this bit when the value is "0" triggers the Software 2 event.
15-9RESERVEDR0hReserved
8SWEV1R/W0hWriting "1" to this bit when the value is "0" triggers the Software 1 event.
7-1RESERVEDR0hReserved
0SWEV0R/W0hWriting "1" to this bit when the value is "0" triggers the Software 0 event.