SWCU185G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
When the clock loss feature is enabled with the DDI_0_OSC:CTL0.CLK_LOSS_EN and the AON_PMCTL:RESETCTL.CLK_LOSS_EN registers, a detected loss of SCLK_LF results in a system reset. After recovery, the AON_PMCTL:RESETCTL.RESET_SRC register shows clock loss as the source of reset.
The application must set both DDI_0_OSC:CTL0.CLK_LOSS_EN and the AON_PMCTL:RESETCTL.CLK_LOSS_EN in order to enable Clock Loss Detection, it is not enabled after boot.