This tutorial guides through the process of using Xilinx Vivado and Vitis development environments to bring up Serial Peripheral Interface (SPI) and non-timing critical General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design. This guide will demonstrate how to use a Xilinx ZCU102 setup as an example.
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This user guide is a walk-through of complete hardware and software flow to bring up SPI and GPO in a AFE79xx system along with a Xilinx FPGA. The hardware in this case refers to a Xilinx Microblaze processor based block design along with AXI SPI, AXI GPIO and other required peripherals.
The specific step-wise objectives are as follows: