SLAAEO9 October 2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519 , MSPM0L1105
This document introduces the low-power mode of MSPM0, takes measurement of system and peripherals power consumption data based on LP-MSPM0G3507, and gives the guidance about entering and exiting the low-power mode from different peripherals.
EnergyTrace and Code Composer Studio™ are trademarks of Texas Instruments.
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There are two core power domains in MSPM0 devices: PD1 and PD0.
As shown in Figure 1-1, the PD1 domain includes the CPU subsystem, the SRAM memory, PD1 peripherals, and the PD1 peripheral bus, which runs from MCLK (including the DMA) with a maximum frequency of 80MHz. The peripherals on PD1 peripheral bus are commonly high-speed peripherals, and usually consume high power while working. The PD0 domain includes the PD0 peripherals and PD0 bus segment, which runs from ULPCLK and is connected to low-speed peripherals, such as universal asynchronous receiver/transmitter (UART), inter-integrated circuit (I2C), real-time clock (RTC).
MSPM0 MCUs implement a policy-based power and clock management scheme. And in certain low-power mode, PD1 can be disabled to minimize power consumption and the peripherals connected are also disabled.
There are five power modes in MSPM0 devices: RUN, SLEEP, STOP, STANDBY and SHUTDOWN. Figure 1-2 shows the interaction between the modes.
PD1 is only enabled in RUN and SLEEP mode. While PD1 is disabled in STOP and STANDBY mode, the CPU registers, SRAM, and peripheral MMR configuration registers are maintained in retention such that these modules are available to resume operation immediately when STOP or STANDBY modes are exited.
PD0 is powered in all modes except SHUTDOWN mode and can be thought of as an "always-on" domain. PD0 runs from ULPCLK with a max frequency of 40MHz in RUN and SLEEP mode, 4MHz in STOP mode, and 32kHz in STANDBY mode.
Figure 1-3 defines how to configure the relevant policy bits for each operating mode. All values are indicated in binary format. A dash (-) indicates that the particular policy bit is a don't care for the specified operating mode. For the detailed description of these low power modes, please refer to 2.1PMCU Overview of MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual (Rev. A) (ti.com).
In RUN mode, the CPU is active executing code and every peripheral can be enabled.
There are three RUN mode policy options: RUN0, RUN1, and RUN2.
The RUN mode is active after clock configuration by DL_SYSCTL_setPowerPolicyRUNxSLEEPx() API function in MSPM0 SDK, where x is selected from 0/1/2, representing three RUN mode policy options.
In SLEEP mode, the CPU is disabled (clock gated) but otherwise the device configuration is the same as RUN. So the configuration API function of SLEEP mode is as same as RUN mode. The difference is that, SLEEP mode disables CPU running by WFI/WFE instruction.
In STOP mode, the CPU, SRAM, and PD1 peripherals are disabled and in retention (if applicable). PD0 peripherals are available with a max ULPCLK frequency of 4MHz. SYSOSC can run at higher frequencies to support ADC, OPA, or COMP operation, but ULPCLK is automatically limited to the 4MHz SYSOSC output by SYSCTL. High speed oscillators (SYSPLL, HFXT, HFCLK_IN) are automatically disabled.
There are three policy options for STOP mode: STOP0, STOP1, and STOP2.
The STOP mode is configured by DL_SYSCTL_setPowerPolicySTOPx() API function in MSPM0 SDK, where x is selected from 0/1/2, representing three STOP mode policy options. STOP mode configuration is triggered to be valid by WFI/WFE instruction.
In STANDBY mode, the CPU, SRAM, and PD1 peripherals are disabled and in retention. PD0 peripherals, with the exception of the ADC, 12-bit DAC, and OPA, are available with a maximum ULPCLK frequency of 32kHz. High-speed oscillators (SYSPLL, HFXT, HFCLK_IN) and SYSOSC are disabled.
There are two policy options for STANDBY mode: STANDBY0 and STANDBY1.
The STANDBY mode is configured by DL_SYSCTL_setPowerPolicySTANDBYx() API function in MSPM0 SDK, where x is selected from 0/1, representing two STANDBY mode policy options. STANDBY mode configuration is triggered to be valid by WFI/WFE instruction.
In SHUTDOWN mode, no clocks are available. The core regulator is completely disabled and all SRAM and register contents are lost. The BOR and bandgap circuit are disabled.
The device can wake through a wake-up capable IO, a debug connection or NRST.
The XDS110 debug probe has on-board circuitry that can be used for measuring the target’s energy consumption. The hardware circuitry provides high-accuracy energy consumption with low bandwidth current and power profile. The energy profiling range covers 1μA to 100mA current draw, above which the tool can display an overcurrent message and shutdown. This tool is designed for characterizing energy consumption, but not for capturing short current spikes, because sampling occurs over large time windows (about 500μs).
For more details of EnergyTrace introduction, see 3.6 Energy Trace of XDS110 Debug Probe (ti.com.cn).
To start the EnergyTrace tool automatically on launching debug session, follow the steps of “Window - Preferences - Code Composer Studio™ - EngergyTrace Technology” in CCS. Enable the checkbox for “Enable Auto-launch on target connect”.
Alternatively, if the EnergyTrace tool must be started after establishing a debug connection, then when the core is connected, set the target connection as XDS110.
And, Figure 1-6 shows the fast launch method of EnergyTrace tool embedded in CCS. In this way, the current that XDS110 debug probe supplies to MCU system board can be measured and shown in “Current” windows. The data can be also exported, and analyzed external.
Table 2-1 shows the hardware/software configuration and test results of MSPM0G350x system power consumption measurement under different low-power mode. The power consumption of MSPM0 without any peripheral enabled is strongly related to the clock configuration. For reference, SYSOSC, MCLK, ULPCLK is listed under a different low-power policy.
Low-Power Mode | Configuration | Current | |||
---|---|---|---|---|---|
Low-Power Policy | SYSOSC | MCLK | ULPCLK | ||
Hardware |
|
||||
Software |
|
||||
Low Power Policy | Standby1 + WFI | DIS | DIS | 32kHz | 1.5uA |
Standby0 + WFI | DIS | DIS | 32kHz | 1.9uA | |
Stop2 + WFI | DIS | DIS | 32kHz | 46uA | |
Stop1 + WFI | 4MHz | DIS | 4MHz | 182uA | |
Stop0 + WFI | 32MHz | DIS | 4MHz | 346uA | |
RUN2SLEEP2 + WFI | DIS | 32kHz | 32kHz | 293uA | |
RUN2SLEEP2 + while (1) {} | DIS | 32kHz | 32kHz | 294uA | |
RUN1SLEEP1 + WFI | 32MHz | 32kHz | 32kHz | 535uA | |
RUN1SLEEP1+ while (1) {} | 32MHz | 32kHz | 32kHz | 536uA | |
RUN0SLEEP0 + WFI (SYSOSC=32MHz) | 32MHz | 32MHz | 32MHz | 1.36mA | |
RUN0SLEEP0 + while (1) {} (SYSOSC=32MHz) | 32MHz | 32MHz | 32MHz | 2.22mA | |
RUN0SLEEP0 + WFI (SYSOSC=4MHz) | 4MHz | 4MHz | 4MHz | 456uA | |
RUN0SLEEP0 + while (1) {} (SYSOSC=4MHz) | 4MHz | 4MHz | 4MHz | 569uA |
Table 3-1 summarizes key peripheral power consumption data of MSPM0G350x. For details of each peripheral power test performance, see the following sections.
The following provides an explanation of the two-power value in the table:
Peripherals | Clock | Power Consumption | ||
---|---|---|---|---|
SYSOSC = 32MHz | LPM Power | Static Power in RUN0 | ||
PD0 | UART | ULPCLK=32MHz | 3.5uA | 80uA |
I2C | ULPCLK=32MHz | 2.5uA | 230uA | |
TIMG0 | LFCLK=32kHz | <0.1uA (Running in STOP/STANDBY mode) | ||
RTC/WWDT | LFCLK=32kHz | |||
PD1 | TIMA0 | MCLK=32MHz | 30uA (Static Power in RUN0 mode) | |
SPI | MCLK=32MHz | 4.1uA | 170uA | |
MCAN | HFCLK=40MHz | 10.6uA | 480uA | |
Analog | SYSPLL | SYSPLL2x =32MHz | 38uA (LPM Power in STANDBY1 mode) | |
VREF | MCLK=32MHz | 9.0uA | 80uA | |
ADC | MCLK=32MHz | 2.5uA | 60uA |
The following sectors give the power consumption test results of different peripherals. The common hardware and software configuration are shown as below and the following sectors only point the specific configuration of corresponding peripheral:
GPIO | Configuration | Current |
---|---|---|
Hardware |
|
|
Test condition | Not configuring unused pins | 1.8uA |
Configuring unused pins as output low | 1.8uA | |
Configuring unused pins as input with pulldown resistor | 1.8uA | |
Configuring unused pins as input without internal resistor | 4.0mA |
According to the table, when configuring pins as input without internal resistor, there is large power consumption unexpected. So for the pins unused, the key point to decrease the power waste is not to configure these pins as floating input, so it is a valid way to make the input GPIO function to be pull down internal or external.
When pins are used in peripherals, especially as input pins, the floating of an input pins brings a lot unexpected power consumption or even make the peripheral active in low-power mode. It is also recommended to configured the peripheral input pin to pullup or pulldown according.
For any pin in MSPM0, a valid way to disconnect the pin to other parts is configuring the pin as analog input by DL_GPIO_initPeripheralAnalogFunction(). In this case, the pin is not configured as input or output, and only leaves the connecting path to analog peripherals.