The surge test is performed to make sure the system is immune to surges produced by lightning strikes and power system transients such as capacitor bank switching, short circuits and arcing faults. Surge testing is one of the highest energy pulse tests done on the system.

Typical traditional surge and front-end protection circuits used in a PLC system are shown in Figure 1-1. Input side passive components like common mode choke, series inductor and capacitors are used to reduce slew rate of the surge pulse. A string of TVS diodes is used to clamp the surge magnitude to an acceptable level. A series diode or an OR-ing controller with an external FET is used to protect the downstream from negative voltages. Negative voltages are most common either due to miswiring or a negative surge pulse. Discrete or semi-integrated solutions are used for hot-swap, inrush control, monitoring, undervoltage (UV) and overvoltage (OV) protection.

Figure 1-1 Traditional Input Protection Circuits

Figure 1-2 shows catastrophic damage of the board due to protection circuits failure. Probability of the failure is high in a discrete components-based implementation. Selecting a proper integrated protection solution is critical to avoid possible system failure, unwanted downtime and bad reputation of the product.

Figure 1-2 Impact of the Improperly Designed Protection Circuits

Figure 2-1 EFuse Integrated Solution

The eFuse-based surge protection solution is shown in Figure 2-1. It requires only a single TVS diode to protect the PLC from surges. The device does not need any passive wave shaping circuits to reduce slew rate of the surge. It can handle slew rates as fast as 20 V/µs. Built-in back-to-back FETs and reverse polarity protection circuits effectively block negative voltage that can be generated due to a negative surge.

The ±70 V transient absolute maximum ratings of the device enables the use of a single TVS diode for clamping the surge. Overvoltage and undervoltage protection makes sure that the downstream converters are isolated from input when the surge is at peak or valley level. A proprietary high-speed protection algorithm immediately disconnects the output from the input and prevents the surge passing from the input to the output.

Figure 3-1 Efuse Solution Schematic for Surge Protection

The complete schematic of the surge protection solution is shown in Figure 3-1. This protection circuit is designed for a 19.2 V to 28.8 V supply voltage range and 2-A load current. A 28-V reverse standoff voltage TVS in SMC package is used to clamp the surge voltage. When a ±500 V, 2Ω surge pulse is applied, the input voltage clamps to a ±44 V maximum. The Internal FET experiences maximum stress during the negative surge event. Maximum voltage across the device is the sum of the input clamp voltage and the output voltage under no load conditions. The maximum device stress at nominal test input voltage is less than the transient absolute maximum rating of the device with the selected TVS.

Figure 4-1 to Figure 4-4 shows the performance of the TPS2660 for positive and negative 500-V, 2-Ω, 8/20-µs surge pulses. The output voltage waveform shows that the device shuts-down and re-starts without operator intervention after all of the surge related oscillations are over and provides criteria B performance. For circuits to give criteria A performance, contact the application engineer on the E2E Forum.

Figure 4-1 +500 V, 2-Ω Surge Performance at V_IN = 24 V and Load = 16 Ω

Figure 4-2 Zoom at the Instance of Surge Application

Figure 4-3 –500 V, 2-Ω Surge Performance at V_IN = 24 V and Load = 16 Ω

Figure 4-4 Zoom at the Instance of Surge Application