SLVA857B July 2018 – January 2023 TPS50601-SP , TPS50601A-SP , TPS7H1101-SP , TPS7H1101A-SP , TPS7H3301-SP , TPS7H4001-SP
As aerospace technology continues to develop, the industry has seen a dramatic increase in the lifetime of satellites. With this increase, the operational lifetime of many satellites now surpasses that of the telecom standards they were developed around. Because of this, the need for re-programmability in space applications has also risen [1]. Microsemi® is one company that addresses this need with their SRAM-based FPGA, the RTG4™. Modern FPGAs tend to operate at lower voltages and higher currents than their predecessors, and the RTG4 is no exception. FPGA power supply requirements have become more demanding and features such as soft-start and sequencing are required to avoid large inrush currents that could potentially create problems in the regulators upstream. This application note demonstrates how TI's space qualified power portfolio can be used to power RTG4-based designs.
RTG4™ is a trademark of Microsemi Corporation.
Microsemi® is a registered trademark of Microsemi Corporation.
All trademarks are the property of their respective owners.
All specifications for the RTG4 are taken from Microsemi (RTG4 FPGS Data Sheet (Rev. 4) [3] and application reports [4].
Symbol | Parameter | Min | Typ | Max | Units |
---|---|---|---|---|---|
VDD | DC FPGA core supply voltage. Must always power this pin. | 1.14 | 1.2 | 1.26 | V |
VPP | Power supply for charge pumps (for normal operation and programming). Must always power this pin. | 3.15 | 3.3 | 3.45 | V |
VDDPLL | Power for eight corner PLLs, PLLs in SERDES PCIe/PCS blocks, and FDDR PLL. | 3.15 | 3.3 | 3.45 | V |
SERDES_x_Lyz_VDDAIO | Tx/Rx analog I/O voltage. Low voltage power for lane-y and Lane-z of SERDES_x. It is a +1.2-V SERDES PMA supply. | 1.14 | 1.2 | 1.26 | V |
SERDES_x_Lyz_VDDAPLL | Analog power for SERDES_x PLL lanes yz. It is a +2.5-V SERDES internal PLL supply. | 2.375 | 2.5 | 2.625 | V |
SERDES_VDDI | Power for SERDES reference clock receiver 1.8-V supply. Must always power this pin. | 1.71 | 1.8 | 1.89 | V |
Power for SERDES reference clock receiver 2.5-V supply. Must always power this pin. | 2.375 | 2.5 | 2.625 | ||
Power for SERDES reference clock receiver 3.3-V supply. Must always power this pin. | 3.15 | 3.3 | 3.45 | ||
SERDES_VREF | Reference voltage for SERDES receiver reference clocks. | 0.49 × SERDES_VDDI | 0.5 × SERDES_VDDI | 0.51 × SERDES_VDDI | V |
VDDIx | 1.2-V DC supply voltage for FPGA I/O banks. | 1.14 | 1.2 | 1.26 | V |
1.5-V DC supply voltage for FPGA I/O banks. | 1.425 | 1.5 | 1.575 | ||
1.8-V DC supply voltage for FPGA and JTAG I/O banks. | 1.71 | 1.8 | 1.89 | ||
2.5-V DC supply voltage for FPGA and JTAG I/O banks. | 2.375 | 2.5 | 2.625 | ||
3.3-V DC supply voltage for FPGA and JTAG I/O banks. | 3.15 | 3.3 | 3.45 | ||
DC supply voltage for LVDS25 differential I/O banks. | 2.375 | 2.5 | 2.625 | ||
DC supply voltage for LVDS33 differential I/O banks. | 3.15 | 3.3 | 3.45 | ||
DC supply voltage for BLVDS, MLVDS, Mini- LVDS, RSDS differential I/O banks. | 2.375 | 2.5 | 2.625 | ||
DC supply voltage for LVPECL differential I/O banks. | 3.15 | 3.3 | 3.45 |
The power-up requirements are based on the VDDPLL and the SERDES_x_Lyz_VDDAIO voltage rails. The only way to not have any power-up sequencing requirements are to hold the RTG4 in reset (by asserting DEVRST_N) until the VDDPLL supply reaches its minimum recommended level and to have the SERDES_x_Lyz_VDDAIO supplies tied to VDD. If this cannot be done however, then the RTG4 voltage rails need to be properly sequenced. In this case, the following requirements apply:
There is no power-down requirement if an external 1-kΩ pull-down resistor is used for each critical output that cannot tolerate an output glitch during power-down or DEVRST_N assertion.
Microsemi has a development kit intended to demonstrate the capabilities of the RTG4 and expedite software development. The power distribution for this development board is shown in Figure 2-1. In this design, Microsemi uses a reset supervisor that holds the FPGA in reset for approximately 150 ms after the 3.3-V, 10-A regulator comes up. This allows sufficient time for all rails to reach regulation before the device begins operation bypassing the need for a power-up sequence. The oscilloscope plot in Figure 2-2 shows the main rails on startup while the device is held in reset. All of the voltage rails come up at the same time and reach their recommended operating points before the reset supervisor releases the active low reset.