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This application note uses a typical image sensor to assess three feasible power solutions that need to support the sensor's power sequence requirements. These requirements can be found in the sensor data sheet. Figure 1-1 demonstrates the power up sequence requirement of a typical image sensor. AVDD 2.8 V must power up first, followed by DOVDD 1.8 V, and then DVDD 1.2 V.
Figure 1-2 is the power down sequence requirement of the image sensor. The sequence is the reverse order of the power up sequence: DVDD 1.2 V, followed by DOVDD 1.8 V, and lastly AVDD 2.8 V.
Achieving the power up sequence is often a straightforward process. The bigger design challenge is reversing this sequence to meet the power down requirements. The following sections discuss this challenge in the context of three common power solutions for image sensors. These solutions consist of:
In a power solution using discrete regulators, the power good (PG) output of the previous regulator in the sequence can drive the enable (EN) pin of the next regulator. In this application note, the first regulator is a switching regulator that converts 12 V or 5 V into 3.3 V, for example TI hero products LMR33620 and TPS62160. A low-noise, high-PSRR LDO, such as the LP5907, converts 3.3 V into the AVDD 2.8 V rail for the image sensor. Secondary regulators are also used to convert 3.3 V into DOVDD 1.8 V and DVDD 1.2 V. DOVDD 1.8 V could be supplied by the TPS62260 or TPS62065, while a low cost LDO like the TLV702 or TPS793 supplies DVDD 1.2 V. In this solution, the power up sequence is achieved by routing PG outputs to EN inputs. However, this approach alone cannot satisfy the power down sequence requirement, which must be in the reverse order of the power up sequence.
Capacitors would need to be added control the delay in this circuit to indirectly satisfy the shutdown sequence requirement. This adds cost and size to the solution, which are both critical factors in camera module design.