A typical DLP® automotive projector system as shown in Figure 1-1 uses solid state illumination and a DMD controller such as the DLPC120 or DLPC230 for applications similar to head-up display (HUD) or high-resolution headlight. The controller has an input for video data and an output for DMD data, DMD control signals, and illumination control signals. Each frame of video is read by the controller, processed, and converted to a set of DMD native format bit-planes. These bit-planes set the state of the DMD mirrors and cause light to be reflected toward the projection optics or away from the projection optics. Each bit-plane is associated with an illumination color. Each time a bit-plane is loaded and displayed control signals from the DMD controller enable the correct illuminator. As each bit-plane is loaded, the viewer's vision system combines the bit-planes into a single full color video frame.

While this approach provides the maximum flexibility for system design, it also leads to a number of system requirements that may increase system cost and complexity. This type of system requires a video source such as a CPU/GPU combo that generates the video content or loads it from memory. It may also require a host microcontroller to bring up and configure the DMD controller. The DMD controller itself also requires RAM for either an external or internal frame buffer depending on the controller architecture. If space is a concern then the host processor and GPU may need be located remotely. This requires that a high-speed video bus be added to the system which may include serializers/deserializers along with specialized cables and connectors. While all of this is appropriate where you have a system critical display that requires constantly updated information from the ADAS system such as a HUD, it may not be appropriate for dynamic ground projection displays where only a limited subset of information needs to be displayed for a short period of time.

Figure 2-1 shows a simplified block diagram for a DLP3021-Q1 based dynamic ground projector. The DLP3021-Q1 dynamic ground projection system architecture is designed to reduce the need for external components while still supporting high quality, full color images and animations. To remove the need for a GPU to generate content, the DLPC120-Q1 DMD controller has been replaced with an automotive qualified Xilinx Spartan®-7 FPGA that streams content from SPI flash directly to the DMD.

Rather than processing an arbitrary video stream from a GPU, the FPGA loads pre-processed content directly from a flash device to the DMD array. To load the high resolution DMD quickly enough, a SPI flash part with an octal interface is used to support the bandwidth required. On power-up the FPGA automatically begins loading video content and on power loss the FPGA automatically executes the DMD power down sequence. The overall design and operation process is shown in Figure 2-2.

Videos can be loaded into a tool called DLP Composer which takes each frame of video content and pre-renders them into individual bit-planes in DMD native format. DLP Composer then compresses and combines the individual bit planes, any default start-up conditions, and the FPGA configuration into a single flash binary as shown in Figure 2-3.

When power is applied to the system, the FPGA configuration is loaded to the FPGA. Depending on the default configuration, the FPGA begins loading bit-planes to the DMD and sequencing the LED enables for each bit plane loaded. Alternatively, a microcontroller can issue commands to the FPGA via SPI to enable video playback, change videos, read DMD temperature via the TMP411, or adjust current levels to the LEDs.