2 Dynamic Ground Projection

Figure 2-1 shows a simplified block diagram for a DLP3021-Q1 based dynamic ground projector. The DLP3021-Q1 dynamic ground projection system architecture is designed to reduce the need for external components while still supporting high quality, full color images and animations. To remove the need for a GPU to generate content, the DLPC120-Q1 DMD controller has been replaced with an automotive qualified Xilinx Spartan®-7 FPGA that streams content from SPI flash directly to the DMD.

Rather than processing an arbitrary video stream from a GPU, the FPGA loads pre-processed content directly from a flash device to the DMD array. To load the high resolution DMD quickly enough, a SPI flash part with an octal interface is used to support the bandwidth required. On power-up the FPGA automatically begins loading video content and on power loss the FPGA automatically executes the DMD power down sequence. The overall design and operation process is shown in Figure 2-2.

Videos can be loaded into a tool called DLP Composer which takes each frame of video content and pre-renders them into individual bit-planes in DMD native format. DLP Composer then compresses and combines the individual bit planes, any default start-up conditions, and the FPGA configuration into a single flash binary as shown in Figure 2-3.

When power is applied to the system, the FPGA configuration is loaded to the FPGA. Depending on the default configuration, the FPGA begins loading bit-planes to the DMD and sequencing the LED enables for each bit plane loaded. Alternatively, a microcontroller can issue commands to the FPGA via SPI to enable video playback, change videos, read DMD temperature via the TMP411, or adjust current levels to the LEDs.