DLPU100B May   2020  – June 2024 DLP2021-Q1 , DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

4.4 Host IRQ Interrupt Signal

HOST IRQ is a level interrupt output from the FPGA. Multiple internal interrupt sources can trigger the external interrupt signal. If the signal is low, all of the enabled interrupt sources are cleared. If the signal is high, one of the sources is enabled and has been triggered. Three registers are used for handling the interrupt sources:

  • FPGA Interrupt Enable
  • FPGA Interrupt Set
  • FPGA Interrupt Clear

FPGA Interrupt Enable is used to mask which interrupt sources will trigger the external HOST IRQ signal. For example, if the “video loop complete” enable bit is set to 1, then this source will set HOST IRQ high when triggered. If it is set to 0, then HOST IRQ will not be set high due to this source.

FPGA Interrupt Set is used to read back the currently set interrupts. Once an internal interrupt source is set, it will remain set until it is cleared by writing to the FPGA Interrupt Clear register.

FPGA Interrupt Clear is used to clear interrupt sources once handled. Typically, the FPGA Interrupt Set register can be directly written to the FPGA Interrupt Clear register in order to clear all currently active interrupts. Then, the host MCU can determine what action to take based on the interrupts that were set.

HOST IRQ will remain high if multiple enabled interrupt sources trigger.