DLPU100B May   2020  – June 2024 DLP2021-Q1 , DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

4.1.6 Example 5: Display 3+ Videos/Images Seamlessly

Displaying more than two videos without pause requires host intervention since there are only two sets of configuration registers. The HOST IRQ signal includes interrupt events that can help seamlessly transition to additional video content.

  1. Write FPGA Interrupt Enable register “Video configuration complete” bit.
  2. Read FPGA Interrupt Set register and Write FPGA Interrupt Clear register.
    1. Write 1 to the FPGA Interrupt Clear register to clear any active interrupts that can be holding the HOST IRQ signal high.
  3. Write Video Frame Rate register.
    1. The clock count should match the length of the DMD sequence that is used.
  4. Write Video Start Address 1 register.
    1. Start address should match the location of the first video in Flash memory. This can be found in the build log output from the DLP Composer tool.
  5. Write Video Configuration 1 register.
    1. Frame count = number of frames in the video
    2. Loop count = 1
  6. Write Video Start Address 2 register.
    1. Start address should match the location of the second video in Flash memory. This can be found in the build log output from the DLP Composer tool.
  7. Write Video Configuration 2 register.
    1. Frame count = number of frames in the video
    2. Loop count = 1
  8. Write Video Control register.
    1. Loop configurations = 0
    2. Toggle configurations = 1
    3. Configurations pointer = 0
    4. Play = 1
    5. Stop = 0
    6. Auto-stop = 0
  9. Wait for HOST IRQ signal to interrupt host MCU and read FPGA Interrupt Set register to confirm that “video configuration complete” is a source of the interrupt.
  10. Write Video Start Address 1 register.
    1. Start address should match the location of the third video in flash memory
  11. Write Video Configuration 1 register.
    1. Frame count = number of frames in the video
    2. Loop count = 1
  12. 12. Wait for HOST IRQ signal to interrupt host MCU and read FPGA Interrupt Set register to confirm that “video configuration complete” is a source of the interrupt.
  13. Write Video Control register.
    1. Loop configurations = 0
    2. Toggle configurations = 1
    3. Configurations pointer = 0
    4. Play = 1
    5. Stop = 0
    6. Auto-stop = 0

The first two videos are set up in Video Configuration 1 and 2. Then, the host MCU should wait until the “video configuration complete” interrupt triggers to indicate that the FPGA has swapped to displaying Configuration 2. After this occurs, the host MCU can modify Configuration 1 without affecting the displayed video content. It should then store the settings of the third video in Configuration1 before video 2 completes. After video 2 completes, the FPGA will loop back to configuration 1, which should now be set up to display video 3. This process can be repeated for any desired number of videos or images. After HOST IRQ interrupts to switch to the final video configuration, the Video Control register can be set to auto-stop after completion. When this register is written, do not set the play bit. If the play bit is set at this time, the video configuration would restart at the specified configuration pointer on the next video frame instead of waiting for the current configuration to complete.