DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

4.3.3.12 Single Channel Transfer Mode

For non-critical pattern rate application, the DLPC964 supports operating with only Aurora channel 0. Only the three 10Gbps serial links for channel 0 are used and must be channel 0 in this mode of operation.

GUID-20231113-SS0I-SVLS-SXKV-NRJ7LDJPCRHC-low.png Figure 4-23 System Block Diagram For Single Channel Operation

Operation is enabled by setting Block Control word field, SINGLE_CHANNEL = ‘1’ (Table 4-2 ), and transfer DMD segment in order of 3(first), 2, 1, 0(last) (DMD_SEGMENT field in Table 4-2 ). In other words, to control a particular DMD block, theApps FPGA must operate segment 3 of that block first, follow by segment 2, segment 1, and 0 being the last transfer segment.

The guidelines stated in Section 4.3.3.9, Section 4.3.3.10, and Section 4.3.3.11, still apply to single channel operation mode where each block and segment Aurora transfer must still begin with a Block Control word and end with the DMDLOAD_REQ along with the 300ns setup time. However, one major difference regarding the Apps FPGA/DLPC964 handshaking in this mode is that the actual DMD operation only triggered by the DMDLOAD_REQ corresponds to segment 0; for example, BLKLOADZ is not asserted for segment 3, 2 and 1. (See Figure 4-24 for details).

All four segments of the selected block must be operated and in order of segment 3 (first), 2, 1 and 0 (last), otherwise the DLPC964 do not carry out the proper DMD operation to that block.

GUID-20231113-SS0I-0QVV-Z7S5-73NS7NP9FSH8-low.png Figure 4-24 Single Channel Operation Waveform Example
  1. Apps FPGA Aurora Data Transfer for DMD Block 0 in Single Channel Mode.
    1. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 0 Segment 3
    2. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 0 Segment 2.
    3. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 0 Segment 1.
    4. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 0 Segment 0.
    5. Segment 0’s DMDLOAD_REQ triggers DLPC964 to begin block 0 data loading, assert BLKLOADZ to indicate operation in process.
  2. Apps FPGA Aurora Data Transfer for DMD Block 1 in Single Channel Mode.
    1. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 1 Segment 3.
    2. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 1 Segment 2.
    3. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 1 Segment 1.
    4. Block Control word, DMD data, and DMDLOAD_REQ for DMD block 1 Segment 0.
    5. Segment 0’s DMDLOAD_REQ triggers DLPC964 to begin block 1 data loading, assert BLKLOADZ to indicate operation in process.

Note that there is no data transfer happening on GT channel 1, 2, and 3. Only channel 0 is operated in this Single Channel mode.