The IDAC current, I_IDAC, in conjunction with the nominal bridge resistance, R_BRIDGE, determine the total voltage across the bridge, V_BRIDGE. Assuming zero lead wire resistance, V_BRIDGE = V_EXCITATION = V_EXCITATION+ – V_EXCITATION-, which is also used as the ADC reference voltage, V_REF. Unlike the circuit described in Section 6.1 where V_EXCITATION is fixed, V_BRIDGE varies as R_BRIDGE changes. This varying V_BRIDGE voltage causes V_REF and the input voltage to the ADC to change as well. Additionally, the current source does not inherently center the bridge common-mode voltage, V_CM(Bridge), as it does in other bridge measurement circuits. The bias resistor, R_BIAS, helps keep V_CM(Bridge) within the common-mode range of the ADC analog and voltage reference inputs.

Small variations in R_BRIDGE due to tension or compression cause the differential bridge output voltage to change. The PGA integrated into the ADC gains up this low-level signal to reduce system noise and utilize more of the ADC full-scale range (FSR). The ADC samples and converts this amplified voltage against V_REF, which is the same voltage used to excite the bridge and therefore ratiometric. The excitation source noise and drift are seen equally in both V_IN and V_REF in a ratiometric reference configuration, effectively removing these errors from the ADC output code.

A four-wire resistive bridge measurement with a ratiometric reference and current excitation requires:

• Differential analog inputs (AINP and AINN)
• Differential reference inputs (REFP and REFN)
• Low-noise amplifier
• Constant-current source (IDAC)
• Bias resistor (optional in some cases)

Additionally, a four-wire resistive bridge measurement with a ratiometric reference and current excitation requires consideration of several factors, including:

• Absolute (V_REFP and V_REFN) and differential (V_REF) reference voltages
• Bridge excitation current, I_IDAC
• IDAC compliance voltage
• Bridge common-mode voltage, V_CM(Bridge)
• Voltage across the bridge, V_BRIDGE
• Bridge resistance, R_BRIDGE
• Bias resistor value, R_BIAS

All of these factors are inter-related such that selecting one influences the selection of one or more of the others. Several design iterations can be required to determine a final result that meets all of the system specifications.

To reduce the number of possible circuit configurations, it is recommended to begin the design by choosing an ADC with differential V_REF inputs, integrated IDACs, and a PGA. The absolute and differential V_REF specifications constrain the possible values of V_BRIDGE. Integrated IDACs limit the choice of I_IDAC to several discrete values and eliminate external circuitry to drive the bridge. The integrated IDACs also have a well-defined compliance voltage that helps determine the maximum values of R_BRIDGE and R_BIAS. The integrated PGA typically requires a common-mode voltage of half the analog supply voltage (AVDD / 2) to maximize the amplifier gain and keep the PGA output voltage within the linear range of operation. This sets a target V_CM(Bridge) of AVDD / 2, which helps determine if an R_BIAS resistor is necessary and, if it is, the required value.

For example, the 24-bit ADS1261 integrates all of these necessary features. Figure 6-8 shows the differential and absolute V_REF voltage requirements for the ADS1261. Using a unipolar supply such that AVDD = 5 V and AVSS = 0 V, Figure 6-8 shows that V_REF must be between 0.9 V and 5 V. This bounds the possible values of V_BRIDGE. Additionally, the absolute voltage on V_REFN can extend down to AVSS while the absolute voltage on V_REFP can extend up to AVDD. This wide absolute V_REF voltage range typically does not limit the selection of the other system components, though this should always be verified in each design.

Figure 6-8 ADS1261 V_REF Operating Conditions

Figure 6-9 shows the available IDAC current settings and the compliance voltage for the ADS1261. An IDAC integrated into a precision ADC requires some headroom with AVDD to maintain the current magnitude. Since AVDD = 5 V ±5% for the ADS1261, the IDAC compliance voltage = AVDD – 1.1 V = 3.9 V. This value sets an upper bound on R_BRIDGE + R_BIAS as well as I_IDAC.

Figure 6-9 ADS1261 IDAC Current Settings and Compliance Voltage

To determine if V_CM(Bridge) is within the PGA linear region of operation, Section 6.3.4 introduced the ADS1261 Excel Calculator that plots the PGA output to reveal if the input parameters are valid. It is also possible to select a desired target value such as V_CM(Bridge) = AVDD / 2 and design the rest of the system around this common-mode voltage. After the specific ADC operating conditions have been defined, begin selecting the remaining system component values.

For this example, assume that R_BRIDGE can be any one of four common bridge resistance values: 120 Ω, 350 Ω, 1 kΩ, or 3.5 kΩ. Then, use the ADS1261 IDAC values given in Figure 6-9 to determine V_BRIDGE using the equation in Table 6-19. Table 6-12 calculates V_BRIDGE for all possible combinations of I_IDAC and R_BRIDGE.

Assuming no lead resistance, V_BRIDGE = V_REF. Therefore, Table 6-12 also highlights in green all possible system combinations where 0.9 V < V_BRIDGE < 5 V, as per the ADS1261 requirements. Out of the 40 possible combinations, only nine remain.

Next, determine the possible values of R_BIAS for each of the remaining nine combinations by choosing a value for V_CM(Bridge). This example uses V_CM(Bridge) = AVDD / 2, though other voltages are possible. Always ensure that the PGA common-mode and absolute voltage requirements are met for the target gain value.

As per Table 6-19, V_CM(Bridge) = V_BRIDGE / 2 + V_BIAS, V_BRIDGE = I_IDAC • R_BRIDGE, and V_BIAS = I_IDAC • R_BIAS. Rearranging these equations helps determine R_BIAS in terms of I_IDAC, R_BRIDGE, and AVDD, as per Equation 60:

One important detail about Equation 60 is that R_BIAS can be 0 Ω such that the V_CM(Bridge) equation simplifies to V_CM(Bridge) = V_BRIDGE / 2. In other words, it is possible to eliminate the R_BIAS resistor as long as the ADC and system requirements can still be met. However, this example assumes an R_BIAS resistor is necessary. In either case, the next step is to calculate V_COMPLIANCE using the equation from Table 6-19. Table 6-13 reports the calculated values of R_BIAS and V_COMPLIANCE for each of the nine valid combinations in Table 6-12. Additionally, Table 6-13 highlights in green the values of V_COMPLIANCE that are within the ADS1261 IDAC compliance voltage of 3.9 V.

As Table 6-13 shows, seven of the original nine combinations are within the IDAC 3.9-V compliance voltage specified by the ADS1261. Any of these options could be used in the final design. For example, Figure 6-10 shows a system where R_BRIDGE = 1 kΩ, R_BIAS = 2 kΩ, and I_IDAC = 1 mA. The IDAC current path is highlighted in red and the resulting system voltages are highlighted in blue.

Figure 6-10 Current-Excited Bridge Measurement Using R_BRIDGE = 1 kΩ, R_BIAS = 2 kΩ, and I_IDAC = 1 mA

One important result from Figure 6-10 that was not previously-discussed is that V_BRIDGE = V_REF = 1 V. In other words, the current-excited system has V_EXCITATION = 1 V, while a voltage-excited system typically has V_EXCITATION ≥ 5 V. Assuming each bridge has the same sensitivity, the output voltage from the current-excited bridge is 20% compared to the voltage-excited bridge. This can reduce the dynamic range of the system to an unacceptable level given the system noise targets. In this case, repeat the design process using a different ADC, a discrete current source, or a wider range of R_BRIDGE values.

After the system configuration has been selected, identify the maximum differential output voltage of the bridge, V_{OUT(Bridge Max)}, using the equation from Table 6-19 and parameters from Table 6-18. This value provides the maximum output voltage possible from the bridge under normal operating conditions and corresponds to the maximum load that can be applied to the bridge, Load_{(Bridge Max)}. If the system does not use the entire output range of the bridge, V_{OUT(System Max)} defines the maximum differential output signal that is applied to a specific system and Load_{(System Max)} is the corresponding maximum load. For example, if V_{OUT(Bridge Max)} corresponds to Load_{(Bridge Max)} = 5 kg, but the system specifications only require that Load_{(System Max)} = 2.5 kg, then V_{OUT(System Max)} is given by Equation 61:

Note that if Load_{(System Max)} = Load_{(Bridge Max)}, then V_{OUT(System Max)} = V_{OUT(Bridge Max)}.

After V_{OUT(System Max)} has been determined, choose the corresponding gain value for the ADC PGA. The maximum gain value is limited by the previously-selected value of V_CM(Bridge) and the ADC FSR. The amplifier gain should be the largest allowable value that keeps the PGA output voltage within the linear range of operation given the V_CM(Bridge) voltage and is less than the ADC FSR. In some cases it is not possible to choose an amplifier gain that uses the entire ADC FSR. While this is often an acceptable tradeoff between resolution and ease-of-use, care should be taken to ensure that all system requirements are still met when the ADC FSR cannot be maximized.

Finally, follow the instructions in Section 5.5 if calibration is required.