SBAA607A December   2023  – January 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1 , AMC1303M2520 , AMC1305L25 , AMC1306M25 , F29H850TU , F29H859TU-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenge With Digital Interface Timing Specifications
  6. 3Design Approach With Clock Edge Delay Compensation
    1. 3.1 Clock Signal Compensation With Software Configurable Phase Delay
    2. 3.2 Clock Signal Compensation With Hardware Configurable Phase Delay
    3. 3.3 Clock Signal Compensation by Clock Return
    4. 3.4 Clock Signal Compensation by Clock Inversion at the MCU
  7. 4Test and Validation
    1. 4.1 Test Equipment and Software
    2. 4.2 Testing of Clock Signal Compensation With Software Configurable Phase Delay
      1. 4.2.1 Test Setup
      2. 4.2.2 Test Measurement Results
    3. 4.3 Testing of Clock Signal Compensation by Clock Inversion at MCU
      1. 4.3.1 Test Setup
      2. 4.3.2 Test Measurement Results
        1. 4.3.2.1 Test Result – No Clock Inversion of Clock Input at GPIO123
        2. 4.3.2.2 Test Result – Clock Inversion of Clock Input at GPIO123
    4. 4.4 Digital Interface Timing Validation by Calculation Tool
      1. 4.4.1 Digital Interface With No Compensation Method
      2. 4.4.2 Commonly Used Method - Reduction of the Clock Frequency
      3. 4.4.3 Clock Edge Compensation With Software Configurable Phase Delay
  8. 5Conclusion
  9. 6References
  10. 7Revision History

5 Conclusion

Clock edge delay compensation helps to meet setup and hold time requirements with isolated Delta-Sigma modulators and the MCUs digital interface without the necessity of reducing the modulator clock frequency. This allows the system to operate at full performance.

The clock edge delay compensation can be implemented by various methods these are compensation by:

  • Additional Clock Signal with software configurable phase delay
  • Clock Signal with hardware configurable phase delay
  • Clock Return
  • Clock Inversion at MCU

Compensation methods such as additional clock signal with software configurable phase delay and clock inversion at MCU were analyzed in more detail for the most common used isolated Delta-Sigma modulator variants and validated with AMC1306EVM evaluation module and C2000 TMS320F28379D Launchpad as well as Sitara AM243x Launchpad chosen as MCUs. The test results hold true for MCUs with CMOS interface and SDFM as well as for Sitara MCUs with no SDFM when working with PRU.

Table 5-1 shows the benefits and drawbacks of each clock signal compensation method. In the following the abbreviations SW Phase Delay and HW Phase Delay are used for compensation with software configurable phase delay and hardware configurable phase delay.

Table 5-1 Comparison of clock edge compedation methods
Method Benefits Drawbacks
SW Phase delay
  • Compensation of any propagation delays
  • Allows the use of the maximum clock frequency enabling highest reliable communication
  • Implementation of precise phase delays
  • Change during run-time possible
  • No additional BoM cost
  • One additional MCU GPIO and internal phase locked clock source is required
  • Additional MCU software
HW Phase delay
  • No change of MCU software
  • No additional MCU GPIO is required
  • Compensation dependent on implemented hardware delay hardware
  • Tolerance in the precision of phase delay by hardware components
  • No changes during run-time possible
  • Adds BoM cost
Clock Return
  • No software and hardware efforts
  • Does not work for all configurations
  • Adaptation of the layout
  • Longer clock signal more sensitive to transient noise
Clock Inversion
  • Simple implementation, if compensation by one half of the clock period solves the timing differences
  • Does not work for all configurations
  • Fixed compensation by one half of the clock period only
  • MCU needs to be capable of inverting the clock signal at the GPIO input

Depending on the type of the Delta-Sigma Modulator, differentiated by external or internal clock source and CMOS or LVDS interface, different clock signal compensation methods can be better than others. Table 5-2 compares the suggested compensation methods for each type of Delta-Sigma modulator which are commonly used.

Table 5-2 Suggested clock edge compensation methods for modulators with internal or external clock

Method

AMC1306M25

external clock (CMOS)

AMC1305L25

external clock (LVDS)

AMC1303M2520/10

internal clock (CMOS)
Software Phase Delay + + N/A
Hardware Phase Delay o o o
Clock Return o - N/A
Clock Inversion o o +

For modulators which require an external clock, the clock signal compensation with software configurable phase delay offers the best performance, followed by the clock inversion at the MCU, if a fixed one-half of clock cycle meets the requirements. Both of these clock signal compensation methods help to meet the setup and hold timing requirements of the MCU especially at higher modulator clock frequencies. The following calculation tool can be used to validate the setup and hold timing requirements of the MCU when using the Delta-Sigma modulator AMC1306M25 and AMC1305L25.