5 Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance

One of the bigger contributors to noise from a phase noise curve is the noise floor, otherwise known as broadband noise. If a source has a higher noise floor than another source, then the source with the higher noise floor increases the area under the phase noise curve, and as a result, increase the jitter value for a specified integration bandwidth.

In general, bandpass filters (BPF) lower the broadband noise of a clock signal or a signal source. BPF also help to inherently filter out an unwanted spurious, even at times generated by high-performance, low-noise signal generators. However, keep in mind that BPF can also lower the slew rate of a signal. Therefore, one needs to increase the clock signal relative to the loss of the filter to keep the slew rate high. Figure 5-1 shows the phase noise curves of three different signal generators phase noise plots with and without bandpass filtering applied. The bandpass filter used for the experiment was centered around 25MHz with a bandpass of 10%. Notice the improved performance drop in the broadband noise beyond 1MHz, which indicates that using a BPF generally results in a cleaner broadband, lower-jitter clock signal (while the clock slew rate degradation is not significant enough to affect the ADC performance).

Figure 5-1 Phase Noise Curves of Different Signal Sources With and Without Filtering Applied

Looking at the filter example in a different way, Figure 5-2 demonstrates the ADC3683’s SNR performance versus analog input frequency using these same three signal generators for the sampling clock, both when filtered and unfiltered. The SNR improvement is clearly seen when applying a filter on the output of the signal generator used for the clock. This is especially illustrated when applying a filter on a lower-performing signal generator with a higher noise floor, where the inherent phase noise is pretty poor to begin with.

Figure 5-2 SNR of the ADC3683 When Filtering vs. no Filtering Applied With Different Clock Signal Sources

So far, signal generators have been used to demonstrate the various tradeoffs of clocking signals. However, in the real world, most designers choose a specific clocking device for an ADC design. In some cases, the designer wants to use an FPGA for the ADC sampling clock. However, this is not recommended. FPGA clock outputs have significant additive jitter as compared to most of TI clocking portfolio. Figure 5-3 illustrates the 25MHz phase noise curves of the FPGA output clock and the following TI clock products: LMX2572, LMK04832, LMX2571, CDCE6214, and the LMK3H0102. Figure 5-4 demonstrates the test setup used for the clocking devices. The phase noise curve of the FPGA clock (green curve) is worse as compared to any of the TI clocking devices shown, especially at the noise floor. Using an FPGA as an ADC sampling clock is not a good design choice and is not recommended if the converter’s data sheet performance, or similar, is required. Keep in mind that TI clock devices’ performance can range based on configuration, which directly affect the device’s phase noise curve.

Figure 5-3 Phase Noise Curves of Several TI Clock Devices vs. a FPGA Output Clock

Figure 5-4 ADC With Clock Device Test Measurement Setup in the Lab

Figure 5-5 demonstrates the effect on the ADC SNR performance when clocking the ADC3683 with the FPGA output clock against the previously mentioned TI clocking devices. Figure 5-5 confirms that a clock source with a higher phase noise and noise floor can significantly affect the performance of a converter. To achieve the ADC3683’s high SNR data sheet performance, the ADC was clocked with a passive device, for example, transformer or balun, instead of an active device, such as TI clocking parts or other. Using an active device further introduces noise and degrades the ADC performance. However, even though using passive devices results in best performance, passive devices are bigger, more expensive and don’t have good drive capacity. This typically moves engineers away from using passive clock devices on their system design and instead leads them to choose an active clocking device that is good enough to meet the required performance. As previously mentioned, filtering can also be employed to the active clock design and can result in bettering the ADC performance. In this experiment however, this was not done because of the complexity of adding a BPF to P and N outputs due to extensive modifications that need to be completed either on board or off board.

Figure 5-5 TI Clock Devices and FPGA Output Clock vs. ADC3683’s Data Sheet SNR Across Analog input frequencies

Fast-rising signals with high slew rates,like LVPECL or CML interfaces also result in better ADC performance than an LVDS signal. Figure 5-6 illustrates the impact on SNR performance versus frequency for the ADC3683 when using a 25MHz sampling clock source with different output configurations, signaling standards, and a filtered analog input source. The clock device was configured and tested using a differential (DIFF) LVDS and LVPECL style interface and a single-ended (SE) LVCMOS style interface. Differential style interfaces are also primarily better since any common mode noise is inherently canceled. For more on differential vs. single-ended signals, see reference SLLD009. When the clock device was configured to output an LVCMOS signal, the ADC SNR decreased.

Figure 5-6 Clock Device Configured for Various Output Signaling Standards vs. ADC3683’s SNR Performance Across Frequency