SBAA653 October   2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding the Difference Between Phase Noise and Jitter
  6. 3Understanding How Phase Noise or Jitter can Affect the ADC Performance
  7. 4Understanding Clocking Tradeoffs and What this Means to an ADC Performance
  8. 5Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance
  9. 6Summary
  10. 7References
  11.   Appendix A: Choosing a TI Clock Device Based on the TI High-Speed Converter Used

3 Understanding How Phase Noise or Jitter can Affect the ADC Performance

Equation 1 depicts the SNR relationship for an ADC. SNRQ is the ADC inherent quantization, SNRN is the thermal noise of the ADC, and SNRJ is the contributed overall jitter. SNRJ, shown in Equation 4, is a combination of the entire clock signal chain additive jitter and the ADC inherent aperture jitter in relation to the analog input frequency. The following equations clearly demonstrate that the overall SNR performance is not just dependent on the clock jitter alone but a combination of several terms.

Equation 1. S N R A D C   [ d B c ] = - 20   l o g   ⁡   [ 10   - S N R Q 20   ]   2 +   [ 10   - S N R N 20   ]   2 +   [ 10   - S N R J 20   ]   2
Equation 2. S N R Q [ d B c ] = q u a n t i z a t i o n   o f   A D C
Equation 3. S N R N [ d B c ] = t h e r m a l   S N R   o f   A D C
Equation 4. S N R J d B c =   o v e r a l l   j i t t e r   =   - 20   l o g   ⁡ ( 2 × π × f i n × t J )
Equation 5. t J = c o m b i n e d   r m s   j i t t e r =   ( c l o c k   i n p u t   j i t t e r ) 2 +   ( A D C   a p e r t u r e   j i t t e r ) 2

Figure 3-1 simulates Equation 1 using one of the higher performing TI ADC, the ADC3683. Each colored curve represents a different clock jitter value demonstrating how increasing clock jitter decreases the SNR of the ADC3683 across analog input frequencies. Notice that for low analog input frequencies, regardless of the overall sampling clock jitter contribution, the ADC SNR performance is maintained because the ADC quantization and thermal SNR terms are significantly higher than the clock input jitter term. However, as the analog input frequency increases, the SNR starts to drop since the clock input term starts dominating the combined rms jitter term and masking the ADC quantization and thermal SNR, as demonstrated in Equation 4 and Equation 5. Clearly, the amount of SNR degradation highly depends on the overall jitter contribution, the ADC aperture jitter (ADC3683 aperture jitter is 180fs), and the difference in magnitude between the clock input jitter and the ADC aperture jitter. The red dashed line in Figure 3-1demonstrates the best performance that can be achieved by the ADC3683. The green and yellow curves are purely theoretical and cannot be achieved in practice and are meant to further show the relationship between a clock’s jitter and an ADC SNR.

SNR vs. Fin External Clock Jitter Relationship Figure 3-1 SNR vs. Fin External Clock Jitter Relationship

As mentioned before, a better-performing clock is required when higher analog input frequencies are used. This is because increasing the slope or slew rate of the analog input signal leads to a larger conversion error. To compensate for this extra added error, the system requires a less-jittery clock. Figure 3-2 illustrates more clearly how the same clock edge with the same amount of jitter translates to a larger delta error and worse SNR for the same amount of time, as the analog input frequency increases.

Low Analog Input Frequencies vs. the Same Sampling Clock Edge Occurring for the Same Time PeriodFigure 3-2 Low Analog Input Frequencies vs. the Same Sampling Clock Edge Occurring for the Same Time Period
High Analog Input Frequencies vs. the Same Sampling Clock Edge Occurring for the Same Time PeriodFigure 3-3 High Analog Input Frequencies vs. the Same Sampling Clock Edge Occurring for the Same Time Period